A method of cleaning a surface of a silicon wafer includes subjecting the surface of the silicon wafer to a hydrogen (H2) gas plasma containing at least one inert gas while biasing the hydrogen plasma with a rf bias power to direct the hydrogen (H2) plasma to clean the surface of the silicon wafer.
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1. A method of forming a barrier layer of a semiconductor device, comprising:
forming a region heavily doped with p-type impurities on a semiconductor substrate, the heavily doped region being formed employing BF2+ ions;
subjecting a surface of the semiconductor substrate to a first hydrogen plasma containing at least one inert gas while biasing the first hydrogen plasma with a rf bias power to direct the first hydrogen plasma to the surface of the semiconductor substrate, the surface of the semiconductor substrate including at least a portion of the heavily doped region;
evaporating the p-type impurities from the semiconductor substrate by maintaining the first hydrogen plasma at a temperature greater than about 600° C.; and
depositing a refractory metal layer on the surface of the semiconductor substrate.
21. A method of forming a barrier layer of a semiconductor device, comprising:
forming a heavily doped region on a semiconductor substrate, the heavily doped region including p-type impurities;
reducing a surface concentration of the p-type impurities in the heavily doped region by subjecting a surface of the semiconductor substrate to a first hydrogen plasma containing at least one inert gas while biasing the first hydrogen plasma with an rf bias power to direct the first hydrogen plasma to the surface of the semiconductor substrate, the surface of the semiconductor substrate including at least a portion of the heavily doped region;
evaporating the p-type impurities from the semiconductor substrate by maintaining the first hydrogen plasma at a temperature greater than about 600° C.; and
depositing a refractory metal layer on the surface of the semiconductor substrate.
20. A method of forming a barrier layer of a semiconductor device, comprising:
subjecting a surface of a semiconductor substrate to a hydrogen plasma containing at least one inert gas while biasing the hydrogen plasma with a rf bias power to direct the hydrogen plasma to the surface of the semiconductor substrate, the semiconductor substrate including dopant impurities;
evaporating the dopant impurities from the semiconductor substrate by maintaining the first hydrogen plasma at a temperature greater than about 600° C.;
depositing a refractory metal layer on the surface of the semiconductor substrate, the depositing of the refractory metal layer including employing a chemical vapor deposition process;
subjecting the refractory metal layer to a nitridation atmosphere to form a first refractory metal nitride layer on a surface portion of the refractory metal layer; and
forming a second refractory metal nitride layer on the first refractory metal nitride layer employing a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
17. A method of forming a barrier layer of a semiconductor device, comprising:
forming a heavily doped region on a semiconductor substrate, the heavily doped region including p-type impurities;
depositing an insulating layer over the semiconductor substrate;
forming a contact hole through the insulating layer to expose the heavily doped region;
subjecting a surface of the semiconductor substrate to a first hydrogen plasma containing at least one inert gas while biasing the first hydrogen plasma with a rf bias power to direct the first hydrogen plasma to the surface of the semiconductor substrate, the surface of the semiconductor substrate including at least a portion of the heavily doped region;
evaporating the p-type impurities from the semiconductor substrate by maintaining the first hydrogen plasma at a temperature greater than about 600° C.;
depositing a refractory metal layer on the surface of the semiconductor substrate;
subjecting a surface of the refractory metal layer to a second hydrogen plasma containing at least one inert gas while biasing the second hydrogen plasma with the rf bias power to direct the second hydrogen plasma to the surface of the refractory metal layer to remove impurities;
subjecting the refractory metal layer to a nitridation atmosphere to form a first refractory metal nitride layer on a surface portion of the refractory metal layer; and
forming a second refractory metal nitride layer on the first refractory metal nitride layer employing a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
2. The method of forming a barrier layer of a semiconductor device as claimed in
3. The method of forming a barrier layer of a semiconductor device as claimed in
4. The method of forming a barrier layer of a semiconductor device as claimed in
5. The method of forming a barrier layer of a semiconductor device as claimed in
6. The method of forming a barrier layer of a semiconductor device as claimed in
7. The method of forming a barrier layer of a semiconductor device as claimed in
8. The method of forming a barrier layer of a semiconductor device as claimed in
9. The method of forming a barrier layer of a semiconductor device as claimed in
depositing an insulating layer over the semiconductor substrate;
forming a contact hole to expose the heavily doped region;
subjecting the semiconductor substrate to the first hydrogen plasma after forming the heavily doped region;
subjecting a surface of the refractory metal layer to a second hydrogen plasma containing at least one inert gas while biasing the second hydrogen plasma with the rf bias power to direct the second hydrogen plasma to the surface of the refractory metal layer to remove impurities; and
subjecting the refractory metal layer to a nitridation atmosphere to form a refractory metal nitride layer on a surface portion of the refractory metal layer.
10. The method of forming a barrier layer of a semiconductor device as claimed in
11. The method of forming a barrier layer of a semiconductor device as claimed in
12. The method of forming a barrier layer of a semiconductor device as claimed in
13. The method of forming a barrier layer of a semiconductor device as claimed in
depositing the refractory metal layer includes employing a chemical vapor deposition process; and
subjecting the refractory metal layer to a nitridation atmosphere to form a refractory metal nitride layer on a surface portion of the refractory metal layer.
14. The method of forming a barrier layer of a semiconductor device as claimed in
15. The method of forming a barrier layer of a semiconductor device as claimed in
the method further comprising:
treating the refractory metal layer with a second hydrogen plasma to remove impurities in the refractory metal layer; and
treating the refractory metal layer in a nitridation atmosphere to form a refractory metal nitride layer on the refractory metal layer.
16. The method of forming a barrier layer of a semiconductor device as claimed in
18. The method of forming a barrier layer of a semiconductor device as claimed in
19. The method of forming a barrier layer of a semiconductor device as claimed in
depositing a metal layer on the second refractory metal nitride layer while filling the contact hole; and thereafter
patterning the metal layer to form metal contacts over the heavily doped region.
22. The method of forming a barrier layer of a semiconductor device as claimed in
depositing an insulating layer over the semiconductor substrate;
forming a contact hole to expose the heavily doped region;
subjecting the semiconductor substrate to the first hydrogen plasma after forming the heavily doped region;
subjecting a surface of the refractory metal layer to a second hydrogen plasma containing at least one inert gas while biasing the second hydrogen plasma with the rf bias power to direct the second hydrogen plasma to the surface of the refractory metal layer to remove impurities; and
subjecting the refractory metal layer to a nitridation atmosphere to form a refractory metal nitride layer on a surface portion of the refractory metal layer.
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This is a divisional application based on application Ser. No. 10/175,812, filed Jun. 21, 2002, now U.S. Pat. No. 7,169,704 the entire contents of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to the field of semiconductor device manufacturing and, more particularly, to a method for depositing a barrier layer on a semiconductor device.
2. Description of Background Art
In a semiconductor integrated circuit (IC), a high integration density, forces an attendant reduction in the size of individual device elements, such as a channel length of a transistor, an interval between active areas, a wiring width, a wiring interval and, in particular, a size of an electrical contact pad. To obtain a low contact resistance in such a reduced-sized contact pad, the contact pad is generally formed using a metal silicide layer.
The metal silicide layer serves as an ohmic layer which serves as a low resistance interface between a silicon substrate and a metal layer formed on the silicon substrate. The metal silicide layer also serves as a diffusion barrier layer between a metal layer and an underlying semiconductor region or between two metals in a multilevel metal system, which prevents the diffusion of two materials in the metal layer and the underlying semiconductor region into each other. The metal silicide layer is comprised of a material, such as titanium silicide (TiSi2) or a Group-VIII silicides, such as PtSi2, PdSi2, CoSi2, NiSi2 etc. In a conventional semiconductor device using a design rule of 0.25 micron or less, titanium silicide or cobalt silicide (CoSi2) is widely used for the metal silicide layers.
Typically, after depositing a refractory metal layer using a sputtering process, a heat treatment, such as a rapid thermal process (RTP) is used to form the metal silicide layer at the interface of the refractory metal layer and the exposed silicon region.
However, as an aspect ratio (i.e., depth vs. surface opening hole diameter) of a contact hole increases, the use of the sputtering method results in poor step coverage against the stepped portion having a higher aspect ratio, including poor coverage at the bottom of the hole. Thus, forming a layer of metal silicide of a sufficient thickness at the bottom of the contact hole is difficult.
In order to overcome the difficulties of the step coverage including at the bottom of the contact hole due to the use of the sputtering method, deposition of an intermediate refractory metal layer using a chemical vapor deposition (CVD) or a plasma-enhanced CVD (PE-CVD) process has been employed, wherein a metal silicide layer is formed simultaneously with the deposition of the refractory metal layer. According to this method, even if the aspect ratio of the contact hole is high, the refractory metal reacts with silicon in the active region to form a silicide without a subsequent annealing process and results in good step coverage in a simplified process.
Thereafter, a refractory metal layer 20, e.g., a titanium (Ti) layer, is deposited on the sidewall and the bottom of the contact hole 16 and the insulating layer 14 via a CVD or a PE-CVD process. During the deposition, a reaction occurs between silicon and titanium at an interface between the titanium layer 20 and the exposed silicon area 12, whereby a titanium silicide (TiSix) layer is formed. A refractory metal nitride layer, e.g., a titanium nitride (TiN) layer (not shown), is subsequently deposited onto the titanium layer 20 via a CVD process, to form a barrier layer consisting of the titanium layer 20 and the titanium nitride layer. A metal wiring layer 22, comprised of a conductive metal, such as tungsten (W), aluminum (Al) or copper (Cu), is then deposited on the barrier layer and patterned via a photolithographic process or a chemical mechanical polishing (CMP) process to form a metal contact in contact with the heavily doped region 12, e.g., a P+ well.
Disadvantageously, since the heavily doped region 12, e.g., a P+ well, is formed using an ion-implantation process employing BF2+, dopant concentration of the interface material located between the heavily doped region 12, e.g., a P+ well, and the titanium layer 20 (i.e., the surface portion of the substrate) is reduced due to a diffusion of fluorine (F) and boron (B) caused by the thermal budget used during the formation of the titanium silicide layer. In this reaction, diffused fluorine and boron react with the titanium to form materials having high resistivity, e.g., TiBx and TiFx, thereby increasing the contact resistance in the heavily doped region 12, e.g., a P+ well. Due to fluorine diffusion, micro-voids are also created in the titanium silicide layer, which further increases the contact resistance of the heavily doped region 12, e.g., a P+ well.
In addition, if the oxide layer 18 that has grown on the exposed silicon surface is not removed before depositing the barrier layer, the formation of the metal silicide layer becomes non-uniform, which further increases the contact resistance. Thus, before depositing the refractory metal layer such as the titanium layer 20, a pre-cleaning process to remove the native oxide layer 18 should be conducted.
Typically, a pre-cleaning process is performed using wet cleaning equipment. However, when the underlying layer of a contact is comprised of a cobalt silicide (CoSi2), a plasma RF etching chamber should be added to a deposition chamber because of the wet bath contamination caused by the pre-cleaning of the barrier layer which creates additional expenses due to retrofitting and loss of process time.
Further, in a case where the titanium silicide is formed by a CVD or PE-CVD process using a TiCl4 source gas, chlorine (Cl) atoms, which are dissociated from the TiCl4 gas, remain as impurities in the titanium silicide layer, and reaction by-products of TiClx-type compounds are generated in the deposition chamber. During subsequent heating, the chlorine atoms existing at the surface of the titanium silicide layer reacts with titanium or silicon to increase the contact resistance.
According to preferred embodiments of the present invention, methods for manufacturing a refractory-metal barrier layer in a semiconductor device features a plurality of controlled steps for reducing contact resistance and microvoids in a plurality of conductive contact pads of the semiconductor device through the use of a hydrogen-based plasma cleaning and deposition process. Activating an argon-hydrogen gas mixture at elevated temperatures in a plasma chamber provides a preferred reactant for reactively removing metal-oxides from a surface of the semiconductor device, in addition to chemically removing embedded surface ion residues of strongly reactive halogens, such as fluorine and chlorine.
In accordance with a preferred embodiment of the present invention, there is provided a method of cleaning a surface of a silicon wafer, including subjecting the surface of the silicon wafer to a hydrogen (H2) plasma containing at least one inert gas while biasing the hydrogen (H2) plasma with a RF bias power to direct the hydrogen plasma to clean the surface of the silicon wafer.
In accordance with another preferred embodiment of the present invention, there is provided a method of forming a barrier layer of a semiconductor device, including subjecting a surface of a semiconductor substrate to a hydrogen plasma containing at least one inert gas while biasing the hydrogen plasma with a RF bias power to direct the hydrogen plasma to the surface of the semiconductor substrate, and thereafter depositing a refractory metal layer on the surface of the substrate. The refractory metal layer may be subject to a nitridation ambient to form a refractory metal nitride layer on a surface portion of the refractory metal layer.
In accordance with yet another embodiment of the present invention, there is provided a method of forming a barrier layer of a semiconductor device, including forming a heavily doped region at a surface portion of a semiconductor substrate, depositing an insulating layer over the semiconductor substrate, forming a contact hole to expose the heavily doped region, subjecting the semiconductor device to a first hydrogen plasma containing at least one inert gas while biasing the hydrogen plasma with a RF bias power to direct the first hydrogen plasma to the surface portion of the semiconductor substrate to remove native oxides, depositing a refractory metal layer on the surface portion of the substrate, subjecting a surface of the refractory metal layer to a second hydrogen plasma containing at least one inert gas while biasing the hydrogen plasma with a RF bias power to direct the second hydrogen plasma to the surface of the refractory metal layer to remove impurities, and thereafter subjecting the refractory metal layer to a nitridation ambient to form a first refractory metal nitride layer on a surface portion of the refractory metal layer. A second refractory metal nitride layer may be formed on the refractory metal nitride layer using a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. Thereafter, a metal layer may be deposited on the second refractory metal nitride layer while filling the contact hole, and thereafter the metal layer may be patterned.
In accordance with still another embodiment of the present invention, there is provided a method of forming a barrier layer of a semiconductor device, including depositing a refractory metal layer on a semiconductor substrate using a chemical vapor deposition process, subjecting a surface of the refractory metal layer to a hydrogen plasma containing at least one inert gas while biasing the hydrogen plasma with a RF bias power to direct the hydrogen plasma to the surface of the refractory metal layer to remove impurities, and thereafter subjecting the refractory metal layer to a nitridation ambient to form a refractory metal nitride layer on a surface portion of the refractory metal layer. A second refractory metal nitride layer may be formed on the refractory metal nitride layer using a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
In accordance with another embodiment of the present invention, there is provided a method of forming a barrier layer of a semiconductor device comprising partially removing impurities existing at a surface portion of a substrate in which the impurities are implanted, and depositing a refractory metal layer on the surface portion of substrate. In accordance with yet another embodiment of the present invention there is provided a method of forming a barrier layer of a semiconductor device, comprising treating, with a first hydrogen plasma, a substrate in which impurities are implanted to remove an native oxide layer formed on the substrate and simultaneously, to partially remove the impurities existing at a surface portion of the substrate, depositing a refractory metal layer on the surface portion of the substrate, treating, with a second hydrogen plasma, the refractory metal layer to remove impurities in the refractory metal layer, and treating the refractory metal layer in a nitridation ambient to form a refractory metal nitride layer on the refractory metal layer.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
The above and other objects and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
In general, a plasma-enhanced chemical vapor deposition (PECVD) system usually includes a reaction chamber (or a reactor) wherein a deposition occurs. Reaction gas sources are coupled to the reaction chambers through gas feed lines, and mass-flow controllers are provided on the gas feed lines for metering the reaction gases into the reaction chamber. A heater is also provided in the reaction chamber for controlling the wafer temperature. Also, pumps are coupled to the reaction chambers through an outlet line for establishing a reduced pressure and exhausting gases from the reaction chamber. An RF generator is provided for generating a plasma.
Referring to
A gas inlet 66 is provided for introducing reaction gases such as argon (Ar), hydrogen (H2), CVD source gases, ambient gases, etc. into deposition chamber 50. An RF electrode 54, which is connected to a second power source 60 having an RF plasma power of between about 200 W to 900 W, e.g., 300 W, at a low frequency of between about 400 KHz to 500 KHz, e.g., 460 KHz, is used to generate a plasma 58. The RF plasma power activates a plasma in the reaction gases, and the first power source 62 provides the substrate table 52 with the RF bias to cause the generated plasma 58 to interact with silicon wafer 56. Reaction by-products generated by the interaction are removed from deposition chamber 50 through a vent line 68, typically using a vacuum pump (not shown).
In the present invention, a pre-cleaning process is performed on the silicon wafer 56, wherein contaminants such as native oxides are removed from the silicon wafer 56 in the deposition chamber 50. The native oxides are removed from the surface of the silicon wafer 50 by a sputter etching type process. According to the pre-cleaning process of the present invention, plasma 58 is generated in deposition chamber 50, and ions in the plasma 58 are accelerated by the electric field created by the RF bias supply. The accelerated ions collide with the surface of the wafer 56 to remove the native oxides formed on the surface of the wafer 56.
For example, after heating the silicon water 56 to a temperature of between about 580° C. to about 700° C., the plasma gases, i.e., argon and hydrogen, are introduced into deposition chamber 50 through gas inlet 66. Preferably, a flow rate ratio of the argon gas and the hydrogen is in the range of between about 1:9 to about 2:3. The argon gas is used to ignite the plasma, and the hydrogen gas is used to etch away contaminants such as a native oxide layer formed on the silicon wafer 56. The pressure of deposition chamber 50 is preferably in a range of between about 0.01 Torr to about 10 Torr. Upon application of power sources 60 and 62, electrons and ions of Ar+ and H+ (indicated as “e”s and small circles, respectively, in
Referring to
After removing the native oxide layer, a refractory metal layer may be deposited on wafer 56 via a PECVD process in the same chamber 50. Since the same deposition chamber is used for both the in-situ pre-cleaning of the native oxide and the deposition of the refractory metal layer, no extra chamber for performing the pre-cleaning process is needed, and a wet etching process for removing the native oxide layer may be eliminated. Moreover, the hydrogen plasma pre-cleaning treatment partially removes impurities included in the surface portion of the wafer 56 thereby improving the contact resistance of that layer as well.
Referring to
Referring to
Specifically, after loading the semiconductor substrate 100 into the PECVD deposition chamber 50 of
Further, the hydrogen plasma treatment prevents the formation of micro-voids caused by the diffusion of fluorine atoms and high resistance compounds such as TiFx or TiBx, thereby reducing the contact resistance of the P+ region 102. Also, since a metal silicide, such as titanium silicide (TiSix), is formed on the cleaned surface of substrate 100 after the native oxide is removed by the hydrogen plasma treatment, the contact resistance of P+ region 102 can be further improved.
Additionally, due to the hydrogen plasma treatment, the accumulation of chlorine (Cl) is suppressed in a subsequent deposition process using a TiCl4 source gas, thereby preventing potential resistance failures caused by chlorine atoms.
Specifically, after completing the hydrogen plasma treatment, a depositing source gas, e.g., TiCl4 gas, is introduced into the chamber 50 shown in
The titanium layer 112 is then heat-treated or plasma-treated in a nitridation atmosphere, which may be formed by introducing NH3 gas or N2 gas into the reaction chamber. Preferably, NH3 gas is introduced into the reaction chamber at a flow rate of about 300 sccm together with the flow rates for the hydrogen and argon gases as described above. An RF bias power is grounded and a RF plasma power of about 300 W are preferably applied, thereby forming a second plasma in the chamber 50. In reaction to the second plasma, titanium atoms at a surface portion of the titanium layer 112 (noted by circle A in
According to the first embodiment of the present invention, the hydrogen plasma treating process, the titanium depositing process, and the nitridation process are preferably performed in-situ in a single reaction chamber, i.e., in a PECVD deposition chamber.
Referring to
Specifically, after forming the titanium layer 210, argon gas and hydrogen gas are introduced into deposition chamber 50 preferably at the same flow rates and flow ratios as in the first embodiment. Then, an RF bias power of about 10˜900 W and a RF plasma power of about 200˜900 W are applied to form the second plasma composed of Ar+ ions, H+ ions and electrons in the deposition chamber 50. The H+ ions collide with the surface of the titanium layer 210 to 1) remove reaction by-products such as TiClx (x=1˜4) remaining in the chamber and 2) replace chlorine atoms (Cl) existing at the interface between the titanium silicide layer and the titanium layer with an HCl-type compound, thereby decreasing the remaining quantity of chlorine atoms in the titanium layer 210.
Referring to
In the second embodiment of the present invention, the titanium deposition process, the second hydrogen plasma treatment process, and the nitridation process are preferably performed in-situ in a single reaction chamber, i.e., in a PECVD deposition chamber. Although, in the second embodiment, the second hydrogen plasma treatment process is performed before the nitridation process, in an alternate embodiment, the sequence may be reversed, with the second plasma treatment process being performed after the nitridation process. In either case, the nitridation using NH3 plasma is effective at decreasing chlorine content in the titanium silicide layer
The third embodiment is similar to the second embodiment but with an additional titanium nitride layer being formed via a CVD method on the titanium nitride layer 212 of
In
In the third embodiment, the first hydrogen plasma treatment process, the titanium depositing process, the second hydrogen plasma treatment process and the nitridation process are preferably performed in-situ in a single reaction chamber, i.e., in a PECVD deposition chamber 50.
Referring to
The second titanium nitride layer 314 is formed to a thickness of about 10 to 30 nm, preferably 20 nm, by introducing TiCl4 gas at a flow rate of about 3-50 sccm, N2 gas at a flow rate of about 600 sccm, and NH3 gas at a flow rate of about 50 sccm at a temperature of about 650° C. If only the thermal titanium nitride layer formed by nitriding the titanium layer in a nitridation atmosphere is used as a barrier layer, the thermal budget is preferably controlled in order to obtain a thickness suitable for a barrier layer in CVD (Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) process. Alternatively, if the CVD-titanium nitride layer is deposited after forming the titanium nitride layer via a nitridation treatment, the thickness of the thermal titanium nitride layer can be decreased in order to reduce the thermal budget.
Next, a metal such as tungsten (W) or aluminum (Al) is deposited onto the second titanium nitride layer 314 to form a metal layer 316 filling the contact hole 306. The metal layer is patterned via a photolithographic process or a chemical mechanical polishing process, thereby forming the metal contacts on the P+ well 302 in the contact hole 306.
Observation of Contact Resistance
After forming the barrier layer in accordance with the method as in Embodiment 1, tungsten (W) or aluminum (Al) was deposited on the barrier layer to form a metal layer filling the contact hole. The metal layer was patterned to form the metal contacts in the contact hole. Contact resistances were observed with regard to the various contact holes.
In ,
,
and
, and the N+ contact resistance by depositing Ti at the deposition temperature of 630° C. to various thickness and annealing the deposited Ti to form TiN at a temperature of 700° C. are indicated by symbols ▪, ●, ▴, and ♦. The symbols
and ▮ show the observed contact resistances at the N+ contact having a size of 0.19 μm which was formed at the peripheral region. The symbols
and ● show the observed contact resistances at the N+ node contact having a size of 0.14˜0.15 μm. The symbols
and ▴ show the observed contact resistances at the Vss contact having a size of 0.16˜0.14 μm. The symbols
and ♦ show the observed contact resistances at the bitline contact having a size of 0.16˜0.14 μm.
In ,
and
, and the P+ contact resistance by depositing Ti at the deposition temperature of 630° C. to various thickness and annealing the deposited Ti to form TiN at a temperature of 700° C. are indicated by symbols ▪, ● and ▴. The symbols
and ▮ show the observed contact resistances at the P+ contact having a size of 0.19 μm which was formed at the peripheral region. The symbols
and ● show the observed contact resistances at the P+ node contact having a size of 0.14˜0.15 μm. The symbols
and ▴ show the observed contact resistances at the Vss contact having a size of 0.16˜0.14 μm.
Referring to
The reduction of the contact resistance in the p+ contact is greater than in the n+ contact. Thus, it can be noted that the contact resistance becomes lower as the amount of titanium silicide increases.
As for the thickness of the titanium layer, the variation of the P+ contact resistance is larger than that of the N+ contact resistance because the formation of high resistance compounds caused by the P-type impurity, e.g., TiBx or TiFx, is suppressed by the hydrogen plasma treatment.
Observation of the Leakage Current at the p+ Contact
The barrier layer was formed in accordance with the method as shown and described in the third embodiment of the present invention. Here, the CVD-titanium nitride layer was deposited to a thickness of 20 nm to form a metal layer so as to fill the contact hole 306. The obtained metal layer was patterned to thereby form various metal wirings. Junction leakage was observed on the various contact holes.
In the graph, the symbol shows the junction leakage obtained under the condition that the titanium layer was deposited to a thickness of 45 Å at a temperature of 615° C. and the CVD titanium nitride layer was formed at a temperature of 650° C. The symbol ∘ shows the junction leakage obtained under the condition that the titanium layer was deposited to a thickness of 45 Å at a temperature of 630° C. and the CVD titanium nitride layer was formed at a temperature of 700° C. The symbol Δ shows the junction leakage obtained under the condition that the titanium layer was deposited to a thickness of 55 Å at a temperature of 630° C. and the CVD titanium nitride layer was formed at a temperature of 700° C. The symbol ∇ shows the junction leakage obtained under the condition that the titanium layer was deposited to a thickness of 70 Å at a temperature of 630° C. and the CVD titanium nitride layer was formed at a temperature of 700° C. The symbol ⋄ shows the junction leakage obtained under the condition that the titanium layer was deposited to a thickness of 85 Å at a temperature of 630° C. and the CVD titanium nitride layer was formed at a temperature of 700° C. The symbol
shows the junction leakage obtained under the condition that the titanium layer was deposited to a thickness of 85 Å at a temperature of 615° C. and the CVD titanium nitride layer was formed at a temperature of 650° C.
Referring to
Observation of Impurities
Referring to
When comparing
As compared with the boron concentration (B1) in
Etching Quantity Measurement by the Hydrogen Plasma Treatment
Referring to
As the RF plasma power or the plasma etching time increases, the etch quantity of the native oxide layer also increases. Therefore, by controlling the RF plasma power for activating the plasma in the PECVD chamber, the thin native oxide layer formed on the silicon substrate can be sufficiently removed.
Chlorine Content Measurement
Referring to
Referring to
After depositing a titanium layer as described in connection with the first embodiment, the titanium layer was subjected to heat treatment which was performed at a temperature of 60˜800° C.
In the case of line a of
In the case of line b of
indicates the case where the second hydrogen plasma treatment as described in the context of the second embodiment was performed.
From
According to the present invention as described above, before depositing the refractory metal layer for use as the barrier layer, the first hydrogen plasma treatment is carried out in CVD or PECVD deposition chamber, such that impurities, such as fluorine and boron, included in the surface portion of the substrate are removed to suppress the formation of high resistance compounds and micro-voids, thereby reducing the contact resistance. Further, the native oxide layer formed on the substrate is removed by the first hydrogen plasma treatment, so that the in-situ pre-cleaning process can be performed without an additional cleaning chamber and a wet cleaning process for removing the native oxide layer may be eliminated. In addition, after depositing the refractory metal layer, the second hydrogen plasma treatment is carried out to remove impurities such as chlorine (Cl) atoms existing in the surface portion of the refractory metal silicide layer and to remove by-products such as TiClx generated in the deposition chamber, which results in the reduction of the contact resistance.
Preferred embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.
Park, Sangwook, Won, Jaihyung, Koo, Kyeongmo, Um, Hyeonill, Jung, Junhyuk
Patent | Priority | Assignee | Title |
8951913, | May 24 2012 | Applied Materials, Inc. | Method for removing native oxide and associated residue from a substrate |
Patent | Priority | Assignee | Title |
5654235, | Aug 18 1994 | LAPIS SEMICONDUCTOR CO , LTD | Method of manufacturing contact structure using barrier metal |
5747384, | Dec 26 1994 | Sony Corporation | Process of forming a refractory metal thin film |
5780356, | Dec 15 1995 | Hyundai Electronics Industires Co., Ltd. | Method for forming metal wire of semiconductor device |
5834371, | Jan 31 1997 | Tokyo Electron Limited | Method and apparatus for preparing and metallizing high aspect ratio silicon semiconductor device contacts to reduce the resistivity thereof |
6054768, | Oct 02 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Metal fill by treatment of mobility layers |
6057231, | Oct 02 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for improved metal fill by treatment of mobility layers |
6107192, | Dec 30 1997 | Licentia Ltd | Reactive preclean prior to metallization for sub-quarter micron application |
6143128, | Jan 31 1997 | Tokyo Electron Limited | Apparatus for preparing and metallizing high aspect ratio silicon semiconductor device contacts to reduce the resistivity thereof |
6217721, | Aug 07 1995 | Applied Materials, Inc | Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer |
6365516, | Jan 14 2000 | Advanced Micro Devices, INC | Advanced cobalt silicidation with in-situ hydrogen plasma clean |
6482735, | Oct 02 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for improved metal fill by treatment of mobility layers |
6563133, | Aug 09 2000 | INVENSAS BONDING TECHNOLOGIES, INC | Method of epitaxial-like wafer bonding at low temperature and bonded structure |
6693030, | Dec 30 1997 | Applied Materials, Inc. | Reactive preclean prior to metallization for sub-quarter micron application |
6812139, | Oct 02 1997 | Micron Technology, Inc. | Method for metal fill by treatment of mobility layers |
6841450, | Sep 21 2000 | SHIN-ETSU HANDOTAI CO , LTD | Annealed wafer manufacturing method and annealed wafer |
20030194859, | |||
JP697111, | |||
KR73508, | |||
KR19990054920, | |||
KR20010032716, | |||
KR20010033812, | |||
KR20010039860, | |||
KR20010044869, | |||
WO9928955, |
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