According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.
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11. A semiconductor device comprising:
at least two channel-portion holes disposed in a semiconductor substrate;
line patterns filling the channel-portion holes and disposed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate;
a channel region disposed in the semiconductor substrate directly under a portion of the line patterns that are within the channel-portion holes,
a source region disposed in the main surface of the semiconductor substrate and overlapped by one sidewall of one of the line patterns; and
a drain region disposed in the main surface of the semiconductor substrate and overlapped by another sidewall of the one of the line patterns,
wherein the channel region is disposed between the channel-portion holes and wherein lower portions of at least two of the channel-portion holes cover the same channel region, and
wherein the channel region and the semiconductor substrate have a same conductivity type.
1. A semiconductor device comprising:
at least two channel-portion holes disposed in a semiconductor substrate;
line patterns filling the channel-portion holes and disposed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate, wherein each line pattern includes a gate electrode; and
a channel region disposed in the semiconductor substrate directly under a portion of the line patterns that are within the channel-portion holes,
wherein the channel region is disposed between the channel-portion holes and wherein lower portions of at least two of the channel-portion holes cover the same channel region;
a source region disposed in the main surface of the semiconductor substrate and overlapped by one sidewall of one of the line patterns; and
a drain region disposed in the main surface of the semiconductor substrate and overlapped by another sidewall of the one of the line patterns,
wherein the source region and the drain region are laterally spaced apart from each other by the channel region.
12. A semiconductor device comprising:
at least two channel-portion holes disposed in a semiconductor substrate;
line patterns filling the channel-portion holes and disposed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate; and
a channel region disposed in the semiconductor substrate directly under a portion of the line patterns that are within the channel-portion holes;
line spacers disposed respectively on sidewalls of the line patterns;
electrode impurity regions disposed in the semiconductor substrate and overlapping with the line patterns; and
landing pads disposed between the line patterns and extending from upper portions of the line patterns and also covered with an interlayer insulating layer,
wherein the landing pads contact the electrode impurity regions, respectively, and the electrode impurity regions have a conductivity type different from that of the channel region, and
wherein the channel region is disposed between the channel-portion holes and also covers lower portions of the channel-portion holes.
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This patent application claims priority from Korean Patent Application No. 10-2004-0009776, filed Feb. 13, 2004, the contents of which are hereby incorporated by reference in their entirety.
1. Field of the Invention
The invention relates to semiconductor devices and methods of forming the same and, more specifically, to transistors having a channel region between channel-portion holes and methods of forming the same.
2. Description of the Related Art
Generally, semiconductor devices include discrete elements to place data input by a user in a desired place. The discrete elements include a capacitor for storing data and a transistor for transmitting the data to the capacitor through a line.
The transistor includes a gate pattern disposed on a semiconductor substrate, source and drain regions formed in the semiconductor substrate to overlap the gate pattern, and a channel region disposed in the semiconductor substrate under the gate pattern to transmit user's data. When a voltage is applied to the gate pattern, and the source and drain regions to drive the transistor, the channel region serves as a data transmission route between the source region and the drain region.
However, as a design rule of the semiconductor device is reduced, the channel region and the gate pattern become smaller areas in the transistor. To cope with this change, the channel region is formed by at least one ion implantation process, which is performed in the semiconductor substrate. The channel-portion hole is disposed to extend from a top surface of the semiconductor substrate to a lower region thereof by a predetermined depth, and to contact the channel region. There is provided a gate pattern that fills the channel-portion hole with the trench shape. The gate pattern provides a data transmission route along the semiconductor substrate that defines the channel-portion hole. As such, if a voltage is applied to both the channel-portion hole and the channel region during the operation of the transistor, a body effect is increased due to the channel region around the channel-portion hole, thereby decreasing current driving capability.
On the other hand, U.S. Pat. No. 5,817,558 to Shye Lin Wu et al (the '558 patent) discloses a method of forming a t-gate lightly-doped drain semiconductor device. According to the '558 patent, this method includes forming a pad oxide layer on the semiconductor substrate. A lightly doped layer is formed around the pad oxide layer by implanting impurity ions into the semiconductor substrate, and a first insulating layer is formed on the pad oxide layer. An aperture is formed in the first insulating layer, and a sidewall spacer is formed on the sidewall of the aperture.
The method includes performing an etching process in the semiconductor substrate by using the first insulating layer and the sidewall spacers as an etch mask to form a groove in the substrate. At this time, the sidewall spacers are also removed. A gate oxide layer is formed in and around the groove, and a gate material layer, which fills the aperture and the groove, is formed on the first insulating layer.
Further, the method includes partially performing an etching process in the gate material layer to form a T-shaped gate in the aperture and the groove. Subsequently, the first insulating layer is removed. Heavily doped source and drain layers are formed on the lightly doped layer so that they are arranged at both sides of the T-shaped gate.
However, the method further includes forming an anti-punch-through layer to prevent a contact between the source and the drain in the semiconductor substrate having the groove. The anti-punch-through layer is arranged along the groove to reduce an impurity concentration of the lightly doped layer adjacent to the groove, thereby causing a current leakage while driving the semiconductor device. This is because the lightly doped layer and the anti-punch-through layer have different conductivity types from each other. Furthermore, since the gate oxide layer is partially etched, characteristics of the semiconductor device may be degraded due to the etching damage of the oxide layer.
According to some embodiments of the invention, there are provided transistors having a channel region between at least two channel-portion holes suitable for increasing current driving capability, and methods of forming the same.
And there are provided transistors of DRAM cells having a channel region, which is disposed on the semiconductor substrate below a bit line node rather than below a capacitor node, between at least two channel-portion holes to improve current driving capability and refresh characteristics, and methods of forming the same.
Exemplary embodiments of the invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows when taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts.
Referring to
First and second line patterns 100 and 105 are arranged on the active region 25 and the device isolation layer 20, respectively. Each of the first and second line patterns 100 and 105 includes a gate electrode 85 and a gate capping layer pattern 95 stacked thereon. The second line patterns 105 are disposed on the device isolation layer 20 in parallel with and opposite to at least one of the first line patterns 100. At this time, the gate electrode 85 of the first line patterns 100 fill the channel-portion hole 60 arranged in the semiconductor substrate 10 of the active region 25. The gate electrodes 85 comprise a polysilicon layer with n or p conductivity type and a metal silicide layer stacked thereon. The gate electrodes 85 may be the polysilicon layer with the n or p conductivity type. The polysilicon layer has a conductivity type opposite to the channel region 125 in the semiconductor substrate 10. In the peripheral circuit region other than the DRAM cell array region 190, the polysilicon layer and the channel region 125 may have either a same conductivity type or different conductivity types from each other. Preferably, the gate capping layer pattern 95 is a silicon nitride layer (Si3N4).
Line spacers 130 are disposed on sidewalls of the first and second line patterns 100 and 105, respectively. Preferably, a line insulating layer pattern 75 is disposed below the line spacers 130 as well as the first and second line patterns 100 and 105. The line spacers 130 preferably have the same etching ratio as the gate capping layer pattern 95. Preferably, the line insulating layer pattern 75 has an etching ratio different from the gate capping layer pattern 95, and is one selected from either a silicon oxide layer (SiXOY) or a silicon oxynitride layer (SiXOYNZ).
Electrode impurity regions 145 are disposed in the semiconductor substrate 10 between the first and second line patterns 100 and 105, wherein the electrode impurity regions 145 overlap the first and second line patterns 100 and 105. The electrode impurity regions 145 have a conductivity type different from the channel region 125, which covers the lower portions of the channel-portion hole 60. Each of the electrode impurity regions 145 refers to source and drain regions of a transistor. Landing pads 180 are disposed between the first and second line patterns 100 and 105, and disposed to extend from an upper portion of the first and second line patterns 100 and 105, wherein the upper sides of the landing pads 180 are covered with an interlayer insulating layer 160 and electrically insulated from each other. Each of the landing pads 180 is disposed on the semiconductor substrate 10 and contacts the electrode impurity regions 145.
A method of forming a transistor according to an embodiment of the invention will now be described with reference to the accompanying drawings and embodiments.
Referring to
In
Subsequently, by using the pad layer patterns 35, the photoresist patterns 55, and the reflective patterns 45 as an etching mask, the etching process is performed on the semiconductor substrate 10, as shown in
Referring to
The sacrificial layers 65,the reflective layer patterns 45, and the pad layer patterns 35 are removed from the semiconductor substrate 10. A gate capping layer 90, a line insulating layer 70, and a gate layer 80 are sequentially formed on the semiconductor substrate having the channel-portion holes 60. The line insulating layer 70 is conformally formed in the channel-portion holes 60 to cover the main surface of the semiconductor substrate 10. The gate layer 80 is formed of a polysilicon layer having n or p conductivity type and a metal silicide layer stacked thereon. The gate layer 80 may be formed of the polysilicon layer having either the n or p conductivity type. The polysilicon layer is formed to have a conductivity type opposite to the channel region 125 of
By using the line insulating layer 70 as an etching stop layer, a photolithography and an etching process are sequentially performed to the gate capping layer 90 and the gate layer 80. Through the photolithography and etching processes, the first and second line patterns 100 and 105 are formed on the line insulating layer 70. Each of first and second line patterns 100 and 105 is formed of a gate electrode 85 and a gate capping layer pattern 95. At this time, the first line patterns 100 are formed to be spaced apart from each other on the active region 25, where the gate electrodes 85 are formed to fill the channel-portion holes 60, and each of the second line patterns are formed on the device isolation layer 20 in parallel with and opposite to at least one of the first line patterns 100.
Referring to
To minimize a body effect of a transistor, it is preferable that the channel region 125 is formed to have a predetermined volume in the semiconductor substrate 10 between the first line patterns 100. Preferably, the channel region 125 and the semiconductor substrate 10 have the same conductivity type. Further, if the channel region 125 is formed in the peripheral circuit region other than the DRAM cell array region 190, the channel region 125 is formed to have a conductivity type different from the semiconductor substrate 10 or the same conductivity type as the semiconductor substrate 10.
Next, as shown in
Referring to
Next, in
Referring to
Subsequently, in
A DRAM having the transistor uses the landing pads 180, 184 and 188 as electrical nodes of the source and drain regions of the transistor, respectively. Further, of the landing pads, two landing pads 180 and 188 are used as electrical nodes of capacitors and the rest 184 is used as a electrical node of a bit-line. At this time, the two landing pads 180 and 188 dispose therebelow the PN junctions 150 and 158 of
Referring to
At this time, while driving one of the transistors 205, a back bias is applied to the channel region below the main surface of the semiconductor substrate 10, so that the body effect is increased in proportion to a volume of the channel region between both sides of the device isolation layer 20. This refers to a tendency to increase the threshold voltage at the same VBB in the case of fixing a channel length of the transistors 200, 205. While driving the other transistors 200, the back bias is applied to the channel region 125 disposed only between the first line patterns 100 of
Further, to compare electrical characteristics of the DRAMs 210 and 215 having the transistors 200 and 205, a number of failed bits were counted according to a static refresh time.
One of the DRAMs 215 includes the transistor 205 so that the channel region is formed between both sides of the device isolation layer 20. That is, the DRAM 215 is formed so that all of the junctions of the channel region and the electrode impurity regions 145 have the same depth as the junction 154 disposed between the first line patterns 100 of
However, the other DRAM 210 is formed to have the same channel region 125 as shown in
As described above, the invention provides a proper way to minimize the body effect of a transistor by forming a channel region between at least two channel-portion holes. A DRAM having the transistor can maximize a current driving capability, and further, increase the refresh characteristics of the cell array region.
Embodiments of the invention will now be described in a non-limiting way.
Embodiments of the invention provide transistors having a channel region between channel-portion holes and methods of forming the same.
According to some embodiments of the invention, there is provided transistors having channel region between channel-portion holes that includes at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are disposed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is disposed between the channel-portion holes and also covers lower portions of the channel-portion holes.
According to some embodiments of the invention, transistors have a channel region between channel-portion holes in a DRAM cell that includes an active region isolated by a device isolation layer. At least two channel-portion holes are disposed in a semiconductor substrate below the active region. First line patterns are disposed in parallel to be spaced apart from each other on the active region to fill the channel-portion holes. Second line patterns are disposed on the device isolation layer along with the first line patterns, each being adjacent to the active region and being in parallel with and opposite to at least one of the first line patterns. A channel region is disposed in the semiconductor substrate below the first and second patterns. The channel region is disposed between the channel-portion holes and also covers lower portions of the channel-portion holes.
According to some embodiments of the invention, methods that form transistors have a channel region between channel-portion holes that includes forming pad layer patterns to expose a main surface of a semiconductor substrate. The semiconductor substrate is etched by using the pad layer patterns as an etching mask to form at least two channel-portion holes extending downward from the main surface of the semiconductor substrate. The pad layer patterns are removed from the semiconductor substrate. Line patterns are formed on the semiconductor substrate, each of the line patterns being formed to fill the channel-portion holes. A channel region covers lower portions of the channel-portion holes.
According to some embodiments of the invention, methods that form transistors have a channel region between channel-portion holes in a DRAM cell that includes forming a device isolation layer isolating an active region of a semiconductor substrate. Pad layer patterns are formed on the semiconductor substrate having the device isolation layer, the pad layer patterns exposing a main surface of the semiconductor substrate of the active region. An etching process is performed in the semiconductor substrate by using the pad layer patterns as an etching mask to form at least two channel-portion holes extending downward from the main surface of the semiconductor substrate. The pad layer patterns are removed from the semiconductor substrate. First line patterns and second line patterns are formed on the device isolation layer and the active region, respectively. The second line patterns being formed to be disposed opposite to at least one of the first line patterns, and the first line patterns being formed to fill the channel-portion holes. A channel region covers lower portions of the channel-portion holes.
Although the invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
Kim, Yong-sung, Lee, Jin-woo, Chung, Tae-Young
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