A display device which includes a plurality of adjacent gate lines and drain lines disposed in a display area of the display device, and a plurality of pixels disposed in the display area, each of the plurality of pixels having a switching element coupled to a corresponding one of the plurality of adjacent gate lines and a corresponding one of the plurality of drain lines. During one frame period, the plurality of adjacent gate lines are selected, and thereby video signals are written into the plurality of pixels via the plurality of drain lines, and thereafter during the one frame period, the plurality of adjacent gate lines are selected, and thereby signals corresponding to blanking data are written into the plurality of pixels.
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1. A display device comprising:
a plurality of gate lines;
a plurality of drain lines; and
a plurality of pixels, each of said plurality of pixels having a switching element coupled to a corresponding one of said plurality of gate lines and a corresponding one of said plurality of drain lines;
wherein said display device is configured to switch between a first operating mode and a second operating mode;
where said first operating mode is such that each of said plurality of gate lines are selected two times during one frame period, and thereby video signals and signals corresponding to blanking data are written into said plurality of pixels, and said second operating mode is such that each of said plurality of gate lines are selected once during one frame period, and thereby video signals are written into said plurality of pixels, but the signals corresponding to the blanking data are not written into said plurality of pixels; and
wherein said first operating mode generates said video signals by using a first group of gray scale voltages, and said second operating mode generates said video signals by using a second group of gray scale voltages.
2. A display device according to
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This application is a continuation of U.S. application Ser. No. 10/382,295, filed Mar. 7, 2003, now U.S. Pat. No. 6,903,716, the contents of which are incorporated herein by reference.
This invention relates to a liquid crystal display device driven by a switching element using amorphous silicon, polycrystalline silicon or the like for each pixel, an electroluminescent-type display device, and a display device provided with a light emitting element such as a light emitting diode and the like for each pixel. In particular, this invention relates to a display device that performs blanking processing.
Liquid crystal display devices have been widely used as display devices that retain light emitted from each of a plurality of pixels in a desired amount within a predetermined period of time (e.g., a period of time corresponding to 1 frame period) on the basis of video data inputted for each 1 frame period. In the liquid crystal display device of active matrix scheme, each of a plurality of pixels arranged in a two-dimensional form or in a matrix form is provided with a pixel electrode and a switching element (e.g., a thin film transistor) for supplying a video signal to the pixel electrode. The video signal is supplied from one of a plurality of data lines (also called video signal lines) extending in the longitudinal direction of a picture, for example, to a pixel electrode through the switching element. The switching element receives scanning signals at predetermined intervals (e.g., for each frame period) from one of a plurality of gate lines (also called scanning signal lines) intersecting the plurality of data lines and extending (e.g., in a horizontal direction in a picture) and supplies a video signal from one of the plurality of data lines to a pixel electrode. Accordingly, the switching element keeps the pixel electrode at a potential based on the video signal supplied to this pixel electrode in response to the previous scanning signal until it receives the next scanning signal, so that the pixel provided with this pixel electrode is maintained at a desired brightness level.
Such an operation stands in contrast to an impulse emission operation of a cathode-ray tube represented by a Braun tube where a phosphor arranged for each pixel is caused to emit light at the instant of receiving the video signal. Unlike the impulse light emission, the video displaying operation of the active matrix type liquid crystal display device as described above is also called sometimes hold-type light emission. In addition, such video display as performed by the active matrix type liquid crystal display device is also employed in the electroluminescent type (abbreviated as EL type) or a light emission diode array type display device and those operations can be described by replacing the aforesaid voltage control of the pixel electrode with the control of carrier injection to the electroluminescent element or the light emission diode.
Since the display device using such a hold-type light emission displays an image by retaining a brightness level of each of the pixels within a predetermined period of time to display the image, when the image to be displayed by the display device is replaced with a different image, for example, between a pair of the successive aforesaid frame periods, the pixel sometimes does not provide a sufficient response. This phenomenon can be explained by the fact that the pixel set to a predetermined brightness level in a certain frame period (e.g., a first frame period) keeps the brightness level associated with the previous frame period (the first frame period) in the next frame period (e.g., a second frame period) subsequent to the first frame period until the brightness level associated with the second frame period is set. In addition, this phenomenon can also be explained by the so-called hysteresis of the image signal in each of the pixels, in which part of the image signal (or an amount of electric charge corresponding to the image signal) sent to the pixel in the aforesaid certain frame period (the first frame period) interferes with the image signal (or an amount of electric charge corresponding to the image signal) to be sent to the pixel in the aforesaid next frame period (the second frame period). The technology for resolving such a problem as above in regard to the response performance of the image display in the display device using the hold-type light emission has been disclosed by Japanese Patent Publication Nos. 06-016223 and 07-044670, and Japanese Patent Laid-open Nos. 05-073005 and 11-109921, for example.
Among them, Japanese Patent Laid-Open No. 11-109921 makes a reference to the so-called blurring phenomenon in which a contour of an object becomes vague as compared with that of a cathode ray tube for light emitting the pixel in an impulse manner when moving images are reproduced by the liquid crystal display device (one example of the display device using the hold-type light emission). To obviate the blurring phenomenon, Japanese Patent Laid-open No. 11-109921 discloses the liquid crystal display device in which a pixel array (a group of pixels arranged in a two-dimensional manner) in a liquid crystal display panel is divided into two, upper and lower, segments in a picture (an image display area) and each of the divided pixel arrays is provided with a data line drive circuit. This liquid crystal display device performs the so-called dual scanning operation in which a video signal is supplied from the data line drive circuits arranged the respective pixel arrays while selecting a gate line of each of the upper and lower pixel arrays one by one, i.e. two, upper and lower, gate lines in total.
An upper phase and a lower phase are displaced while this dual scanning operation is being carried out in 1 frame period, a signal (the so-called video signal) corresponding to a displayed image at one phase and a signal of blanking image (e.g., a black image) at the other phase are inputted from the associated data line drive circuits to the pixel array. Accordingly, a period in which the image is displayed and a period in which a blanking display is carried out are given to both upper and lower pixel arrays in 1 frame period, whereby a period for holding an image in the entire picture area is shortened. With such an arrangement, the liquid crystal display device can also provide moving image display performance comparable to that of a Braun tube.
However, since the liquid crystal display device described above as the prior art has a configuration in which the liquid crystal display panel is divided into upper and lower halves, and a data line drive circuit is provided for each of the upper and lower segments, this liquid crystal display device cannot avoid disadvantages that parts cost and manufacturing cost are increased, the entire liquid crystal display device becomes larger in size with the increased number of component parts, and its structure becomes complicated. In addition, it is also apparent that a cost for making the liquid crystal display panel into a large-sized picture area and increasing its display definition is increased more than that of a usual panel. Further, the aforesaid liquid crystal display panel remarkably improves a moving image display characteristic and in turn it is not different from the usual liquid crystal display panel in view of a still image represented by a desktop image in a personal computer and the like. That is, this type of liquid crystal display panel becomes overqualified in an application of a monitor of a notebook personal computer and the like and this is limited to a high-class unit for an application of multi-media. For this reason, it becomes necessary to prepare some component parts specific to this type of liquid crystal display device or arrange a production line, with the result that efficiency in view of mass-production is inevitably decreased.
It is therefore an object of the present invention to provide a display device capable of restricting deterioration in image quality such as a blurring phenomenon generated in a moving image while restricting an increased-sized and complicated structure of the entire device.
The present invention relates to a display device for displaying an image by receiving video data per frame period. The display device in accordance with the present invention is provided with a data control circuit for inserting blanking data into the video data corresponding to one frame period, and generates a clock for scanning pixel lines (i.e. pixel rows in the display device) successively, so that the video data and blanking data are displayed (i.e. the video data and blanking data are supplied to pixels in the display device) during an arbitrary frame period (for example, a frame period succeeding the frame period during which the above-mentioned video data is being supplied). An example of the display device to which the present invention is applicable is provided with a display panel having a plurality of pixels (display units) arranged in a matrix configuration, each of the pixels having an active element, a drain driver (a video signal drive circuit) for generating gray scale voltages in accordance with an image to be reproduced (video data supplied to the display device), a gate driver (a scanning signal drive circuit) for supplying a scanning signal to the active elements in a group of desired ones among the plural pixels such that the gray scale voltages are supplied to the pixels of the group, a data control circuit for generating blanking data during a time interval during which the video data corresponding to one frame period is being supplied to the display device, and a timing control circuit for generating a clock so that the gray scale voltages in accordance with the video data and signal voltages in accordance with the blanking data are supplied to the pixels of the group during the one frame period. For example, the above-mentioned group of desired ones among the plural pixels means a row of pixels arranged in a lateral direction on a display screen. A plurality of such rows of the pixels are arranged in the screen of a display device, and each of the active elements in the pixels in each of the rows receives an output from the drain driver. Such operation of supplying outputs from the drain driver to electrodes which contribute to image displaying in respective pixels (which are called pixel electrodes in the case of a liquid crystal display device) by opening and closing such active elements is called scanning per group of pixels (or scanning per pixel row, or scanning per pixel line). Each of the pixels is held at a desired brightness (light transmission, or light emission intensity) between two successive scannings. Operation of supplying signal voltages based upon pseudo video data different from the video data to plural pixels as in the case of gray scale voltages during a time interval between two times of supplying gray scale voltages the plural pixels based upon the video data is called insertion of blanking data into the video data.
In an example of the display device in accordance with the present invention, arranged in a display area formed with a plurality of pixels are a plurality of gate lines (which are also called scanning signal lines) extending from the gate driver or from a side formed with the gate driver of the display area, and a plurality of drain lines (which are also called data lines or video signal lines) extending from the drain driver or a side formed with the drain driver of the display area in a direction intersecting the plural gate lines. In the display area, each of the above-mentioned groups formed of ones among the plural pixels is a pixel row arranged along one of the plural gate lines, and the active elements provided in the respective pixels in the pixel row receive a scanning signal from the one of the plural gate lines. Ones of the plural pixels form a pixel column which receive video signals from one of the plural drain lines, and it is often that plural pixels forming one pixel row belong to pixel columns different from each other.
The above-mentioned video data corresponding to one frame period can be supplied to the display device in the form of data for interlaced odd-numbered and even-numbered fields. For example, a plurality of pixel rows are divided into a plurality of groups each comprising plural adjacent pixel rows, the odd-numbered field data correspond to odd-numbered groups of the pixel rows, and the even-numbered field data correspond to the even-numbered groups of the pixel rows.
The above-mentioned data control circuit can be configured so as to reduce or increase the size of video data corresponding to one frame period. For example, by using video signals corresponding to a group of pixels, video signals to be supplied to plural adjacent groups formed of plural pixels can be created. Such video data processing is called scaling. Further, in this case, blanking data can also be created for each of the plural groups of the pixels, or video signals corresponding to the blanking data can be created, and they can be supplied to each of the groups of the pixels.
Further, vertical resolution (for example, the degree of image definition in a direction of extension of the data lines) of video data corresponding to one frame period can be reduced by the data control circuit, and blanking having the similar vertical resolution can be inserted into the video data irrespective of the degree of reduction. For example, the size of video data corresponding to one frame period is scaled by using the data control circuit such that vertical resolution of the video data is reduced, and blanking data corresponding to the reduced video data can be inserted into the scaled video data. Data effective for displaying an image can be added to video data corresponding to one frame period by using the data control circuit, and if an expedient for changing modes of inserting blanking data into the video data is added to the data control circuit, a desired mode of inserting blanking data can be selected from among plural modes of inserting blanking data.
The above-mentioned timing control circuit can be configured so as to supply gray scale voltages to the drain driver via plural different systems, and in this case an expedient can be provided which select a group of gray scale voltages from one among the different systems.
The gate driver can be configured such that a plurality of pixel rows are divided into a plurality of groups each formed of plural adjacent pixel rows, and the plurality of groups of the pixels are successively scanned with all the pixel rows of each of the groups being scanned at one time, in any of the above-described display devices.
A signal voltage produced based upon the blanking data is selected to produce a gray scale level equal to that of a black level in gray scale represented by video data.
The above-described display devices can be provided with a light source device (a light source unit) for illuminating the display panel and a light source control circuit for controlling at least one of the amount of light irradiated onto the display panel from the light source device, the lighting time of the light source device, and the light-ceasing time of the light source device in timing with displaying of the above-explained blanking data. The light source device can be provided with a plurality of light sources controllable independently of each other, for example.
The above-explained gate driver can be configured such that each of the plural gate lines or each of output terminals of the gate drivers connected to the gate lines outputs a scanning signal (a gate selection pulse) plural times during one frame period. A first gate selection pulse for writing in video data and a second gate selection pulse for writing in blanking data can be included in the above-mentioned plural gate selection pulses outputted during one frame period.
Further, the above-explained gate driver can be configured such that at least one of the output terminals of the gate drivers or at least one of the gate lines connected to the output terminals of the gate drivers outputs a gate selection pulse only once during one frame period, and the remainder of the output terminals or the remainder of the gate lines output plural times during the one frame period. In this case, it is desirable that the at least one output terminal for outputting a gate selection pulse only once is provided separately from the remainder of the output terminals.
The drain driver can be configured such that it creates the above-explained blanking data.
Each of the above-explained present inventions is applicable to a hold-type active-matrix-driven display device which is provided with a pixel array in the form of a matrix having a plurality of pixels arranged in pixel rows extending in a first direction and pixel columns extending in a second direction intersecting the first direction, each of the plurality of pixels being provided with a switching element; supplies to the pixel array a first signal for controlling groups of switching elements in respective pixel rows from respective ones of a plurality of first signal lines extending in the first direction and arranged in the second direction, and supplies second signals to the switching elements (at least one of the switching elements supplied with the first signal from the first signal line) in the respective pixel columns from a plurality of second signal lines extending in the second direction and arranged in the first direction such that the pixels associated with the switching elements in the respective pixel columns produce specified display conditions. The above-mentioned first signal is called a scanning signal or a gate signal, and the above-mentioned second signal is called a data signal or a drain signal.
This display device is also provided with a first drive circuit for outputting the first signal to each of the first signal lines, a second drive circuit for outputting the second signal to each of the second signal lines, and a display control circuit for transferring to the first drive circuit a timing signal for the first drive circuit to output the first signal, and for transferring to the second drive circuit video data for the second drive circuit to generate the second signal therewith. Video to be displayed on the display device is periodically supplied to the display control circuit as video information from the outside. In general, the period is called a frame period during which video is displayed over an entire area of the pixel array once. This video information is composed of lateral-direction data read out per horizontal scanning period during one vertical scanning period. Usually, the first and second directions of the pixel array correspond to horizontal and vertical scanning directions, respectively.
In the display device of the above configuration, in an embodiment of the present invention, one frame period includes a first time interval and a second time interval, the first drive circuit supplies one first signal to plural adjacent ones of the plurality of first signal lines during the first time interval and supplies another first signal to the plural adjacent ones of the first signal lines during the second time interval. During the first time interval, the second drive circuit generates the second voltage corresponding to the video data and supplies the second voltage to ones of the plural pixels associated with the plural adjacent ones of the first signal lines supplied with the first signal, and during the second time interval, the second drive circuit generates the second voltage and supplies the second voltage to ones of the plural pixels associated with the plural adjacent ones of the first signal lines supplied with the first signal such that the ones of the plural pixels associated with the plural adjacent ones of the first signal lines supplied with the first signal produce luminance lower than that produced during the first time interval.
In another embodiment of the present invention, the plurality of first signal lines are divided into a plurality of groups each comprising plural adjacent ones of the first signal lines, and one frame period includes at least two scanning periods. The first drive circuit supplies the first signal to the plurality of groups successively during each of the at least two scanning periods with all of the first signal lines of each of the plural groups being supplied with the first signal at one time. During at least one of the at least two scanning periods disposed at a beginning of the frame period, the second drive circuit generates the second voltage corresponding to the video data and supplies the second voltage to ones of the plural pixels associated with one of the plural groups of the first signal lines supplied with the first signal, and during at least one of the at least two scanning periods disposed at an end of the frame period, the second drive circuit generates the second voltage and supplies the second voltage to ones of the plural pixels associated with one of the plural groups of the first signal lines supplied with the first signal such that the ones of the plural pixels associated with the one of the plural groups of the first signal lines supplied with the first signal produce luminance lower than that produced during the at least one of the at least two scanning periods disposed at the beginning of the frame period.
In a similar manner, in a method of driving a display device including a pixel array having a plurality of pixels arranged in rows extending in a first direction and columns extending in a second direction intersecting the first direction, a plurality of first signal lines extending in the first direction and arranged in the second direction, and a plurality of second signal lines extending in the second direction and arranged in the first direction, the method comprises: (a) generating a video signal to be supplied to each of the plurality of pixels, and a scanning signal for determining a timing for supplying the video signals to the plurality of pixels, based upon video information per frame period supplied to the display device; (b) selecting the rows of the pixels successively during the frame period by outputting the scanning signal to respective ones of the plurality of first signal lines; and (c) supplying the video signals to ones of the plurality of pixels belonging to the selected rows of the pixels via the plurality of second signal lines, wherein the plurality of first signal lines are divided into a plurality of groups each comprising plural adjacent ones of the plurality of first signal lines, the method includes: (1) at least two scanning steps for outputting the scanning signal to the plurality of groups of the first signal lines successively, during the frame period with all of the first signal lines of each of the plurality of groups being supplied with the scanning signal at one time; (2) supplying the video signals to ones of the plurality of pixels associated with one of the plurality of groups of first signal lines supplied with the scanning signal by at least one of the at least two scanning steps disposed at a beginning of the frame period, and (3) supplying a voltage to ones of the plurality of pixels associated with one of the plurality of groups of first signal lines supplied with the scanning signal by at least one of the at least two scanning steps disposed at an end of the frame period such that the ones of the plurality of pixels associated with the one of the plurality of groups of first signal lines supplied with the scanning signal produce luminance lower than that produced during the at least one of the at least two scanning steps disposed at the beginning of the frame period.
In another embodiment of the display device in accordance with the present invention, when a first video data and a second video data are supplied to the display device of the above configuration, during a first frame period and a second frame period succeeding the first frame period, respectively, a first drive circuit supplies a first signal to a plurality of first-kind groups successively at least two times during the first frame period, and supplies the first signal to a plurality of second-kind groups successively at least two times during the second frame period, where a respective one of the plurality of first-kind groups comprises N adjacent ones of the plural first signal lines, a respective one of the plurality of second-kind groups comprises N adjacent ones of the N first signal lines, the respective one of the second-kind groups of the first signal lines differ from the respective one of the first-kind groups of the first signal lines, all of the first signal lines of each of the first-kind and second-kind groups are supplied with the first signal at one time, the respective one of the plurality of first-kind groups is displaced by n lines of the first signal lines from one of the plurality of second-kind groups which is nearest to the respective one of the plurality of first-kind groups, N is a natural number equal to or greater than 2, and n is a natural number smaller than N. The second drive circuit generates a second voltage corresponding to the video data and supplies the second voltage to ones of the plurality of pixels associated with one of the first-kind and second-kind groups of the first signal lines supplied with the first signal at at least one of the at least two times of supplying the first signal at a beginning of each of the first and second frame periods, and further the second drive circuit generates the second voltage and supplies the second voltage to ones of the plurality of pixels associated with one of the first-kind and second-kind groups of first signal lines supplied with the first signal at at least one of the at least two times of supplying the first signal at an end of each of the first and second frame periods such that the ones of the plurality of pixels associated with the one of the first-kind and second-kind groups of first signal lines supplied with the first signal produce luminance lower than that produced at the at least one of the at least two times of supplying the first signal at the beginning of each of the first and second frame periods.
In another embodiment of the display device in accordance with the present invention, a plurality of first signal lines are divided into a plurality of groups each comprising plural adjacent ones of the first signal lines, a display control circuit of the display device is successively supplied with video information per two successive frame periods, and thereby generating a timing signal for determining a timing for a first drive circuit to output a first signal per frame period, and generates video data used for generation of a second signal by a second drive circuit and blanking data for producing a gray scale level lower than a gray scale level produced by the video data, transfers the timing signal to the first drive circuit, and transfers the video data and the blanking data to the second drive circuit. The first drive circuit supplies the first signal to the plurality of groups successively at least two times during each of a first frame period of the two successive frame periods and a second frame period of the two successive frame periods succeeding the first frame period with all of the first signal lines of each of the plurality of groups being supplied with the first signal at one time, and the second drive circuit generates the second voltage corresponding to the video data and supplies the second voltage to ones of the plurality of pixels associated with one of the plurality of groups of the first signal lines supplied with the first signal at at least one of the at least two times of supplying the first signal in a former half of each of the two successive frame periods, and generates the second voltage based upon the blanking data and supplies the second voltage to ones of the plurality of pixels associated with one of the plurality of groups of the first signal lines supplied with the first signal at at least one of the at least two times of supplying the first signal in a latter half of each of the two successive frame periods. In one of the display devices of the above configuration, the display control circuit compares a second one of the video information corresponding to the second frame period with a first one of the video information corresponding to the first frame period, and generate the blanking data used in the latter half of the first frame period such that the blanking data provides luminance in ones of the plurality of pixels exhibiting a difference in gray scale level between the first and second ones of the video information, different from luminance in a remainder of the plurality of pixels. On the other hand, in another of the display devices of the above configuration, the display control circuit compares a second one of the video information corresponding to the second frame period with a first one of the video information corresponding to the first frame period, and generate the video data used in the former half of the second frame period such that the video data enhances a difference in gray scale level between the first and second ones of the video information in ones of the plurality of pixels exhibiting the difference.
The functions and advantages of the above-described present inventions and the details of the preferred embodiments of the present inventions will become clear from the subsequent explanation.
In the accompanying drawings, in which like reference numerals designate similar components throughout the figures, and in which:
Referring now to the liquid crystal display devices illustrated in Embodiments 1 to 11 and the accompanying drawings related to each of the embodiments, the specific embodiments of the display device in accordance with the present invention will be described.
<Embodiment 1>
This system is constructed as a part of a personal computer or a television set and includes not only a liquid crystal display device or a liquid crystal display module, but also includes a central processing unit (CPU) of the computer for transmitting video data to the liquid crystal display device or liquid crystal display module, a receiver of the television set, and a decoder of a digital versatile disc (DVD) and the like as a video signal source 101
The video data (video signal) generated by or reproduced by this video signal source 101 is received at an interface of the scanning data generator circuit 102, the format of the video data is converted and the picture of the liquid crystal display device is scanned a plurality of times to generate the video data suitable for reproduction. For example, the scanning data generator circuit 102 decomposes the data of the moving image transmitted continuously from the video signal source 101 into data of “picture” displayed on the picture area of the liquid crystal display device for each unit of time called a frame period or a field period described later. Accordingly, the scanning data generator circuit 102 can also be called a plural-time-scanning data generator circuit. The data of “picture” generated in this way is reproduced within the aforesaid unit of time by a plurality of pixels arranged two-dimensionally in the picture area of the liquid crystal display device. Each of the plurality of pixels is provided with an electrode (also called a pixel electrode) to which a voltage corresponding to the video data is applied and an active element or a switching element for applying a voltage to this electrode. In addition, timing of applying a voltage to the electrode is controlled by a scanning signal supplied to the active element or switching element. The voltage applied to each of the pixels in accordance with the video data is generated as a gray scale voltage (also called a video signal) by a drain line drive circuit 105 described later.
This scanning signal is generated by the gate line drive circuit (also called a gate driver or a scanning signal drive circuit) to which a timing signal (also called a clock) generated by a scanning timing generator circuit (a plural-time scanning timing generator circuit) 103 in accordance with the video data generated by the scanning data generator circuit 102. The scanning timing generator circuit 103 is often included in a control circuit of a liquid crystal display device or a liquid crystal display module together with the scanning data generator circuit 102 or part of the scanning data generator circuit 102. This control circuit is called a timing controller.
A picture area (a display area) of the liquid crystal display device having a plurality of aforesaid pixels arranged in a two-dimensional manner is indicated in
Meanwhile, a backlight 107 is mounted on the rear side (a back surface) of the picture area as seen from a user of the liquid crystal display device and is driven by a backlight drive circuit 108 controlled by the scanning timing generator circuit 103 through a backlight control bus 111.
A plurality of pixels 207 (one of them is indicated by an area enclosed by a dotted line) are arranged to form a matrix with m×n. For instance as shown in
The aforesaid video signal is supplied as a gray scale voltage (described later) from the aforesaid drain line drive circuit 105 to the drain line 203 and applied to one of the electrodes forming the aforesaid capacitor 206 through the TFT 204 that is turned on or off with the scanning signal applied in sequence from the aforesaid gate line drive circuit 104 to the gate line 201. Incidentally, in the specification of the present invention, it is conveniently defined such that, irrespective of a potential between the capacitor 206 of the TFT 204 having a field effect transistor structure and the drain line 203, the former is called a source and the latter is called a drain. A holding capacitor 205 (Cstg type) in the pixel 207 is formed between the source of the TFT and a common signal line 202.
As long as the liquid crystal display device has a field effect transistor as an active element, the equivalent circuit shown in
When a television video signal is received with such a display device, the block diagram of
The resolution of the pixel-element array 106 is defined by the number (m) of a plurality of pixels 207 arranged in a row direction (a horizontal direction) and the number (n) of a plurality of pixels 207 arranged in a column direction (a vertical direction), which pixels are arranged in an effective display area of the display device shown in
Meanwhile, the resolution of the video data inputted to the receiving circuit through television broadcasting is classified as a vertical resolution of 480i or 480p for 480 scanning lines (the pixel row composed of a plurality of pixels arranged in the horizontal direction) arranged in a vertical direction of the picture area, 720i or 720p for 720 scanning lines, and 1080i or 1080p for 1080 scanning lines, for example. This vertical resolution corresponds to the number (n) of pixels (strictly speaking, the number of pixel rows) arranged in a column direction (a vertical direction) in the effective display area of the display device. Characters (i) and (p) affixed to the vertical resolutions indicate the video data received by the interlace mode and those received by the progressive mode, respectively. In the case where the number of pixel rows in the vertical direction of the video data received is different from that in the effective display area of the display device, the conversion of resolution, the so-called scaling is carried out by the aforesaid receiving circuit.
Each of the video data inputted to the receiving circuit is divided into odd line data and even line data; the odd line data means that the pixels in the display device corresponding to the video data belong to the odd pixel rows when counted in a vertical direction from the upper side in the effective display area; and the even line data means that the pixels in the display device corresponding to the video data belong to the even pixel rows when counted from the upper side of the effective display area. In the aforesaid interlace mode, the video data composed of odd line data and the video data of even line data are inputted alternatively to the receiving circuit for each field period. Each field period where the odd line data or even line data is inputted to the receiving circuit is 16.7 ms (millisecond), for example, and the odd line data and the even line data are inputted to the receiving circuit with the period of 33 ms (30 Hz in terms of frequency) are inputted to the receiving circuit. In contrast to this, in the aforesaid progressive mode, the odd line data and the even line data are inputted to the receiving circuit in the frame period of 16.7 ms (60 Hz in terms of frequency). The video data inputted to the receiving circuit in the interlace mode is expanded by the receiving circuit for each field period and the video data inputted to the receiving circuit in the progressive mode is expanded by the receiving circuit for each frame period and the aforesaid processing is performed. The processing for this video data is carried out in the video signal source 101 and part of the scanning data generating circuit 102 shown in
The video data 121 inputted to the timing controller 114 is once stored in any of either a memory M1 or a memory M2 for each frame period or field period described above and then transmitted to the aforesaid drain line drive circuit 105 in response to a clock signal generated by the display control signal (an external clock signal) 122 sent from the receiving circuit 113 to the timing controller 114. This state is schematically illustrated in
The data groups for each pixel row forming the video data 121 inputted to the timing controller 114 in the display device applicable to the color video display are formed such that a datum associated with each of the pixels 207 arranged side by side in a horizontal direction of the pixel array 106 is arranged in sequence according to color, i.e., red (R), green (G) and blue (B). In
Meanwhile, the timing controller 114 processes the display control signal 122 inputted together with the video data 121 with a frequency divider circuit incorporated therein or the like and produces a frame memory control signal 124 for use in reading out the video data 123 from the memory, a clock signal for use in adjusting timing where a video signal (a voltage signal applied to the pixel) is produced by the drain line drive circuit 105 in accordance with the video data 121, and a scanning start signal FLM, a scanning clock signal CLS or the like for adjusting timing where the video signal is applied to each of the pixels in the pixel array. In the timing controller 114, a timing signal required for the display device (a display module) is produced by the scanning timing generator circuit 103 shown in
The timing controller 114 produces several kinds of gray scale voltages in accordance with the video data, in common to red, green and blue and sends them to the drain line drive circuit 105 so as to display a desired image at the pixel array 106 by the video data sent to the drain line drive circuit 105. In
Inputting of the video data into the display device (display module) and the processing of the video data at the display device described above can be applied not only to a liquid crystal display device, but also to such a display device as one in which either an electroluminescent element (EL element) or a field emission element (FE element) is arranged for each pixel. Accordingly, although a drive mode of the display device in accordance with the present invention will be described under an assumption that the device is the liquid crystal display device, it is apparent that this drive state can be applied to the display device or the like using electroluminescent elements. Incidentally, although the liquid crystal display apparatus is sometimes provided with dummy pixels, dummy pixel rows and dummy pixel columns, on the periphery of the aforesaid effective display area, the pixels except those of the effective display area and their drive modes are omitted in the following description unless otherwise specified.
In the case where the video data is inputted to the liquid crystal display device in the interlace mode, the video signal to be inputted to the pixel groups of the odd lines and the video signal to be inputted to the pixel groups of even lines are alternatively generated for each frame period 301 shown in
Operation for inputting either the video signal or the blanking signal into the pixel in the pixel array as described above is referred to as data writing to the pixel. In addition, a plurality of pixels 207 arranged along the aforesaid gate line 201 (in other words, forming pixel rows) in the pixel array shown in
The active elements (switching elements, the TFT 204 in the present embodiment) arranged in each of the selected pixels are turned on within the scanning signal input period and then a voltage corresponding to the video signal or the blanking signal is applied to one of a pair of electrodes (also called the pixel electrode) forming the capacitor 206 in
As described above, the operation in which either applying of voltage to the pixel electrode or carrier injection into the electroluminescent element in each of the pixel groups driven by either a specified gate line or a specified scanning signal line and the like is carried out for the video signal and for such another object as blanking signal or the like is called data writing to the line. The line used in the following description means a signal line for controlling the active element arranged at a specified pixel group such as a gate line or a scanning signal line etc. unless otherwise specified. In addition, the operation of writing data into the line means that the active element is controlled by the gate line or the scanning signal line specified as the specified line, and a predetermined voltage is applied to a pixel electrode connected to this active element or a predetermined amount of carriers is injected into a light emitting element such as an electroluminescent element connected to this active element.
In the case of performing the drive mode shown in
As shown in the timing chart of
In the operation of the 2-lines simultaneous write-in (2-lines skip-scanning), gate lines G1, G2 are selected simultaneously within the video write-in period 302, images are written into the two pixel rows, then gate lines G3, G4 are selected while skipping the gate lines G1, G2 and images are written into the two pixel rows. The same images are written for each pixel column to the two pixel rows corresponding to the pair of gate lines and to the two pixel rows corresponding to the gate lines G3, G4 within the period in which the gate lines G1, G2 are selected.
This 2-lines simultaneous write-in operation will be described as follows in reference to a driver data output from the timing converter 114 in
At first, in the case where driver data is outputted in the interlace mode, the pixel groups PIX(1, 1), PIX(2, 2), . . . PIX(m, 1) corresponding to the gate line G1 and the pixel groups PIX(1, 2), PIX(2, 2), . . . PIX(m, 2) corresponding to the gate line G2 are selected and the video signal to be supplied to any one of these pixel groups are supplied to two pixel groups. For example, a video signal to be supplied to PIX(5, 1) in the first row is supplied to both the pixels of pixel PIX(5, 1) in the first row and pixel PIX(5, 2) in the second row, and a video signal to be supplied to PIX(m−1, 1) in the first row is supplied to both the pixels of pixel PIX(m−1, 1) in the first row and pixel PIX(m−1, 2) in the second row. Then, the pixel groups PIX(1, 3), PIX(2, 3), . . . PIX(m, 3) in the third row corresponding to the gate line G3 and the pixel groups PIX(1, 4), PIX(2, 4) . . . PIX(m, 4) in the fourth row corresponding to the gate line G4 are selected and a video signal to be supplied to any one of these pixel groups in the third row or pixel groups in the fourth row is supplied to both the pixel groups of the third row and pixel groups of the fourth row. For example, a video signal to be supplied to the pixel PIX(5, 3) in the third row is supplied to both the pixel PIX(5, 3) in the third row and the pixel PIX(5, 4) in the fourth row, and a video signal to be supplied to the pixel PIX(m−1, 3) in the third row is supplied to both the pixel PIX(m−1, 3) in the third row and the pixel PIX(m−1, 4) in the fourth row. Subsequently, a similar operation is repeated until it reaches the gate line (Gn in
Also in the case where the driver data is outputted in the progressive mode, supplying of the video signal to the pixel group corresponding to the gate line G1 and the pixel group corresponding to the gate line G2 or the pixel group corresponding to the gate line G3 and the pixel group corresponding to the gate line G4 is carried out in the substantial same procedure as that of the aforesaid interlace mode. However, the driver data outputted in the progressive mode prohibits occurrence of the video signals in the pixel groups corresponding to any one of the odd-numbered gate lines G1, G3, G5, . . . or the even-numbered gate lines G2, G4, G6, . . . because the video signals in the pixel groups corresponding to all gate lines arranged in the effective display area of the display device are generated by the drain line drive circuit.
When such video writing into the pixel groups of two rows corresponding to a pair of gate lines is carried out at the same speed as that of video writing into the pixel group in one row corresponding to one conventional gate line, the video writing (video writing corresponding to either one frame or one field) into the pixels (hereinafter referred to as a pixel array) corresponding to all the gate lines arranged in the effective display area is completed in a half of the period of time required for the conventional video writing (one frame period or one field period). As described above, the period of time for writing the video into the pixel array of the display device is often dependent on a period of time required for inputting the video data 121 corresponding to one frame or one field to the display device. Accordingly, introduction of the 2-lines simultaneous write-in operation in accordance with the present invention in the display device enables the remaining half of one frame period or one field period where the video data 121 is inputted to this display device to be utilized as a scanning period in which another signal can also be written into the pixel array. This is also apparent from the fact that the video writing in the frame period 301 (corresponding to either one frame period or one field period in which the aforesaid video data 121 is inputted to the display device) described in reference to
In accordance with the present invention, the blanking data (black data is preferable) is supplied to the pixel array through the aforesaid simultaneous write-in (2-line skip-scanning) in this new generated scanning period (the blanking scanning period 303 in
When the blanking data is written into the array, a full scanning period for the video data and the blanking data can be further shortened by a scanning method different from that of the video data writing-in operation if the 2-line simultaneous write-in and 2-line skip-scanning is performed at the time of writing-in of the video data and if the 4-line simultaneous write-in and 4-lines skip-scanning is performed at the time of writing-in of the blanking data. However, as an interval error between a video signal applying time for the pixel group corresponding to each of the gate lines and a blanking signal applying time among the gate lines (scanning signal lines) is made low, non-uniformity in display at the picture of the display device is suppressed, so that the above scanning method is carried out by the same scanning method for the video data writing-in operation and the blanking data writing-in operation in the present embodiment.
In the present embodiment, since the same data is written in the plurality of lines in a simultaneous manner, this operation can be completed within the conventional writing-in period. However, simultaneous writing-in of data into the plurality of lines causes the number of pixel electrodes to which a voltage is applied to increase twice or more in the liquid crystal display device, it is highly probable that the writing-in current required for this operation is increased more than that of the prior art. However, in view of supplying capability of writing-in current of the drain line drive circuit 105, inversion of the aforesaid writing-in polarity for each frame period 401 enables an increase in the required writing-in current value to be suppressed, so that the writing-in characteristic is maintained while suppressing a load on the display module, thereby improving the display module. The waveform 406 of the drain line drive voltage output from the drain line drive circuit 105 to the drain line 203 is changed into an alternation form in such a way that the video signal and the blanking data are written in the same polarity for each one frame period (a signal voltage corresponding to each of the data being set to a higher or lower level than a potential of the aforesaid common level 408). For this reason, in the case where the same data is always written in each of the blanking periods for each frame period, the polarity of voltage signal corresponding to the blanking data is inversed for each frame period 401, whereby a dc-induced image retention generated when the same polarity is kept over the plurality of frame periods is suppressed.
The solid curve 407 denotes a source voltage waveform, the solid line 408 denotes a common level and then a differential voltage between them is applied to the liquid crystal. In the case where a liquid crystal cell provided in each pixel is assumed to be a capacitor 206 shown in
After this operation, when the blanking data is written into the pixel in the rear half of one frame period 401 or the blanking period 403, the light transmission of the liquid crystal layer is gradually decreased and it is changed to a black level immediately before the end of the blanking period (or one frame period 401). In this way, each of the light transmissions in the liquid crystal layer corresponding to the pixel is set to a desired value in accordance to a video response for each frame period and subsequently the light transmission is set to the minimum value in accordance to black response. These operations are repeated to provide an optical characteristic similar to an impulse type optical characteristic to the liquid crystal display element having a hold-type display characteristic, thereby improving its moving image displaying performance.
The light transmission of the liquid crystal layer shows a steep impulse-like variation with respect to a video signal as an optical response characteristic of the liquid crystal composition constituting this liquid crystal layer is made faster and also a convergence to a minimum value (the so-called black level) with respect to the blanking signal is made faster. For this reason, when an optical response in the liquid crystal is made faster, an image (in particular, a moving image) reproduced in the display device becomes clearer. However, it is possible that a holding characteristic of an electric field applied to the liquid crystal layer for a frame period is impaired. In the case where a still image is reproduced by a liquid crystal display device, for example, it is not necessary to change brightness of most of the pixels constituting the pixel array, so that it is desirable that the light transmission in the liquid crystal layer is also kept (held) at a predetermined value over a plurality of frame periods.
As a result of the adaptation of the display device for performing a hold-type displaying operation to the moving image display as described above, it may be expected that the contrast or display-uniformity of the displayed image is deteriorated when the display device is mounted in a hold light emitting type monitor for a personal computer and the like. In the liquid crystal display device in accordance with the present embodiment, liquid crystal composition having a well-balanced state between the response to an electric field signal and a holding characteristic is applied to the liquid crystal layer described above so as to enable the liquid crystal display device to be used in both a television receiver and a monitor. If the liquid crystal device in accordance with the present embodiment is exclusively used for displaying a moving image in a television receiver and the like, it is desired that the liquid crystal composition showing a high-speed optical response characteristic be used for the liquid crystal layer.
In the foregoing description in accordance with the present embodiment, it has been assumed that a pixel array (a liquid crystal display element) in a normally black mode (the lower a voltage applied to a pixel electrode, the lower a light transmission of the liquid crystal layer) is driven by dot inversion driving. However, also in the case of a pixel array (a liquid crystal display device) operated in a normally white mode (the lower a voltage applied to a pixel electrode, the higher a light transmission of the liquid crystal layer), this pixel array is operated by the common inversion driving so as to achieve the same effect as that obtained by the pixel array in the normally black mode. In order to further improve an image quality of the displayed image, a gray scale controlling function described below is added to the aforesaid liquid crystal display device in accordance with the present embodiment.
An optical response characteristic in a liquid crystal layer is dependent on either a gray scale voltage value applied to the liquid crystal layer or its applying time. Due to this fact, probably, there arises the possibility that the relationship between a gray scale data inputted to the liquid crystal display panel and brightness characteristics (γ-characteristics) of the liquid crystal display panel is dependent on the following two cases: one case where only a video signal is written into each of lines forming a pixel array for each frame period or each frame field as described above (hereinafter conveniently referred to as impulse type operation or impulse type scanning); the other case where the video signal and the blanking signal are written in sequence to each of the lines forming the pixel array in accordance with the present invention.
In view of this possibility, the present embodiment additionally provides means for applying a gray scale voltage suitable for an impulse type operation (for example, another gray scale voltage generating circuit different from that described below) in addition to the gray scale voltage applying means installed in the prior art liquid crystal display device (e.g., the gray scale voltage generating circuit for generating a gray scale voltage suitable for the hold-type operation) in order to correct a deviation in γ-characteristics generated between the hold-type operation and the impulse type operation of the liquid crystal display device. As one example for generating a gray scale voltage suitable for performing an impulse type operation, a combination of a gray scale voltage dividing resistor (generating much more gray scale voltage from a gray scale voltage inputted to a drain line drive circuit) arranged in the drain line drive circuit 105 such as a drain driver IC is changed over by a switch in compliance with the aforesaid operating system (including at least two kinds of hold-type system and impulse type system) and thereby a γ-characteristic curve (e.g., a curve indicating each of the gray scales and either a voltage applied to its corresponding pixel electrode or an electric field applied to a liquid crystal layer) is changed. In addition, as another example for generating a gray scale voltage suitable for impulse type operation, a scanning timing generator circuit 103 for generating a gray scale voltage (refer to
In the present embodiment, there is employed another example described above in which the gray-scale-voltage groups generated by the scanning timing generator circuit in accordance with an operating mode of the liquid crystal display device are switched, and the details thereof will be described later in reference to
The circuit block groups are arranged at the scanning timing generator circuit in the display control circuit, and the ten types of gray-scale-voltage groups as described above are devidedly generated for the hold-type operation and impulse-type operation. Each of the gray scale voltages for the hold-type operation is outputted from between each pair of resistor elements of a voltage divider having a plurality of resistor elements connected in series called ladder resistors 502. Each of the gray scale voltages for impulse type operation is outputted from between each pair of a plurality of resistor elements forming the voltage divider constituted by the ladder resistors 503. Although both the ladder resistors 502, 503 have a similar constitution to each other, plotting the gray scale voltages to the respective levels ranging from the level 0 to the level 9 forms γ-characteristic curves different from each other. The gray-scale-voltage groups outputted from the ladder resistors 502 are inputted to an analog switch 506 through a gray-scale-voltage bus 504 constituted by ten signal lines for use in transferring each of the gray scale voltages, and the gray-scale-voltage groups outputted from the ladder resistors 503 are inputted to the analog switch 506 through the gray-scale-voltage bus 505 constituted by ten signal lines for use in transferring each of the gray scale voltages.
A selection signal line 501 is also connected to the analog switch 506 and a signal transmitted through this selection signal line causes the analog switch 506 to acknowledge an operation status of the liquid crystal display device (selected from both the hold type scanning and the impulse type scanning). The analog switch 506 selects the gray-scale-voltage groups transmitted from the ladder resistors 502 through the gray-scale-voltage bus 504 when the liquid crystal display device is in the hold-type operation status, and, selects the gray-scale-voltage groups transmitted from the ladder resistors 503 through the gray-scale-voltage bus 505 when the liquid crystal display device is in the impulse-type operation status. The gray-scale-voltage groups selected by the analog switch 506 are supplied to the drain line drive circuit 105 through the selected gray-scale-voltage group bus 508 after they are outputted to a buffer 507 arranged at the subsequent stage.
The selected gray-scale-voltage group bus 508 has ten signal lines arranged for each of the gray scale voltages in the same manner as that of the gray-scale-voltage buses 504, 505. The structure of any of the bus lines corresponds to the drain drive circuit that causes the liquid crystal display panel to perform the color video display drive of 64 scales. Accordingly, if the drain drive circuit that causes the liquid crystal display panel to perform the color video display drive of 256 scales is mounted, these bus line widths are widened.
As described above, gray scale voltages corresponding to the predetermined gray scale levels are allowed to depend on whether the liquid crystal display device is operated by a hold-type scanning or an impulse-type scanning, so that the γ-characteristics suitable for the respective scanning methods are set. Consequently, a deviation in the optical characteristics in the impulse-type scanning is corrected. In addition, the liquid crystal display device operated by the impulse type scanning also enables the generation of steep γ-characteristics as found in a Braun tube and its video quality is improved.
Further, another application example of the present embodiment can operate the liquid crystal display device by the following scanning method.
When the overdriving scheme is employed, video signals per frame period are supplied to respective pixels in a display area of the display device more than twice in one frame period (or in another frame period succeeding the one frame period). Therefore, each of times one pixel can use for taking in a video signal via its active element once, which is a time duration during which the active element is in an ON state, is shortened, and consequently, although the active element of each pixel is turned on more than twice per frame period, the amount of electric charge taken into one pixel is limited because of the short duration of one turned-on state of the active element. The liquid crystal speed-up filter increases the amount of charge taken into one pixel by one turn-on of the active element by increasing a video signal voltage, and thereby accelerates orienting of liquid crystal molecules into a desired orientation in the case of the liquid crystal display device.
The frame period 701 shown in
A voltage signal having the gate waveform (a scanning signal waveform) 706 is applied to the gate line (a scanning signal line) 201 as shown in
The optical response waveform 710 of the liquid crystal layer indicates that a light transmission of the liquid crystal layer in the ¼ frame period changing over from the blanking display state in the previous frame period to the video display state of the frame period subsequent thereto is steeply increased as compared with that in the video write-in period 402 in
In the liquid crystal display device of the present applied example, the blanking signal at the end of the frame period is written into each of the lines for each frame period. If a voltage (a black level signal) making a light transmission of the liquid crystal layer minimum is applied to each of the pixels (a pixel electrode arranged in the liquid crystal layer) as this blanking signal, the effective display area (a pixel array) of the liquid crystal display device is displayed black at the end of the frame period (in other words, before the video in the subsequent frame period is written into each of the lines). Accordingly, in this case, it is possible to control an optical response of the liquid crystal layer in accordance with the write-in of the video signal supplied in the subsequent frame period into each of the lines by setting an initial rising value of light transmission of the liquid crystal layer to a black level. Therefore, it is also possible to simplify a combination of filter factors of the aforesaid fast responding filter and realize this filter circuit by a low scale of integration in circuit. In addition, an inversion repetition period of a write-in polarity can be completed in each of a video write-in period (composed of the aforesaid first video signal write-in period 702 and the second video signal write-in period 703) and a blanking signal write-in period 704 as indicated by the source waveform 708 in
The scanning timing generator circuit (plural-time scanning timing generator circuit) 103 indicated in
One video image 802 shown in
When this video image 802 is inputted to the scanning timing generator circuit 103, a timing signal corresponding to the so-called 2-line simultaneous write-in operation (in the case of the present applied example) is generated by the scanning timing generator circuit 103. When this timing signal (also called a scanning clock) is inputted to the gate line drive circuit 104, the gate line drive circuit 104 drives the gate line of the pixel array 106 with the timing shown in
The drain line drive circuit 105 generates a video signal for each row address from data of one video image 802 in accordance with this gate line drive and outputs it to each of the drain lines 203 arranged at the pixel array 106. As described above, in the present application example in which the liquid crystal display device is driven by the 2-line simultaneous write-in operation, one of the odd-numbered lines (G1, G3, . . . Gn−1) and the even-numbered lines (G2, G4, . . . Gn) of one video data 801 having the same vertical resolution as that of the pixel array 106 is arranged in sequence in the row address group ranging from the upper first row to (n/2)th row of one video data 802 and the other lines are removed. Due to this fact, the drain line drive circuit 105 repeats n/2 times a production of the video signal for each line belonging to any of groups on the basis of information corresponding to only one of the odd-numbered lines and the even-numbered lines of the aforesaid one video data 801.
The video write-in operation into each of the lines corresponding to the aforesaid example of driving the gate line is described as one example of making the even-numbered lines for the video data 801 invalid. Each of the video signals for the line G1 of the video data 801 is supplied to the pixel groups of two rows corresponding to the gate lines G1, G2 in accordance with the aforesaid first pulse; each of the video signals for the line G3 of the video data 801 is supplied to the pixel groups of two rows corresponding to the gate lines G3, G4 in accordance with the aforesaid second pulse; and each of the video signals for the line Gn−1 of the video data 801 is supplied to the pixel groups of two row corresponding to the gate lines Gn−1, Gn in accordance with the aforesaid (n/2)th pulse. With such an arrangement as above, a video image (hereinafter also called a target video image) illustrated in
After completion of the video write-in into the pixel array 106 as described above, the voltage signal corresponding to the invalid video present at the row address subsequent to ((n/2)+1)th address from the upper side of said one video 802 is supplied from the drain line drive circuit 105 to the pixel array 106 in the same manner as that for the aforesaid video signal. This operation is carried out in the blanking scanning period 303 in
In another example of the method for forming the dummy video image, the aforesaid one video image 802 is inputted to the scanning timing generator unit 103 and the row address subsequent to ((n/2)+1)th address from the upper side of this video image 802 is masked with the dummy data. In accordance with this method, even if information fed, from the upper side, to the first row address to (n/2)th row address is written into the ((n/2)+1)th row address to the nth row address from the upper side of the one video image 802 when one video image 802 is generated by compression of one video data 801 at the aforesaid scanning data generator unit 102, this information can be substantially eliminated from the ((n/2)+1)th to the nth row address. The dummy data herein described is used for applying the blanking signal (a signal voltage set irrespective of the video image 801 inputted to the liquid crystal display module) from the aforesaid drain line drive circuit 105 to the drain line 203 in the same manner as that for the aforesaid dummy video and this dummy data can be set as the aforesaid black data. However, the dummy data is not inputted to the row addresses of ((n/2)+1)th to nth addresses from the upper side of the aforesaid one video 802. Therefore, the feature of the dummy data is different from that of the video data of the aforesaid dummy data. That is, the aforesaid dummy data is utilized for generating a signal voltage in the drain line drive circuit 105 in a period in which the signal voltage can be generated by the drain line drive circuit 105 in accordance with information stored at the row addresses of ((n/2)+1)th to nth addresses from the upper side of the aforesaid one video 802 in place of this information.
The invalid video data generated as described above (the lower half, displayed in black, of one video 802 in
One video data 801 shown in
Further, in the case where the video signals or the blanking signals are written while the pixel groups corresponding to four lines (corresponding to four gate lines) are selected simultaneously in reference to the present application example in which the liquid crystal display device is driven by the 2-line simultaneous write-in operation, a selection pulse is supplied to the gate line of the pixel array 106 with the timing shown in
The scanning data generator circuit 102 compresses to ¼ a vertical resolution of an original image 901 inputted to this circuit. In one example of this compressing process, data of the original image 901 which has the same vertical resolution as that of the pixel array or which is processed to have such a vertical resolution other than data corresponding to (multiple number of 4)th line in the pixel array is made invalid. That is, data included in the original image 901 is divided into four groups in accordance with the associated lines of the pixel array. In addition, data belonging to three groups are made invalid and data belonging to the remaining group is arranged in sequence from the upper side in a vertical direction in one intermediate video 902 (refer to
In the present application example, the original image data constituting the video image 904 (data only at (multiple number of 4)th line, for example, selected from the original image 901) is emphasized by the fast-responding filter in order to speed-up the response (rising of light transmission) of the liquid crystal at the start of one frame period. In contrast to this, the original video data constituting the video image 905 is not subjected to such an emphasizing process. Accordingly, in the present application example, the video image 904 and the video image 905 are conveniently distinguished from each other as an emphasized image and a non-emphasized image, respectively.
The intermediate video 902 is generated in such a way that the emphasized video 904, non-emphasized video 905 and invalid video 906 resulting from the vertical compression of the original image into ¼ from the upper side of one video image corresponding to one frame period of the original image are arranged in sequence and then the intermediate video image 902 is transferred to the scanning timing generator circuit 103 shown in
In addition, the invalid video image 906 in the present application example is not limited to one generated by the scanning data generator circuit 102 as described above. The invalid video image may be formed in the following manner. An operation for generating the aforesaid non-emphasized video 905 by the scanning data generator circuit 102 in a period where the invalid video 906 is generated is repeated, the non-emphasized video 905 is stored in an area where the invalid video 906 of the intermediate video 902 should be inputted, the intermediate video 902 is inputted to the scanning timing generator circuit 103, and the area to be made as the invalid video image 906 is masked with the blanking data.
A basic system configuration and an operation of each of the component elements thereof that represent the present invention have been described above. Subsequently, some points to be considered in particular when this basic system is applied to a product such as a television receiver or the like will be described and a method for providing a counter-measure by the system configuration of the present invention will be described in detail.
A point to be considered at first consists in the possibility that the vertical resolution of an image displayed in video equipment is reduced because the method in accordance with the present invention is a scanning method for writing the same scanning data in a plurality of lines. Accordingly, it is also argued that the number of lines to be written simultaneously is preferably as less as possible. However, a trend in recent years shows that a display array having a higher resolution goes mainstream and various kinds of video formats such as digitalized broadcasting, broadband broadcasting, and video services or the like are realized. In view of such a trend in era as described above, the aforesaid argument can resolved by considering the optimum formation of the embodiment of the present invention applicable to a product such as video equipment and the like in consideration of a relation between a resolution of the display array and a video format. Subsequently, on the occasion of discussing the countermeasure, a combination of the display array and the video format will be explained at first.
As regards a standard in product of the liquid crystal display device,
For example, the pixel array with a class (resolution) of XGA (Extended Graphics Array) has a pixel matrix such as (a horizontal resolution)×(a vertical resolution)=1024×768, so that an aspect ratio of the pixel array becomes 4:3. On the other hand, the pixel array with a class of WXGA (Wide Extended Graphics Array), which can be also called a wide version of class XGA, forms a matrix of 1280×768, so that an aspect ratio has a longer lateral size as compared with that of XGA class. A trend in which the aspect ratio has a longer lateral size as described above is caused by some reasons that the aspect ratio in the video signal format is becoming wide toward 16:9 or that an adaptation for multi-media is also penetrated into the liquid crystal display device and the like.
Affix letter (i) attached to the end part of the number of effective scanning lines means that the video data having a vertical resolution of the number of effective scanning lines is transmitted or received through the scanning of an interlace process. In addition, affix letter (p) attached to the end part of this number of effective scanning lines means that the video data having a vertical resolution of this number of effective scanning lines is transmitted or received through the scanning of a progressive process. As described above, since the video image to be transmitted or received in practice by the interlace scanning in one field period is only data of either the odd-numbered line or even-numbered line, the vertical resolution is half of that of the video image to be transmitted or received through a progressive scanning. In order to keep compatibility with a displaying standard of the prior art personal computer and the like while coping with the trend of the wide formation of the video format or the multimedia targeted liquid crystal display device, the plural-time-scanning data generator circuit 102 shown in
Referring to
In
Referring to
In this case, a method for displaying the video image in each of the pixel arrays is selected in the following manner in accordance with an aspect ratio in a horizontal direction between each of the pixel arrays and a video image (a video data) displayed in the pixel array. In the case where an aspect ratio of the video image in a horizontal direction is wider (broader) than that of the pixel array, the video image is generated at the pixel array by the displaying method described above in reference to
In
In the case where a video having an aspect ratio of 4:3 is displayed at a pixel array of WVGA class having a horizontal resolution of 800 and a vertical resolution of 480 (an aspect ratio=5:3), for example, an aspect ratio of the video image along the horizontal direction is narrower than that of the pixel array, so that a vertical resolution of the video is allowed to coincide with that of the pixel array (a vertical resolution: 480) as described in reference to
Meanwhile, the video data transmitted or received through digital broadcasting is based on any one of standards of video formats as shown in
A surplus or lack state of the number of scanning lines of the video data and that in the effective display area in the pixel array will be described more practically in reference to
In the case where the video data having an aspect ratio of 4:3 is displayed at a pixel array of XGA class (a horizontal resolution=1024, a vertical resolution=768 and an aspect ratio=4:3), all the vertical resolution (768 lines) in the pixel array can be utilized in the effective display area because both aspect ratios are equal to each other, resulting in that the number of blanking lines becomes 0 (padding with the blanking data is not required). In the case where this pixel array displays 480i video data with an aspect ratio of 4:3, 528 scanning lines other than 240 effective scanning lines in the effective display area used in the interlace process for each field is supplemented with 480i video data, whereby the video image can be displayed in the entire area of the pixel array without padding 768 scanning lines in the effective display area with the blanking data.
In the case where the video data with an aspect ratio of 16:9 is displayed at the pixel array of XGA class, the aspect ratio of the video data in the horizontal direction is wider than that of the pixel array. Accordingly, the horizontal resolution of the video data is adjusted to coincide with the horizontal resolution 1024 in the pixel array as described above in reference to
On the other hand, in the case where the video data having an aspect ratio of 4:3 is displayed at a pixel array of WXGA class (a horizontal resolution=1280, a vertical resolution=768 and an aspect ratio=5:3), the vertical resolution in the displayed area becomes 768 lines in the same manner as that of XGA class. In this case, since the horizontal resolution of the video data becomes 768×( 4/3)=1024, the aspect ratio is maintained by padding the blanking data having width of total 1280−1024=256 dots on the right and left sides along the horizontal direction in the pixel array. In addition, it is also possible to extend the video data in place of the blanking data in the horizontal direction for displaying.
In the case where the video data with an aspect ratio of 16:9 is displayed in a pixel array of this WXGA class, the number of dots of the video data in the horizontal direction is maintained in such a manner as to coincide with that (1280) of the pixel array, causing the vertical resolution (the number of effective vertical lines required for displaying the video data) to become 1280×( 9/16)=720 lines. Due to this fact, 768 lines arranged in a vertical direction of the pixel array, 720 lines contribute to a formation of the effective display area shown in
Then, a vertical resolution of the displayed video image to which the aforesaid embodiment (and its application example) of the present invention is applied will be discussed in reference to an operation of the display device for generating video data in the effective display area formed in each of the pixel array of XGA class and the pixel array of WXGA class and each of the pixel arrays as described above.
At first, it is assumed that a video image of 480i having an aspect ratio equal to that of a pixel array of XGA class is displayed in the pixel array. The video signal of 480i has its vertical resolution of 240 since the number of effective scanning lines required for scanning with a frequency of 60 Hz for each field period is only 240 lines. Accordingly, a vertical resolution (768) of the pixel array of XGA class becomes not less than 3 times that of the video data of 480i for each field period. Therefore, even if this video data is inputted to the pixel array by 2-line simultaneous write-in operation (2-line skip scanning) or the like to supplement a video signal to the surplus scanning lines in the pixel array, deterioration in video quality is relatively less generated since information of the video data in a vertical direction is not lost. That is, in the combination of the pixel array and the video data, the video data and black data are scanned in sequence in the pixel array in accordance with the aforesaid embodiment of the present invention to cause the pixel array to perform a blanking display operation for each field period, whereby an improvement of moving image display characteristic and its image quality can be accomplished.
Next, an example will be discussed in which video data of 1080i having an aspect ratio different from that of a pixel array of XGA class and having a higher vertical resolution than that in the effective display area formed at the pixel array in dependence on the aspect ratio is displayed. In this example, the vertical resolution of the effective display area of the pixel array with respect to the vertical resolution of 1080 lines of the video data becomes 576 lines as shown in
In view of the foregoing, some optional examples are proposed as operations for displaying video data suitable for improving an effect of blanking operation in the pixel array in accordance with the present invention, the present inventor has considered several options.
In view of the foregoing,
Since the aforesaid frame period 1501 is also a period for completing the scanning corresponding to the vertical resolution (768 times in this case) of the pixel array, if the video data and the blanking data are written into the pixel array in the front half 1502 and the rear half 1503 of this period, respectively, the period assigned to both the operations is a period for completing the scanning of 384 times. Since it is necessary to input data into the aforesaid respective blanking scanning areas for both the video write-in period 1502 and the blanking period 1503, if this is completed by the scanning of 48 times scanning as described above, the remaining scanning of 336 times (=384−48) enables the video data or the blanking data to be inputted into the aforesaid effective display area. In the case where a video having an aspect ratio of 16:9 is displayed at a pixel array having a vertical resolution of 768 lines and an aspect ratio of 4:3, the data is inputted in 576 lines constituting the effective display area of the pixel array in a scanning period corresponding to the aforesaid 336 lines. Therefore, of the scanning of 336 times, 240 times are carried out by the 2-line simultaneous write-in operation (2-line skip scanning) and the remaining scanning of 96 times are carried out for each one line (in such a way that data corresponding to one line is inputted for each one line in the pixel array).
In place of the displaying method described above in reference to
Further, a description will be made of an example in which a video image (its aspect ratio=16:9) according to a format of 1080i is displayed at the pixel array of WXGA class. In the pixel array of WXGA class, the number of lines in the effective display area (vertical resolution) capable of displaying the video data having an aspect ratio of 16:9 as shown in
Although the effect of the present embodiment of the present invention in view of the moving image display at the pixel array has been described in the foregoing, the contents of broadcasting are not limited to the moving image, but they contain many still images. In addition, some display device users demand to watch a moving image in favor of the vertical resolution. Further, the vertical resolution is preferentially always applied in some cases if the display device has a function of reproducing and displaying the video image photographed with a digital camera or the like at the display device (or audio visual equipment having the display device mounted thereon). In addition, either the display device or the audio visual equipment has several display modes shown in
In a practical example, when sports live broadcasting is received in accordance with a format of 1080i and displayed at a pixel array having an aspect ratio of 4:3, after the entire video in a moving image mode as indicated in
In view of these features, the system of the present embodiment is provided with a changing-over means capable of changing-over a moving image mode utilizing a blanking effect caused by plural-line simultaneous write-in operation and a still image mode for making full use of the vertical resolution by scanning for each one line described above. In addition, the system of the present embodiment is provided with several kinds of display modes as shown in
Such a changing-over of the display functions described above is carried out in such a way that the aforesaid gate line control bus 109 as shown in
This scanning data generator circuit 102 generates a video image scanned for each one line in a still image mode and generates a video image (a white ground portion in an intermediate video image 802 shown in
Since a video image generated by the scanning data generator circuit 102 and a timing signal generated by the scanning timing generator circuit 103 correspond to each other, a timing generated by the scanning timing generator circuit 103 is sometimes changed over when the aforesaid movie-still mode switching or a display mode switching at the pixel array as shown in
The original images 801, 901 shown in
In the case of video data shown in
In the case where the video data shown in
An example of the kind of control information stored in the header area in
Several pieces of control information of various kinds of control information can be set in cooperation to each other, or their set values can be set separately for each piece of control information. When the video data is generated in the format to which its control information is added, a fundamental setting of information parameters concerning a display mode switching at a pixel array can be attained and these parameters can be expanded and set as well at the user's request of the display device or video equipment having this display device mounted without adding any surplus wiring to the display control system.
On the other hand, in the periods for the vertical retrace period and the horizontal retrace period (a black ground data area not utilized in transmittance of control information) shown in
In the present embodiment and the application example in which the system configuration shown in
<Embodiment 2>
The system (for controlling the video display of the display device) described in reference to Embodiment 1 causes each of the pixels arranged in the effective display area of the display device to perform video display and blanking display in one frame period. Therefore, when this system is applied to the liquid crystal display device, a luminance of the displayed image is reduced due to a response characteristic of liquid crystal or an aperture ratio of each of the pixels formed at the liquid crystal display panel. In addition, in the case where a light source (a fluorescent lamp, a light emitting diode and the like) installed at a light source device (also called a backlight, a backlight system or a backlight unit) for allowing light to enter the liquid crystal display panel is also lit continuously in the aforesaid blanking display period, light emitting efficiency of the light source is decreased. Thus, the present embodiment improves lighting control for the backlight in the liquid crystal display device provided with the system described in reference to the embodiment 1 above.
In the present embodiment, the light source device (a backlight hereinafter) is controlled in accordance with the indicated lighting timing 1707 in response to the optical response (e.g., a variation of light transmission) of the liquid crystal layer as above. The backlight is lit at a high-level of the lighting timing 1707 and turned off at a low-level of the lighting timing 1707. The backlight (a light source device) installed at the liquid crystal display device is classified into two classes in terms of its arrangement for the liquid crystal display panel. One of them is the so-called side light-type in which an optical element called a light guide or a light guide plate is disposed oppositely to a major surface of the liquid crystal display panel and a light source such as a cold cathode fluorescent lamp or a light emitting diode and the like is arranged at a side surface of the optical element, where the liquid crystal display panel is irradiated with light from the light source indirectly through the optical element. Many of the side light-type liquid crystal display devices sometimes constitute a so-called front light-type liquid crystal display device in which its light source is not faced to the major surface of the liquid crystal display panel, and such an optical device as above is arranged on the user's side of the liquid crystal display panel. The side light-type backlight is preferable for restricting a thickness of an entire liquid crystal display device and applied to a product installed at a notebook type personal computer, for example.
In addition, the other type of backlight is the so-called direct type backlight in which a light source is faced to a major surface of the liquid crystal display panel, and this is preferable for increasing a luminance of the liquid crystal display device. In the case where an aperture ratio of the pixel formed at the liquid crystal display panel is low, for example, a plurality of light sources (cold cathode fluorescent lamps, for example) are arranged side by side oppositely to the liquid crystal display panel to cause a displayed video image in the liquid crystal display panel to be bright. In the present embodiment, the direct type backlight in which a plurality of fluorescent lamps (cold cathode fluorescent lamps) are faced to the liquid crystal display panel in view of increasing a luminance of the pixel array.
As shown in
In the blinking control of the backlight in accordance with the present embodiment, timing of reduction in luminance of the liquid crystal display panel in a turned-off state of the backlight is allowed to coincide with timing of blanking display (black data scanning), a lamp current generated in the fluorescent lamp at the time of turned-on state of the backlight is made higher than the lamp current at a normal operation (a continuous turned-on operation) so as to increase luminance of the liquid crystal display panel at the time of displaying the video image. It is more preferable that a light emission characteristic of not only a fluorescent lamp but also a light source reaches a desired level of brightness within a short period of time from a starting of supply of electrical current to the light source and light emission ceases rapidly (the so-called duration of persistence is short) after supply of electrical current to the light source is shut off. The electrical current that can be supplied to the fluorescent lamp is determined in its upper limit value in terms of the practical value on the basis of the relation between a value of the aforesaid lamp current and a lifetime of the fluorescent lamp. In addition, light emission response of the fluorescent for supply of electrical current or the duration of persistence each continues for about several ms. Due to this fact, in the present embodiment, a period for increasing a lamp current and turning-on the fluorescent lamp is set to a half of one frame period and the fluorescent lam is turned on once for each frame period.
The direct type backlight in which a plurality of fluorescent lamps are arranged side by side oppositely to the liquid crystal display panel may employ a method in which the backlight is controlled such that the blinking timing is shifted in sequence for each one fluorescent lamp. However, even if a certain fluorescent lamp is turned off, light from another fluorescent lamp adjacent to the former one leaks near the certain fluorescent lamp to increase a luminance of the area in the liquid crystal display panel intended to display dark (this phenomenon is called interference between the fluorescent lamps). Accordingly, even if the blinking timing of each of the fluorescent lamps is shifted in sequence, an effect to such an extent that has been intended cannot be obtained.
In contrast to this, the blinking of a plurality of fluorescent lamps are carried out with the same timing in the present embodiment. One example shown in
In the present embodiment, an operation for turning on the fluorescent lamp in a turning-on period 1708 and turning-off in other periods in accordance with the timing shown in
In accordance with the present embodiment, there is a period in which the fluorescent lamp is being turned off even after the light transmission of the liquid crystal layer upper than the central part of the display screen is increased up to a value corresponding to the video signal (response to the video signal is completed). Additionally, there is a period in which the fluorescent lamp is being turned on even after the light transmission of the upper side liquid crystal layer is decreased by the blanking signal (a response to the blanking signal is completed). On the other hand, a light transmission of the liquid crystal layer lower than the central part of the display picture starts to increase in response to the video signal after the fluorescent lamp is turned on (a response to the video signal is started), and a light transmission of the liquid crystal layer below the former layer shows a value corresponding to the video signal for a while (a response for the video signal is completed) also after the fluorescent lamp is turned on. Accordingly, an overlapped time between a period in which a light transmission of the liquid crystal layer is in an increased state by the video signal (response to the video signal is completed) and a period in which the fluorescent lamp (a light source) is in its turned-on state is decreased as it is moved to a value higher or lower than the value as compared with that at the central part of the aforesaid display picture. In other words, the blanking of the display video is governed by the turning-on timing of the fluorescent lamp as the pixel rows of the display picture go to the upper and the blanking of the display video is governed by the turning-off timing of the fluorescent lamp as the pixel rows of the display screen goes to the lower. In contrast to this, the pixel rows at the central part of the display picture are displayed so that a period in which their associated liquid crystal layers complete a response against the video signal and a turning-on period of the fluorescent lamp are overlapped for a long period of time. Therefore, although the light is emitted in an impulse form from each of the pixels for each frame period in the entire display screen, an integrated value of the optical response (the number of photons emitted from the pixel) becomes maximum at the central part of the display screen and it is gradually decreased as the part of the display screen goes to the upper or lower side.
In this case, in view of the fact that users are ready to turn their eyes upon the center of the display screen, a difference in luminance between a luminance at the central part of the display picture and a luminance generated at each of the upper and lower sides of the display picture is scarcely recognized by a user. In addition, in the case where a video signal and a blanking signal are supplied to each of the pixels constituting the display picture for every frame period in accordance with the present invention, light is emitted from all the pixels in an impulse form. Further, a luminance becomes the highest value at the central part of the display picture where an integrated value of optical response becomes a maximum value, and in turn a luminance is substantially decreased in a symmetrical manner as the position goes from the central part of the display screen to each of an upper side and a lower side of the display picture. Due to these reasons described above, the liquid crystal display device in accordance with the present embodiment provides a user with displaying of a clear, bright video image (in particular, a moving image) having a displaying characteristic as found in a Braun tube where a peak luminance appears at the central part of the picture.
In the present embodiment, a lighting period 1708 of a fluorescent lamp is set up to ½ of a frame period 1701. This causes the possibility that a luminance of the screen is decreased due to the presence of light-ceasing period of the fluorescent lamp. In any of light sources such as a fluorescent lamp or a halogen lamp, a light emitting diode and an electroluminescent element, its luminous efficacy is dependent not only upon an electric current supplied to the light source, but also upon an increased temperature caused by this electric current. Accordingly, an operation for intermittently turning on the light source such as a fluorescent lamp does not necessarily give damage to a luminance of the display screen. The light source is cooled within the aforesaid light-ceasing period in dependence on the temperature dependency of luminance of the light source, so that it is also possible to prevent a luminance of the light source from being decreased due to an increased temperature. However, in view of the aforesaid possibility, an electric current (a lamp current) supplied to the fluorescent lamp in the present embodiment is made larger than a lamp current supplied to continuously turn on the fluorescent lamp (when a still image is displayed, for example). A lamp current value of the fluorescent lamp that is turned on intermittently in accordance with the present embodiment is set to twice the lamp current value that is supplied in the continuous turning-on operation.
In the present embodiment, when a luminance of the light source that is turned on intermittently is sufficiently high, the lighting period 1708 is further shortened, that is, the light source may be turned on in a lighting period 1709 started with the same timing as that of the blanking signal write-in period 1703, for example. Further, in order to accomplish such a turning-on timing as above, the lamp current supplied to the fluorescent lamp during the intermittent operation may be further increased. The turning-on period 1709 shown in
As described above, although the liquid crystal display device having the direct type light source (the backlight) mounted thereon is used in the present embodiment, the intermittent turning-on of the light source described above can be applied to the liquid crystal display device having the side light type light source device mounted thereon.
Further,
These switchable backlight control in the present embodiment is properly performed by a method in which the parameters as shown in
The scanning timing generator circuit 103 shown in
A liquid crystal display device mounted in a notebook type personal computer is provided with a side light type backlight so as to make its entire thickness thin. In such a liquid crystal display device as above, since its number of lights to be controlled or its turning-on manner is limited, a necessity for transmitting control information to the backlight drive circuit as described above is low. However, in the case where a moving image to be distributed through the Internet system or the like is watched by the notebook type personal computer, an significant advantage that blinks the lamp (a fluorescent lamp) with the timing shown in
Controlling over a turning-on of the backlight in reference to a blanking display period set for each frame period or an effective display area of the pixel array (display picture) in accordance with the present embodiment described above improves a moving image displaying characteristic in the display device and further luminous efficacy of the light source device installed in the display device.
<Embodiment 3>
As described in the embodiment 1, when the pixel array is operated by the scanning process, the so-called 2-line simultaneous write-in (2-line skip scanning) in which a plurality of pixel rows (forming lines for each gate line or scanning line) arranged side by side along a vertical direction of the pixel array are selected for each two lines, a voltage signal is applied to these pixel rows and the pixel rows having the voltage signal applied thereto are selected in skip for each 2 lines in response to a pulse of the scanning timing signal, a video image having only a half vertical resolution of the original image inputted to the display device is inevitably reproduced at the pixel array in some cases.
As is apparent from
A data transmittance band in a drain drive circuit (a drain driver IC) available at present is about 50 MHz. As shown in
If the pixel array of XGA is driven by use of this drain driver IC (Integrated Circuit), at least 60×768×1024≈47 MHz is needed in the case where the video data is supplied with a frequency of 60 Hz, and there is no margin in this driver data transferring band (also including a case in which color video data is supplied on three types of display color basis). To solve this problem, some products available at present include a display device which is provided with data buses for two pixels (a total of six buses by display color in a color video data) and which has a half rate of a transfer rate of each of the data buses. In this display device, video data of each of the display colors arranged in a horizontal direction are assigned alternatively to any one of the data buses for two pixels through two-pixel parallel interface described above in reference to
However, in contrast to the display device for use in a monitor of which specification is defined by such standards as described above, a display device for displaying television broadcasting is not relatively put restrictions on the method for transferring the video data even if the display device displays digital broadcasting or is provided with as system applicable to NTSC (National Television System Committee). Accordingly, a signal processing circuit specific to each of the manufacturers is mounted on a display device (a liquid crystal display device and the like) for a television receiver. In view of the foregoing, the present inventors have studied a method for making full use of the data transfer band of the drain driver IC used.
The drain driver IC having the data transfer buses for two pixels is mounted on the display device of XGA class and the data is transferred to this drain driver IC with a frequency of 47 MHz as described above, with the result that scanning for two pictures with a frequency of 60 Hz, in other words, application of a signal voltage to all the pixels in the pixel array can be carried out in a frame period of 16.7 ms. In the present embodiment, such a driver IC (with two-pixel parallel interface) is used, of the scanning periods for two pictures assured in the one frame period, one scanning period for one picture is assigned to vide display and the scanning period for the other picture is assigned to blanking display, so that moving image displaying performance without losing a vertical resolution of the video data is improved.
Combining the backlight system described in the embodiment 1 with the liquid crystal display device in accordance with the present embodiment causes the moving image to be displayed more clearly and also causes luminance efficiency of the backlight to be improved.
Unlike the embodiment 1, in the present embodiment, the video data or blanking data is not written simultaneously in a plurality of lines, so that it is not necessary to perform a partial deletion of video information of the original image and a vertical resolution of the video image to be displayed is not decreased. With such an arrangement, displayed image quality is further improved.
The pixel array in the display device in the application example combining the 2-line simultaneous write-in (2-line skip scanning) of the embodiment 1 with the present embodiment can be scanned four times in one frame period, so that its moving image display performance is further improved. When the still image is displayed in this application example, details of this image are reproduced at the display screen (a pixel array) with a high vertical resolution. On the other hand, when a fast moving image is displayed in this application example, applying of the aforesaid liquid-crystal-response-speed-up filter processing or the like causes a resolution (a time margin) to be assured in a time direction and a displaying quality to be improved. Although a trial for speeding up the optical response of the liquid crystal has been promoted through improvement of liquid crystal material, a response speed of the liquid crystal material itself has been up to a range from several ms to several tens ms. In addition, even if the response speed has been improved in this way, a holding characteristic in which the liquid crystal layer holds a video signal in a frame period inevitably tends to deteriorate. Since the holding characteristic of the liquid crystal layer determines a frequency in occurrence of flicker at a screen of the liquid crystal display device, liquid crystal material showing a fast response speed has not been accepted in the liquid crystal display device used in a personal computer or the like in particular.
In contrast to this, if scanning for four pictures is carried out for each frame period as described in the present application example, the four pictures are divided into the initial two pictures for a video write-in scanning and the subsequent two pictures for a blanking scanning, and additionally, the initial one picture for the video write-in operation is assigned to scanning in which the video signal is subjected to a fast-responding filtering process and the subsequent one picture is returned to scanning performed by the normal video signal, whereby an impulse type drive of the liquid crystal display device in which an apparent response is accelerated can be realized. Since a potential of each of the pixels after the blanking scanning in the previous one frame period is always in a black display state in the present application example, the potential of the pixel in the subsequent one frame period is increased from the black display state to a value corresponding to the video signal. Accordingly, the fast-responding filter processes a video signal to be supplied to the pixel in the subsequent one frame period with a pixel potential in a black display state set as an initial value and the thus processed video signal is applied to the pixel. Therefore, a video signal production through the fast-responding filter can be carried out simply and positively in view of performing a fast increasing of the potential of the pixel to a desired level, so that its circuit configuration is also suppressed to a relatively small size. Further, as described above in reference to
In the liquid crystal fast-responding period 2202, a filter coefficient of the fast-responding filter is set in such a way that a video signal applied to the pixel becomes higher than a video signal applied to the pixel in the settling period 2203 so as to cause the pixel to be always responded from the black displaying potential to a desired potential as described above, and an electric field intensity applied to the liquid crystal is made higher than that in the settling period 2203. The so-called pseudo video signal having a voltage value of the video signal set to be higher than a predetermined value with the fast-responding filter in this way is applied to the pixel electrode, thereby the optical response waveform 2210 in the liquid crystal fast-responding period 2202 reaches rapidly to a predetermined light transmission. The time in which a light transmission of the liquid crystal layer reaches from its minimum value to a predetermined value (the maximum value in the case of white display) shown through a drive of the liquid crystal display device is shortened down to 4.2 ms.
The optical response of the liquid crystal layer shows a tendency in which it is made fast as an electric field intensity applied to the liquid crystal layer is increased, and is made slow as an electric field intensity is decreased. An orientation of liquid crystal molecule (determining a light transmission of the liquid crystal layer) is varied forcedly from an initial oriented state (an oriented state under a substantially no electric field) or its approximate oriented state into another orientated state due to an increased electric field intensity artificially in a sense and in turn it is naturally (without being forced) returned to an initial oriented state or its approximate oriented state in accordance with an amount of reduction of the electric field intensity. In the case where the liquid crystal display device is driven in the normally black mode in the present embodiment, a potential of the pixel electrode where the video signal corresponding to a certain frame period is written is set to a value corresponding to the black display (a minimum voltage value capable of being applied to the pixel electrode) at the time of end of another frame period preceding to the one frame period, so that the potential of the pixel electrode is increased by application of the video signal. In other words, a light transmission in the liquid crystal layer is increased from the minimum value at the time of the end of the above another frame period to a predetermined value corresponding to the video signal supplied in the above certain frame period. Therefore, the light transmission in the liquid crystal layer is changed rapidly and its speed is further increased through the processing of the video signal performed by the aforesaid fast-responding filter. In contrast to this, at a stage changing from the settling period 2203 to the blanking period 2204, a potential of the pixel electrode must be changed from a value corresponding to the video signal to its minimum value or its approximate value (this requirement is not applied to a pixel electrode to which the video signal of black display is supplied). In the liquid crystal display device with the normally black mode, an electric field generated at the liquid crystal layer in response to the video signal becomes a more intensified one than that corresponding to the blanking signal as long as a video signal increases a light transmission of the liquid crystal layer more than that of the blanking signal. Therefore, at a transit stage from the settling period 2203 to the blanking period 2204, an optical response at the liquid crystal layer becomes also slow. As described above, when the electrical field generated at the liquid crystal layer is decreased, its light transmission is not forced by a variation in the electrical field, so that the optical response at the liquid crystal layer is not accelerated to the extent that has been expected even if the fast-responding filter is used. It is effective to apply the blanking signal at least twice to the blanking period 2204 as described in the present application example in view of accommodating for deterioration in optical response in such a liquid crystal layer.
In the liquid crystal display device of normally white mode represented by the liquid crystal display device using TN (Twisted Nematic) liquid crystal, its light transmission is decreased as an electrical field intensity applied to the liquid crystal layer is increased. In other words, in the case of the liquid crystal display device of normally white mode, a display color (luminance) of the pixel responds fast toward a black level and responds slow toward a white level. Consequently, a relation between a speed of optical response of the liquid crystal layer at a stage shifting from one of the pair of aforesaid frame periods to the other and a speed of optical response at the liquid crystal layer at a stage shifting from the aforesaid settling period 2203 to the blanking period 2204 is inversed. That is, at the stage shifting from the settling period 2203 to the blanking period 2204, a potential of the pixel electrode (except an electrode to which the video signal of displaying black is supplied) is increased from a value corresponding to the video signal to its maximum value or its approximate value, so that a light transmission at the liquid crystal layer is rapidly changed and its speed is further increased through processing of the blanking signal caused by the aforesaid fast-responding filter.
In the present application example, since a transferring speed of video data to the drain driver IC through the two-pixel parallel interface process is made twice, the write-in period 2205 of the voltage signal (either the video signal or the blank signal) to the pixel rows selected for each line in accordance with the transferring speed is also shortened. In the present application example, a potential of each of the drain lines for supplying a voltage signal to each of the pixels constituting the pixel rows is changed such that a polarity of the potential relative to a common level (a common potential) is inversed for each ¼ period of the frame period 2201 as shown by a drain line drive waveform 2207. With such an arrangement, a polarity inversion period of the signal voltage at the drain line is completed for each frame period 2201 at each of the video signal write-in period (including the fast-responding period 2202 and the settling period 2203) and the blanking period 2204. In other words, the polarity of a signal voltage at the drain line with respect to the common level is inverted a plurality of times for each frame period. With such an arrangement, even if the aforesaid write-in period 2205 is shortened, the signal voltage is applied efficiently to each of the pixel electrodes associated with the lines selected at this period (a data write-in rate for each of the pixels is improved), with the result that each of the pixel electrodes is set positively to the desired potential.
In the case where the still image is displayed by the operation of the display device in accordance with the present application example, there is the possibility that a vertical resolution of the picture is decreased as described above in reference to the embodiment 1. To eliminate the possibility, the display device is preferably provided with means for recognizing whether the video data is the still image or the moving image and a switching means for a scanning process for scanning one line (one pixel row) in the pixel array of the display device for each one line of the video data when the still image is recognized and for scanning a pixel array in accordance with the present application example when the moving image is recognized. In one example of the display device, in the system block diagram for the display device shown in
One example of this judging operation performed by the display device will be described as follows in reference to
As already described in the embodiment 1 in reference to
The scanning timing generator circuit 103 receiving the video data attached with the control information associated with the moving image converts either the video data or the blanking data into the voltage signal applied to each of the drain lines 203 at a high-speed by the drain line drived circuit 105, and generates timing suitable for applying in sequence, for each two lines, a gate pulse for selecting the pixel rows in the pixel array by the gate line drive circuit 104 for each two lines of the gate lines 201. The voltage signal generated by the drain line drive circuit 105 in this way is applied to each of the pixels in the pixel array in response to the gate pulse generated by the gate line drive circuit 104 and a light transmission (a luminance of each of the pixels) in the liquid crystal layer is raised at a high-speed as shown in
On the other hand, the scanning timing generator circuit 103 receiving the video data attached with the control information associated with a still image generates the video data suitable for supplying the pixel information for each one line of the original image for each one line of the pixel array and generates a gate pulse shown in
Further, when a display device user requests a display video image keeping the vertical resolution of an original image even if either the display device or its control system judges the original image as the moving image, it is also possible to generate the moving image at the display device by the same operation as that for the aforesaid still image through the control bus 109 shown in
Further, when a control for the backlight (light source device) described in the embodiment 2 is combined with a drive of the display device in accordance with the present embodiment or its application example, the moving image displayed by the present embodiment or its application example becomes clearer due to a blanking effect caused by blinking of the backlight. In addition, since the luminous efficacy of the light source device is also improved, displayed video quality of the display device (a liquid crystal display device) is also improved.
<Embodiment 4>
As already been described in reference to
The gate line drive circuit 104 sets an address of line starting a vertical scanning and an address of line finishing a vertical scanning of a plurality of gate lines arranged side by side in a pixel array of the liquid crystal display panel 106 (each of them is discriminated by addresses of G1 to Gn shown in
An advantage of the display device (the liquid crystal display device in the present embodiment) provided with the gate line drive circuit 104 having such a scanning line selecting function becomes apparent when a video of format having an aspect ratio different from that of the pixel array (refer to
In contrast to this, if the display device is provided with the gate line drive circuit having a scanning line selecting function described in reference to the present embodiment, the blanking display of the pixel arranged at the area other than the effective display area can be performed separately from the data write-in operation (applying of either a video signal or a blank signal to the pixel electrode) to the pixel arranged in the effective display area. Due to this fact, a time assigned for the scanning of area other than the effective display area for every frame period can be used for a scanning of the effective display area. Accordingly, as described in reference to the embodiment 1, either a displaying operation for selecting the gate line in the pixel array (in the effective display area) for every plurality of lines and performing a simultaneous write-in scanning of data to the pixels corresponding to these lines while skipping for every plurality of lines, or a fast data-transfer operation for shortening a selection time for each of the lines (a gate pulse width) in the aforesaid pixel array (in the effective display area) as described in reference to the embodiment 3 and applying a signal voltage to the pixel electrode corresponding to each of the lines in the selecting period by a plurality of times for every frame period can be carried out with a tolerance for the data-transfer area of the drain line drive circuit. Further, it is not necessary to transfer the aforesaid dummy video from the display control circuit to the drain line drive circuit. That is, the dummy video data may be generated at a location other than the display control circuit (in the drain line drive circuit, for example). In the case of the liquid crystal display device of normally black mode or the electroluminescent type display device, a scanning of an area other than the effective display area is stopped and a luminance of pixel in this area may be kept at a black display state (a light transmission of the liquid crystal layer in this area is made minimum in the case of the liquid crystal display device).
Next, in reference to a timing chart for a gate selection pulse in a pixel array shown in
In the timing chart shown in
In the timing chart shown in
All the pixels in the invalid area corresponding to the aforesaid (n−k) line may be displayed uniformly in black, for example, or in color not hindering a user's sight of view when the video displayed in the effective display area is seen by a user. In the present embodiment, the lines ranging from address G1 to address Gi−1 and the lines ranging from address Gi+k+1 to address Gn are selected simultaneously in the retrace period 2402, and the blanking signal displaying the pixel in black is written into all the pixels corresponding to these (n−k) lines. After the blanking signal is written into the pixels in the invalid area, the video signal and the blanking signal are written in sequence into each of the pixels present in the effective display area in a display period 2403.
The video displaying operation in accordance with the present embodiment and its advantage will be described more specifically in reference to an example in which the video of 1080i is displayed at the pixel array of XGA class. In this example, as shown in
In the present embodiment, videos corresponding to one field of interlace process formatted in 1080i (including data corresponding to 1080 lines of gate lines of 540 odd-numbered lines or 540 even-numbered lines) in one frame period in which an entire area of such pixel array as above is once scanned for every one line are displayed. In the present embodiment, 192 lines in the invalid area are scanned in a retrace period 2402 separate from 576 lines in the effective display area, so that the gate selection pulses generated by 768 times in the display period 2403 can be utilized for the data writing-in operation for 576 lines in the effective display area.
As described above, since the display period 2403 is divided into the video writing-in period 2404 and the blanking data writing-in period 2405, the video signal writing-in operation for 576 lines in the former case and the blanking signal writing-in operation for 576 lines in the latter can be carried out with gate selection pulses of 384 times, respectively. Accordingly, 384 lines out of 576 lines in the effective display area for use in displaying video formatted in 1080i at the pixel array of XGA class is scanned under 2-line simultaneous selection mode with 192 times of gate selection pulses and the remaining 192 lines are scanned under 1-line selection mode with 192 times of gate selection pulses, respectively, whereby the video signal is written into all the pixels corresponding to 576 lines (the video writing-in period 2404) and the blanking signal is written (the blanking data write-in period 2405). As one practical example of such a scanning method as described above, a scanning by the 2-line simultaneous selection mode for every gate selection pulse and a scanning by one-line selection mode are carried out alternately. With such an operation as above, data corresponding to 540 lines of video inputted to the display device for every field period are written into the effective display area of the pixel array with gate selection pulses of 384 times in the video write-in period 2404. That is, data of 384 lines out of 540 lines (540 of the vertical resolution) transmitted to the display device for every field period are reproduced at the picture in a video write-in period 2404, the picture having the video reproduced in its subsequent blanking data write-in period 2405 is switched to the blanking display to cause the video reproduced at the picture to be seen in an impulse manner.
In place of the aforesaid scanning method, it is also possible to perform a writing-in operation for writing the video data of 1080i corresponding to one field period and the blanking data in sequence for every one line of 576 gate lines arranged in the effective display area of the pixel array of XGA class and to display the video in an impulse manner. In this case, since 576×2=1152 lines are scanned in one field period, it is necessary to output the voltage signal according to the times of scanning to the drain line drive circuit. That is, the video data (also including the blanking data) for outputting such a voltage signal as above at the drain line drive circuit must be transferred from the display control circuit (the timing converter). For example, for the video corresponding to one field period to be inputted to the display device at a frequency of 60 Hz, the video data displayed at the pixel array and the blanking data are transferred to the drain line drive circuit at a frequency of about 60×1024×1052=65 MHz. Accordingly, the drain line drive circuit having the data transfer band of 50 MHz usually installed at the pixel array of XGA class is replaced with the drain line drive circuit having a data transfer band of 80 MHz or more for the pixel array of SXGA class.
In this way, when the data transfer band in the drain line drive circuit is set to be sufficiently higher than the data transfer band corresponding to a resolution (the number of pixels) of the pixel array of XGA class having the drain line drive circuit installed therein, 576 gate lines arranged in the effective display area of the pixel array can be scanned by four times, for example, through the plural-line simultaneous write-in operation and the plural-line skip scanning operation in accordance with the embodiment 3 for every field period of 1080i data. Due to this fact, a blur of contour of a moving item displayed at a picture is restricted by displaying the video data corresponding to one field period of data of 1080i through front half twice scanning of four times scanning for the effective display area performed by the plural-line simultaneous write-in operation and the plural-line skip scanning, and by displaying the blanking data at the pixel array through rear half twice scanning, respectively. In addition, the video showing many actions (many number of pixels showing some luminance changed for every frame period) can be displayed clearly by performing an initial scanning to write-in the video data into the effective display area for every one field period of the video data when the display device has a pixel array driven under a normally black mode, and by filtering a voltage signal supplied from the drain line drive circuit to the pixel array through an initial scanning to write-in the blanking data into the effective display area when the display device has a pixel array driven under a normally white mode.
In addition, in the liquid crystal display device in accordance with the present embodiment, the lamps corresponding to the pixel array acting as the invalid display area are turned off over the frame period in accordance with the embodiment 2, or the turning-on of the lamps constituting the light source device (the backlight) is controlled for every frame period, whereby the quality of the moving image can be improved more, a luminous efficacy of the light source device can be improved and a consumption power can be restricted.
Referring to
When the scanning timing generator circuit 103 receives the video data attached with such control information as above, it generates a timing for controlling each of the drive circuits also including a gate drive circuit 104, a drain drive circuit 105 and a backlight drive circuit 108 in a certain liquid crystal display device on the basis of the control information. The display device constructed as above receives an instruction for switching the display mode in response to visual contents desired by a user, at the scanning data generator circuit 102 through the control bus 109, and properly changes the video display corresponding to the instruction to any one of impulse type drive (a pseudo impulse mode in accordance with the present invention) and a hold-type drive to thereby improve its displayed video quality in response to the video.
<Embodiment 5>
In order to perform writing-in of video into the pixel array and writing-in of blanking data for every frame period (for every field period in the interlace mode) through scanning for every one line in the pixel array and to attain an impulse-type luminous characteristic, it is required to arrange the drain line drive circuit having a scanning band at least twice that required in the drain line drive circuit used in the conventional hold-type display of the still image. In order to generate an impulse type video of one frame at the display device having a pixel array of XGA class, for example, 1536 lines exceeding the pixel array (a vertical resolution of 1200) of UXGA class in one frame period are scanned because 768 lines are scanned in ½ of the frame period. Accordingly, in order to generate an impulse video by writing the video signal and the blanking signal into the pixel array in response to such a scanning as above, the data transferring band capable of receiving data for the impulse video and processing it (corresponding to one more than the data transferring band of the drain line drive circuit for UXGA class) is required in the drain line drive circuit.
As already been described in the embodiment 3, the drain driver IC (the drain line drive circuit) available at present is operated such that data is transferred from the display control circuit to the drain line drive circuit, if the data transfer band is slightly larger than a band required for displaying the video for every frame period through scanning for every one line in the pixel array. However, an operation margin of the drain line drive circuit is quite low. In the present embodiment, a transfer speed of the video data (also including the blanking data) from the display control circuit to the drain line drive circuit is increased by two times without changing a data bus width in the drain line drive circuit (for example, without replacing one-pixel single interface mode with two-pixel parallel interface mode), and without increasing its transfer clock frequency, the video signal and the blanking signal are written into the pixel array in sequence for every frame period by performing the scanning for every one line of the pixel array, and then the video is impulse displayed at the pixel array. In order to accelerate the video data transfer without changing either the data bus width or the transfer clock frequency of the drain line drive circuit, the display device in accordance with the present embodiment employs either a new drain line drive circuit or a new data transfer method.
A configuration of a logic portion included in the drain line drive circuit (a drain driver IC) assembled into the display device in accordance with the present embodiment is shown in
In
Although not shown in
The gray scale voltage is a signal voltage for determining a brightness of a pixel to which the gray scale voltage is applied (including an electrode to which the gray scale voltage is applied) and this signal voltage is applied in sequence to a plurality of pixels (pixel columns) arranged along the drain line (along the vertical direction of the pixel array) through the drain lines installed at the pixel array. A timing at which the gray scale voltage is applied to each of the pixels constituting the pixel columns is controlled by the aforesaid gate selection pulse, and in the case of a scanning performed through the aforesaid plural-line simultaneous selection, the gray scale voltage is applied to a plurality of pixels arranged continuously from a certain drain line at a pixel columns corresponding to this drain line is applied in response to a certain one gate selection pulse (that is, the plurality of pixels are displayed by approximate same gray scale). In turn, it is frequently found that the gray scales of each of the pixels constituting the pixel column are different from each other. Due to this fact, the gray scale voltage outputted at the drain line for every horizontal scanning period of the pixel array is also assumed as a voltage signal indicating a variation illustrated as the aforesaid drain waveform.
The drain driver IC is also provided with a data latch circuit having a plurality of synchronous delay elements 2506 connected in series with respect to each of the odd-numbered pixel data and the even-numbered pixel data inputted to the drain driver IC; a processing circuit 2507 receiving an output from each of the data latch circuits; and a data bus 2508 for sending a post-processing signal outputted from the processing circuit 2507 to the data latch circuit 2503. Although these circuits complement a half of the video (video data) deleted at a stage where it is transferred to the drain driver IC, its details will be described later.
A plurality of latch circuits (data latch circuits) 2503 arranged at the drain driver IC is classified into the first group connected to the data bus 2501 for the odd-numbered pixels, the second group connected to the data bus 2502 for the even-numbered pixels, and the third group connected to the output bus 2508 of the processing circuit 2507. The respective latch circuits belonging to the first group and the respective latch circuits belonging to the second group are arranged alternately with one of the latch circuits belonging to the third group being held between each of the respective latch circuits belonging to the first group and each of the respective latch circuits belonging to the second group. Each of the latch circuits belonging to these latch circuit groups is selected by an address circuit (not shown) in response to an address given for every latch circuit.
The video data transferred through the data bus 2501 for the odd-numbered pixels is stored in each of the latch circuits by selecting the plurality of latch circuits belonging to the first group in sequence through the aforesaid address circuit. The video data transferred through the data bus 2502 for the even-numbered pixels is stored in each of the latch circuits by selecting the plurality of latch circuits belonging to the first group in sequence through the aforesaid address circuit.
When an output instruction for a gray scale voltage is outputted at this stage from the data latch circuit 2503 as described above, a gray scale voltage to be applied to a half number of a plurality of drain lines arranged in a horizontal direction of the pixel array is determined. Referring to
This processing is carried out by another circuit connected in parallel with one group of the aforesaid latch circuits 2503 to each of the data bus 2501 for the odd-numbered pixels and the data bus 2502 for the even-numbered pixels and by the plurality of latch circuits belonging to the aforesaid third group receiving an output of this another circuit. The drain driver IC formed in accordance with the present embodiment shown in
Outputs of each of the plurality of delay elements 2506 to which odd-numbered pixel data is inputted and the plurality of delay elements 2506 to which even-numbered pixel data is inputted are connected to the processing circuit 2507. The processing circuit 2507 has an amplifier for every output of the delay element 2506, for example, and an adder for adding sequentially the outputs (that is, pixel data) of the delay elements 2506 amplified by this amplifier. In this way, the processing circuit 2507 constitutes an FIR filter (a digital filter also called Finite Impulse Response Filter or Non Recursive Filter) together with each of the one group of delay elements 2506 connected to the data bus 2501 for odd-numbered pixels and the one group of delay elements 2506 connected to the data bus 2502 for even-numbered pixels. The processing circuit 2507 transfers a result of adding the pixel data (inputted to the delay elements 2506) weighted by different factors, respectively, through the output bus 2508 and stores it in the latch circuit 2503 belonging to the aforesaid third group. Accordingly, a gray scale voltage corresponding to an output of the processing circuit 2507 is applied to half number of drain lines not applied with a gray scale voltage even by either latch circuits 2503 belonging to the aforesaid first group or the aforesaid second group. In other words, the half video data deleted in a horizontal direction are complemented by the output of the processing circuit 2507. The pixel columns to which a gray scale voltage based on the video data is not applied are driven by a gray scale voltage based on the data generated by such a filtering process as described above, whereby a moving image having a sufficient image quality is displayed only if the gray scale voltage based on the video data is applied to certain pixel columns only at the display picture.
In addition, “−z” denoted at the delay element 2506 shows that the delay element 2506 subjects a digital data (expressed as a series fn) inputted to this delay element to z-transform and outputs a sum of a power series of z−n with a general term being fnz−n (z is a complex variable).
As described above, two times scaling has been applied along a horizontal scanning line (a horizontal direction) of the video data and an amount of transfer for the drain driver IC has been decreased in the present embodiment. However, if N-times scaling (N is an optional natural number larger than 2) is applied to the video data, an amount of transfer for the drain driver IC also becomes 1/N and the vertical scanning can be performed by N times for every frame period. In the case that N times scaling is applied to the video data, a bus for transferring the video data to the drain driver IC is set to have a width corresponding to N pixels. For example, a new pixel data bus is provided for the present embodiment in which a bus wiring having a width corresponding to two pixels is provided by the data bus 2501 for odd-numbered pixels and the data bus 2502 for even-numbered pixels. In turn, in the case that a still image is displayed at the display device, data arranged in the horizontal direction is transferred in full to the drain driver IC for every horizontal scanning period to be written into the pixel rows for every gate line in the pixel array, respectively. Therefore, because it is also applicable to hold the gray scale of each of the pixels over a frame period, it is not necessary to make a scaling of the video data in the horizontal direction as disclosed in the present embodiment. Accordingly, it is to be noted that the video data transfer bus for the drain driver IC in the display device is arranged with a width corresponding to N pixels being set and its wiring width is changed over in response to the still image display, the moving image display, and a scaling magnification of the moving image.
In turn, the blanking data generated at the right half portion of the video data 2802 in
As described above, in the present embodiment, a video display is carried out with video data having a reduced amount of data at a front half segment of the frame period and subsequently a blanking display is carried out with blanking data (a masking data) generated by the drain driver IC for every frame period. A video 2803 shown in
The drain driver IC in accordance with the present application example is characterized in that it is provided with a bus division multiplexer 2701. Under an operation mode for transferring data in one pixel unit with a 8-bit bus width (hereinafter 8-bit bus mode), the bus division multiplexer 2701 transfers data inputted to the data bus 2501 for odd-numbered pixels from the data bus 2501 for odd-numbered pixels to the latch circuit 2503 for the odd-numbered pixels and transfers data inputted to the data bus 2502 for even-numbered pixels from the data bus 2501 for even-numbered pixels to the latch circuit 2503 for the even-numbered pixels, respectively. In
On the contrary, under a mode in which the 8-bit bus width is assigned every 4 bits to each of the two pixel units (hereinafter called a half bus mode), the data bus 2501 for the odd-numbered pixels or the data bus 2502 for the even-numbered pixels are divided into two segments, and the data inputted from any one of the data bus 2501 for the odd-numbered pixels and the data bus 2502 for the even-numbered pixels to it are transferred to a pair of latch circuits 2503 connected in parallel to the rear stage (usually, one of them is used as the latch circuit for the odd-numbered pixels and the other of them is used as the latch circuit for the even-numbered pixels). Under the aforesaid 8-bit bus mode, the bus division multiplexers 2701 are selected one by one in sequence using the bus switch and the pixel data are transferred to the two latch circuits. However, under the half bus mode, the bus dividing multiplxers 2701 are selected in sequence every one pair using the bus switch and the pixel data is transferred to four latch circuits. The data (pixel data) to be sent to each of the pixels illustrated under the aforesaid 8-bit bus mode is transferred to the latch circuit 2503 as follows under the half bus mode. At first, the bus switch selects a pair of bus division multiplexers α, β. This bus switch transfers a pair of odd-numbered pixel data corresponding to addresses PIX(1,y), PIX(3,y) to the latch circuits a, b through the bus division multiplexer α and at the same time this bus switch transfers a pair of even-numbered pixel data corresponding to addresses PIX(2,y), PIX(4,y) to the latch circuits c, d through the bus division multiplexer β. Then, the bus switch selects a next pair of bus division multiplexers γ, δ. This bus switch transfers a pair of odd-numbered pixel data corresponding to addresses PIX(5,y), PIX(7,y) to the latch circuits e, f through the bus division multiplexer γ, and concurrently this bus switch transfers a pair of even-numbered pixel data corresponding to addresses PIX(6,y), PIX(8,y) to the latch circuits g, h through the bus division multiplexer δ.
As described above, in the present application example in which the bus width corresponding to one pixel is assigned for a plurality of pixels N (N=2 in the aforesaid example), one multiplexer is assigned for every number of N of the latch circuits connected to either the data bus 2501 for odd-numbered pixels or the data bus 2502 for even-numbered pixels, a transfer amount of the pixel data sent to the latch circuit is set to 1/N and a transfer speed is accelerated by N times through this multiplexer. As described above, any one of the odd-numbered pixel data corresponding to N pixels or the even-numbered pixel data is connected through one multiplexer 2710 to the number of N of latch circuits 2503 connected to the multiplexer 2701. That is, as described above, the latch circuit b for storing even-numbered pixel data corresponding to the address PIX(2,y) under the 8-bit bus mode stores the odd-numbered pixel data corresponding to the address PIX(3,y) under the half bus mode, while the latch circuit c for storing odd-numbered pixel data corresponding to the address PIX(3,y) under the 8-bit bus mode stores the even-numbered pixel data corresponding to the address PIX(2,y) under the half bus mode, so that a gray scale voltage corresponding to another drain line is outputted at the drain line corresponding to a certain latch circuit. Due to this fact, in the present application example, there is provided an address selection circuit (not shown) for replacing the address of the latch circuit in response to a driving operation of the bus switch. In accordance with the aforesaid example, when the bus switch controls the multiplexer under the half bus mode, the address selection circuit produces an instruction recognizing the latch circuit b as the latch circuit c in synchronous with an instruction outputted by the bus switch so that the gray scale voltage corresponding to the data stored in the latch circuit b is outputted at the drain line corresponding to the latch circuit c. The address selection circuit also produces an instruction recognizing the latch circuit c as the latch circuit b so that the gray scale voltage corresponding to the data stored in the latch circuit c is outputted at the drain line corresponding to the latch circuit b.
In the present application example, the data bus for the even-numbered pixels is divided into 2 segments for the transfer of data corresponding to two pixels, each of the divided buses is connected to a pair of latch circuits adjacent to each other, the data bus for the odd-numbered pixels is divided into 2 segments for the transfer of data corresponding to two pixels, each of the divided buses is connected to a next pair of latch circuits adjacent to each other adjoining the former pair of latch circuits, whereby the odd-numbered pixel data corresponding to the two pixels and the even-numbered pixel data corresponding to the two pixels are stored concurrently in these four latch circuits during a time in which each of the odd-numbered pixel data and the even-numbered pixel data is stored in sequence in a pair of latch circuits and a pair of aforesaid next latch circuits for every one pixel. With such an operation as above, since the pixel data is transferred to the drain driver IC at a speed two times a transfer rate in the so-called hold display of the still image normally found, it is possible to write the video into the pixel array in a period of ½ of the frame period of the original image. Accordingly, remaining period of ½ in the frame period is assigned for a blanking period and the video data transferred in the previous ½ period is masked by the mask logic 2504, whereby the blanking data (black display data, for example) is written into the pixel array to enable the video to be displayed in a conventional driver data transfer rate.
In an example in which the video of XGA class having a smaller aspect ratio in a horizontal direction than that of the pixel array is displayed by the display device provided with the pixel array 106 of WXGA class having the aforesaid functions as shown in
In the present embodiment, some parameters shown in
“FULL” in the driver transfer bus mode is a data transfer format as illustrated in the aforesaid 8-bit bus mode under which its bus width is used for transferring data corresponding to one pixel.
If the gate driver IC described in reference to the embodiment 4 is mounted on the gate line drive circuit 104 of the display device shown in FIG. 29, it is possible to perform a scanning operation for four pictures in one frame period. In the case of such a display device constructed as above, a high quality moving image can be displayed through a filtering process or the like where an optical response of the liquid crystal is made fast and various kinds of other displaying functions can also be realized. It is needless to say that a mere combination of at least one function described in the embodiment 1 and the embodiment 2 with the display device in accordance with the present embodiment causes the display device to exhibit a synergy effect along with the displaying function in accordance with the present embodiment.
Further, in the case where an active element arranged for every pixel in the pixel array is formed by a field effect transistor (represented by a thin film transistor TFT) or a diode and the like in which a semiconductor layer of polycrystalline silicon (p-Si) or pseudo-single-crystal silicon is used for a channel (an area where a carrier motion between a drain line and a pixel electrode is controlled in response to the aforesaid line selection), the drain line drive circuit in accordance with the present embodiment can be formed in a substrate (an insulating substrate such as a glass substrate or a plastic substrate and the like or a semi-insulating substrate such as silicon and the like) where the pixel array is formed. This fact is not restricted to the present embodiment, and the gate line drive circuit described in accordance with the embodiment 4 can also be formed in the substrate similarly where the pixel array is formed. A substrate (hereinafter called a pixel array substrate) in which an active element having a channel formed by any one of polycrystalline semiconductor layer or single-crystal semiconductor layer or a semiconductor layer having their intermediate crystalline structure (called a pseudo single-crystal) is arranged together with the pixel array can be widely utilized in a display device in which not only a liquid crystal but also electroluminescent material or compound semiconductor material having a hetero-junction is applied as media for displaying. In the case of both a liquid crystal display device and a display device provided with light-emitting diode made of an organic material or a non-organic material, it becomes possible to restrict a circumferential edge size (called a perimeter) of the pixel array and to display the moving image with a high definition and various functions by employing the pixel array substrate as above and forming the driving circuit on the pixel array substrate (composed of glass, plastics, semiconductor or the like). When all the functions or structures described not only in the present embodiment but also in the aforesaid embodiments 1, 3 and 4 are applied in the display device for pseudo-hold displaying of an image by the pixels formed by the light emitting diodes (element emitting light through carrier injection into an electroluminescent material or a compound semiconductor material or the like), luminance of the pixel element during displaying in black also becomes quite low because the pixel element itself has a function of the light source (due to no requirement of backlight). Accordingly, if the present invention is applied to the display device in which the pixel elements are constituted by the light-emitting diodes, it becomes possible to attain a blanking effect and a clear (having a high contrast ratio) moving image display through this blanking effect.
<Embodiment 6>
In the aforesaid embodiment, there has been described the video display in which the pixel rows of N lines (N is a natural number not less than 2) are selected simultaneously, scanning for applying a voltage signal to these pixel rows is carried out while skip-scanning every adjacent groups of N lines. In the present embodiment, in N line groups selected simultaneously (hereinafter called the first line group), a voltage signal applied to N line group to be selected subsequently (hereinafter called the second line group) is partially taken into certain lines of the second N line groups, and the so-called gray scale gradation displayed between the line groups is generated. This operation is carried out such that at least one-line gate selection time of the first line groups on the side of the second line groups is delayed relative to that of another line (set in such a way that a voltage signal corresponding to the first line groups is prevalently applied) or this gate line selection period is extended compared with that of another line.
The half of one frame period 3001 is assigned to the video write-in period 3002 and the remaining half of one frame period 3001 is assigned to the blanking period 3003, and a voltage signal is applied to the pixel row corresponding to each of the lines at one line selection period 3004. However, when selection periods 3004 of a pair of lines G1, G2 selected simultaneously are compared to each other, a selection period of the line G2 on the side of a pair of lines G3, G4 selected next is delayed relative to that of line G1 by a time 3005. This time 3005 is also called a gate selection timing delay at the aforesaid 2-line simultaneous write-in. The present invention is characterized in that the gate selection timing delay is set for each 2-line simultaneous write-in scanning. This gate selection timing delay 3005 is also set for each of the other pairs of lines G3, G4; Gi−1, Gi; and Gn−1, Gn each of which is selected simultaneously.
On the other hand, the drain waveform 3107 indicates a potential variation according to the video data to be supplied to the pixel rows corresponding to the selected two lines for each two lines. It is apparent that if the video data to be supplied to the pixel rows corresponding to a pair of lines selected through a certain scanning and the video data to be supplied to the pixel rows corresponding to the other pair of lines selected by the subsequent scanning are equal to each other, this potential variation is scarcely produced. In
A potential of the drain waveform 3107 becomes a value corresponding to the video data to be supplied to the pair of line Gy−1 and line Gy at the time of being slightly delayed from a starting time of the line selection period 3104 of the gate waveform 3106 to be applied to the line Gy−1. In addition, also at the finishing time of the line selection period 3104 of the gate waveform 3106 (a time at which the gate voltage is lowered to a “Low” state), the potential of the drain waveform 3107 keeps the value corresponding to the video data. Accordingly, although a potential of the pixel electrode corresponding to the line Gy−1 in the line selection period 3104 of the gate waveform 3106 finally increases up to a potential or its near value of the drain line corresponding to the video data to be supplied to the pair of lines Gy−1, Gy even though its rising is slightly delayed in regard to that found at the starting time of the line selection period 3104 as shown in the source waveform 3108.
On the other hand, the potential of the drain waveform 3107 is already set at a value corresponding to a video data to be supplied to the pair of lines Gy−1, Gy at the starting time of the line selection period 3104 of the gate waveform 3110 applied to the line Gy. However, the potential of the drain waveform 3107 has already changed to a value corresponding to the video data to be supplied to a pair of line Gy+1 and line Gy+2 before the finishing time of the line selection period 3104 of the gate waveform 3110 applied to the line Gy. In the case of an example shown in
More specifically, in the waveform shown in
Further, in the present embodiment, the display device provided with a pixel array operated in a normally black mode is driven by the so-called frame inversion system in which a write-in polarity of a voltage signal to the pixel (a polarity of the drain line potential relative to the common potential) is kept in the frame period and inversed for each frame period.
By shifting a gate selection pulse in at least one line of a plurality of lines (the aforesaid first line group) to be selected simultaneously along a time axis from a gate selection pulse in another line as described in the present embodiment, both data (the first line data) inputted to another line in the first line group and data (the second line data) inputted to the aforesaid second line group selected subsequent to the first line group are written in at least the one line. Consequently, since a gray scale not found in both line data is generated in an analogue mode in at least one line described above, a display device user is scarcely aware of a reduction in vertical resolution of a display screen.
<Embodiment 7>
In the embodiment 6, there has been described a pixel array drive system in which the pixel rows (or pixel row group) indicating an intermediate gray scale relative to a gray scale of each of the pixel row groups are generated between a pair of adjacent pixel rows of the pixel row groups in a plurality of lines selected in sequence. However, a technical concept similar to this drive system can be embodied by another pixel array drive system. In the present embodiment, there will be described another pixel array drive system.
In the present embodiment, an original image inputted, as a progressive image having a frequency of 60 Hz, to video equipment having a system shown in
These video data are created such that the horizontal data having only odd-numbered video data of the original image and the horizontal data having even-numbered video data of the original image for each sub-field period of 16.7 ms are generated alternatively. Since the original image is inputted to the display device for each frame period of 16.7 ms, the even-numbered horizontal data of the original image inputted for each frame period is wasted when the former video data is generated, and the odd-numbered horizontal data of the original image inputted for each frame period is wasted when the latter video data is generated. Therefore, it is no exaggeration to say that the original image inputted to the display device by the progressive mode is converted into the video in an interlace mode within the display device (e.g., the display control circuit arranged in the display device). Accordingly, although the odd-numbered horizontal data of the original image and the even-numbered horizontal data of the original image in the present embodiment are synthesized at the pixel array for each 2 frame periods (i.e. 33 ms) of the original image, its image quality is not deteriorated as long as the moving image is displayed.
In the present embodiment, only the odd-numbered horizontal data of the original image are written in sequence for each two lines in the pixel array in a sub-field period (hereinafter called the first field period) and only the even-numbered horizontal data of the original image are written in sequence for each two lines in the pixel array in the next sub-field period (hereinafter called the second field period) subsequent to the first field period. However, another feature of the present embodiment consists in the fact that a combination of two lines of the pixel array selected for each horizontal data of the original image is changed depending on the first field period and the second field period. For example, the odd-numbered horizontal data 1, 3, 5, 7, . . . , 2n−1 of the original image are inputted in sequence into each of a pair of lines in the pixel array: G1 and G2; G3 and G4; G5 and G6; G7 and G8 . . . Gn−1 and G2n by 2-line simultaneous write-in scanning in the first field period (refer to
In the present embodiment, an operation for selecting simultaneously the gate lines in the pixel array for each two lines at the front half of each of the first field period and the second field period and writing the video data into the pixel rows corresponding to the two lines is repeated as described above, and then the scanning for one picture with the video data corresponding to each of the field periods is completed. In the case where the original image is a progressive image with a frequency of 60 Hz, each of the field periods has the same length as that of one frame period of the original image as described above, so that scanning for one picture with the video data is finished with about 8.4 ms, which is half of one frame period: 16.7 ms of the original image. Subsequent to the scanning for one picture with the video data, an operation for selecting simultaneously the gate lines of the pixel array for each two lines by the same procedure as that for the scanning of video data for one picture in each of the field periods, at the rear half of each of the first field period and the second field period, and writing the blanking data to the pixel rows corresponding to the two lines is repeated, and then the video signal inputted to each of the pixels in the pixel array in the front half of each of the field periods is replaced with a blanking signal (e.g., a voltage signal displaying the pixel in black).
In the present embodiment, a combination of gate lines for each two lines selected for inputting of blanking data in the second field period has been set in the same manner as that selected through inputting of the even-numbered horizontal data of the original image in the aforesaid second field period (except certain data) while a combination of gate lines for each two lines selected for inputting either the video data or the blanking data in the first field period is shifted by one line in the vertical direction of the pixel array. As regards inputting of the blanking data, although there is no trouble in a displaying operation even if a combination of the gate lines for each two lines selected in the second field period is set in the same manner as that for the first field period, changing the inputting mode for the blanking data is advantageous for controlling the display device in accordance with the case where the video data inputting mode (scanning mode) for one picture is changed for each field period. Scanning for one picture with the blanking data at the rear half of each of the first field period and the second field period is completed in half of one frame period of the original image: 16.7 ms, i.e. about 8.4 ms in the same manner as that of the scanning for one picture with the video data irrespective of setting for the combination of gate lines for each two lines in the second field period.
As described above, the present embodiment performs the following two operations alternately: one operation is performed such that a scanning for performing a simultaneous wiring-in of odd-numbered horizontal data of the original image (hereinafter called odd-numbered lines) in sequence for each two lines in the pixel array is carried out for one picture, then a scanning for writing-in the blanking data (e.g., black data) into the pixel array is carried out for one picture to display the first sub-field video with 60 Hz in the aforesaid first field period; and the other operation is performed such that a scanning for performing a simultaneous writing-in of even-numbered horizontal data of the original image (hereinafter called even-numbered lines) in sequence for each two lines in the pixel array is carried out for one picture, then a scanning for writing-in the blanking data into the pixel array is carried out for one picture to display the second sub-field video with 60 Hz in the aforesaid second field period. With such operations, each of the first sub-field video and the second sub-field video is displayed in an impulse manner.
These two sub-field videos are displayed in such a manner as to be superimposed on the picture in the display device in the two frame periods of the original image. In other words, the present embodiment reproduces in a pseudo manner the interlace scanning performed by a Braun tube or the like by displaying the two sub-field videos held and displayed by a liquid crystal display device or an electroluminescent display device or the like on a video screen at a specific period (two frame periods for the original image) in an impulse-display manner. In the present embodiment in which each of the sub-field video images is generated with 60 Hz, this impulse-like interlace video image is displayed with a frequency of 30 Hz (33 ms in the field period).
There will be described an effect of another feature of the present embodiment for changing the combinations of two lines in the pixel array selected in sequence for each sub-field period, in one frame period in such a pseudo interlace scanning.
In the case where the combinations of selected pixel array for each two lines are not changed in each of the two sub-field periods, the two lines display a Yth odd-numbered line of the pixel array in the first field period. That is, the two lines display one of the line data of the original image. In addition, the two lines display the (Y+1)th even-numbered line of the original image in the second field period. That is, the two lines display another line data of the original image. Accordingly, a mere combination of the first field period with the second field period causes two line data of the original image to be displayed at four lines, and a gray scale displayed by the two lines through these periods is only one combination of the Yth odd-numbered data and the (Y+1)th even-numbered data. Consequently, the vertical resolution of video image reproduced at the pixel array is as small as 2/4=½ of the number of lines constituting the pixel array.
In the case where the combinations of two selected lines in the pixel array are changed in each of the two sub-field periods, the two lines display the Yth odd-numbered line of the original image in the first field period. That is, the two lines display one of the line data of the original image. However, in the second field period, one of these two lines displays (Y−1)th even-numbered line of the original image, and the other of these two lines displays (Y+1)th even-numbered line of the original image. That is, the two lines display other two line data of the original image. Accordingly, if the first field period and the second field period are merely combined to each other, three line data of the original image are displayed at four lines. Consequently, the gray scales displayed by the two lines through these periods become two combinations: Yth odd-numbered data and (Y−1)th even-numbered data; and Yth odd-numbered data and (Y+1)th even-numbered data. Therefore, the vertical resolution of the video image reproduced at the pixel array is also increased up to ¾ of the number of lines constituting the pixel array. The gray scale of the pixel array displayed in the vertical direction is made variable for each pixel row through the two sub-fields in this way, with the result that it is possible to display a soft moving image (a moving image having image quality similar to a photograph) with a gray scale between the lines being smoothly varied as compared with the method for scanning the pixel array while the data write-in operation through the 2-line simultaneous selection described in reference to embodiments 1 to 5 is carried out while a skip-scanning is performed for each two lines.
The original image inputted to the display device in the progressive mode is classified into video formats such as 480p, 720p, 1080p and the like in accordance with the vertical resolution (effective number of scanning) as shown in
On the other hand, the present embodiment can also be applied to display of the original image having some video formats such as 480i, 1080i and the like inputted to the display device in the interlace mode. The original image in the interlace mode includes video images of only odd-numbered lines and video images of only even-numbered lines generated while the horizontal data are alternatively removed for each one line. In the case of the original image with a video format of 1080i, the odd-number line video images with a vertical resolution of 540 and video images of only even-numbered lines with a vertical resolution of 540 are inputted to the display device to generate video images having a vertical resolution of 1080 on its display screen. Accordingly, in the case where the original image in an interlace mode is a still image, the video image shown in
When only the odd-numbered or even-numbered line video data formatted with 1080i in the interlace mode are displayed on a liquid crystal display panel having a resolution of XGA class in an impulse manner for each field period in accordance with the present embodiment, the number of vertical scanning lines in the liquid crystal display panel (pixel array) provided for each video display becomes 576 (refer to
As described above, in order to reproduce a moving image of the original image in the pixel array (display screen) or its effective display area in accordance with the present embodiment, scanning must be carried out at least for each picture on odd-numbered line video data and even-numbered line video data. Due to this fact, a period in which scanning for each picture with odd-numbered line video data and even-numbered line video data and scanning for each picture with a blanking data accompanied by each of the scanning are completed is defined as a frame period 3301. In the case where an original image is inputted to the display device as either a video image of the interlace mode or a video image of the progressive mode with a frequency of 60 Hz, the frame period 3301 for the displaying operation in accordance with the present embodiment becomes about 33 ms, and about 16.7 ms of the front half of the frame period is assigned to an odd-numbered field period 3302 where the video display of odd-numbered line and blanking processing performed for this video display are carried out and about 16.7 ms of the rear half is assigned to an even-numbered field period 3303 where video display of even-numbered line and blanking processing performed for this video display are carried out. As is apparent from a length of the odd-numbered field period 3302 and a length of the even-numbered field period 3303, these periods corresponds to one field period for the original image in an interlace mode with 60 Hz and one frame period for the original image in a progressive mode with 60 Hz, respectively.
A video write-in period 3304 is assigned to the front half of the odd-numbered field period 3302 and a blanking data write-in period 3305 is assigned to the rear half of the odd-numbered field period 3302 every about 8.4 ms. In addition, the odd-numbered line data of the original image is written in the video write-in period 3304 and the blanking data for displaying pixel in black, for example, is written in the blanking data write-in period 3305 through the selection of gate lines in the pixel array as shown in
In each of the odd-numbered field period 3302 and the even-numbered field period 3303, each of the lines is selected in a similar gate selection period 3306 and either a video signal or a blanking signal is transferred to pixel rows corresponding to each of the lines during this selection period. When the display device in accordance with the present embodiment recognizes the original image inputted to this display device a still image, the horizontal data of the original image are written in sequence for each lines of the pixel array, and blanking processing is not performed on the video data written into the pixel array. Accordingly, in accordance with the present embodiment, it is also possible to write the video data into the pixel array in the gate selection period 3306 having a similar length irrespective of a video displaying format (applicable to still image display or moving image display).
In the video write-in period 3304 of the odd-numbered field period 3302, the odd-numbered line video data 1, 3, 5, . . . are written in sequence from a pair of gate lines G1, G2 simultaneously for each two lines, and then scanning of one picture with the odd-numbered line video data is completed with writing-in of the (2n−1)-th video data into the gate lines G2n−1, G2. After this operation, black data is written in sequence simultaneously for two lines from the pair of gate lines G1, G2 in the blanking period 3305. The odd-numbered field period 3302 ends with completion of one picture scanning for the blanking data by writing-in of the black data into the gate lines G2n−1, G2n.
Then, an even-numbered field period 3303 starts from a video writing-in period 3307. As described above, a pair of gate lines to which each of the even-numbered line video data is written are set in such a manner to be shifted by one line with respect to that of odd-numbered line video data in a vertical direction.
In this case, when an address 2y (y is a natural number less than n) is assigned for data of an optional even-numbered line, the even-numbered line video data are written into a pair of pixel rows corresponding to a pair of gate lines to which the odd-numbered line video data with an address (2y−1) has already been inputted in another field period, by 2-line simultaneous write-in operation described in reference to the embodiment 1. That is, in the displaying operation for selecting every one line in the pixel array, the odd-numbered line video data with a certain address and the even-numbered line video data written into the pixel array subsequent to the writing-in operation of the video data into the pixel array are written into a pair of pixel rows corresponding to the same pair of gate lines in the 2-line simultaneous writing-in operation described in reference to the embodiment 1. In contrast to this, in the present embodiment, odd-numbered line data with an address 2y−1 are written into a pair of pixel rows corresponding to a pair of gate lines with addresses G2y−1 and G2y affixed in a vertical direction in the pixel array, and the even-numbered line data with an address 2y are written into a pair of pixel rows corresponding to a pair of gate lines with addresses of G2y and G2y+1 positioned lower than a pair of gate lines G2y−1, G2y by one line in the pixel array. Due to this fact, in the video writing-in period 3307 of the even-numbered field period 3303, the video data written into the upper-most gate line G1 in the pixel array is unfixed and the video data written into the lower-most gate line G2n in the pixel array is not written at a gate line other than the above.
Since the user of display devices (or audio visual equipment or information processing device provided with this display device) turns their eyes upon the center of display screen, the user is scarcely aware that either the content displayed at the pixel rows corresponding to the uppermost gate line G1 in the pixel array or even-numbered (2n)th line data is displayed only at the lowermost gate line G2n in the pixel array. However, the pixel array described above in reference to the present embodiment is replaced with an effective display area found in the video display indicated in
In view of the above possibility, in the present embodiment, the second even-numbered line video data written into the pixel array at first in the video write-in period 3307 of the even-numbered field period 3303 are written into three pixel rows corresponding to the three gate lines G1, G2, G3, and subsequently the even-numbered line video data 4, 6, 8, . . . are written in sequence from a pair of gate lines G4, G5 in a 2-line simultaneous write-in manner. Although writing of the second even-numbered line data into the pixel row corresponding to the line G1 is not directly related to an improvement of a vertical resolution in moving image display of the original image, a luminance displayed at the pixel row is prevented from being abnormally increased relative to a luminance around it over one frame period 3301 for a displaying operation at the pixel array. In another operation mode in which the pixel array is provided with an effective display area as shown in
One picture scanning with the even-numbered line video data is completed with writing of the (2n)th video data into the gate line G2 only. Thereafter, the gate lines are selected in sequence within the same blanking period 3308 as the video writing-in period 3307 in the same manner as that for the video writing-in period 3307, black data are written in sequence into the pixel rows corresponding to each of the two lines, from the pixel rows corresponding to three gate lines G1, G2, G3; pixel rows corresponding to two lines G4, G5; pixel rows corresponding to the subsequent two lines G6, G7; and subsequently up to pixel rows corresponding to two lines G2n−2, G2n−1. Upon completion of one picture scanning of blanking data through writing of the black data into the lowermost gate line G2n, the even-numbered field period 3303 is finished and concurrently the displaying operation in one frame period 3301 of the pixel array is also finished.
This displaying operation in one frame period 3301 is repeated in sequence for each two frame periods on the original image in the progressive mode, and for each two field periods on the original image in the interlace mode, whereby the moving image can be impulse displayed in the aforesaid pseudo interlace by the display device for hold-displaying the still image.
In the case of impulse display of the video under a pseudo interlace mode in accordance with the aforesaid present embodiment, line selection of the pixel array in the even-numbered field period 3303 may be shifted by one line relative to the line selection in the odd-numbered field period 3302 from (2y)th gate line in the midway along a vertical direction of the pixel array (because the users pay their concern to the center of the display device). In this case, the even-numbered line data with an address 2y or another data is written in a pixel row corresponding to a gate line with an address (2y−1) where the video data to be written becomes unfixed in the even-numbered field period 3303.
Alternatively, two gate lines are similarly selected for each gate selection pulse in the odd-numbered field period 3302 and the even-numbered field period 3303 up to the gate line with an address 2y along a vertical direction of the pixel array, the odd-numbered line data up to an address 2y−1 and the even-numbered line data up to an address 2y are written into the pixel array, thereafter the line selection of the pixel array in the odd-numbered field period 3302 is shifted by one line with respect to a line selection of the pixel array in the even-numbered field period 3303. For example, the odd-numbered line data with an address 2y+1 is written into only the pixel row corresponding to the gate line with an address (2y+1), subsequently the odd-numbered line data with an address of 2y+3 is written into pixel rows corresponding to two gate lines with addresses (2y+2), (2y+3), and, subsequent odd-numbered line data is written into the residual gate lines for each two lines (for each two pixel rows corresponding to each of the lines). In this case, the even-numbered line data with an address 2y+2 is written into the pixel rows corresponding to gate lines with addresses (2y+1), (2n+2) and subsequently the even-numbered line data with an address 2y+4 is written into the pixel rows corresponding to the gate lines with addresses (2y+3), (2y+4), and subsequent even-numbered line data is written into the remaining gate line for each two lines (for each two pixel rows corresponding to each of the lines), in sequence.
In the case where the two gate lines selected in the odd-numbered field period 3302 are shifted by one line in respective to that in the even-numbered field period 3303 over the pixel array or its effective display area, the odd-numbered line data 1 is written into the pixel row corresponding to only the gate line G1, the odd-numbered line data 3 is written into two gate lines G2, G3 and subsequent odd-numbered line data are written into the remaining gate lines for each two lines (for each two pixel rows corresponding to each of the lines), in sequence. In contrast to this, the even-numbered line data 2 are written into two gate lines G1, G2 and the subsequent even-numbered line data are also written into the remaining gate lines for each two lines (for each two pixel rows corresponding to each of the lines).
In this case, the video data to be written into the pixel row corresponding to the lowermost gate line 2n of the pixel array is unfixed in the odd-numbered field period 3302. However, it is satisfactory that the blanking data is written into the pixel row corresponding to the gate line G2n in accordance with writing of data into the gate line G1 (the uppermost line of the pixel array) when a pair of gate lines selected in the even-numbered field period 3303 are shifted by one line. In addition, the odd-numbered line data with an address n−1 written into the pixel rows corresponding to the gate lines G2n−2, G2n−1 may be written. Further, in the case where a video image is partially displayed at the pixel array as shown in
The order of odd-numbered field period 3302 and an even-numbered field period 3303 in one frame period 3301 may be properly inversed.
As shown in
In view of the gate line G3 shown in
It is possible to further increase a resolution of the moving image by the impulse display of the pseudo interlace video in accordance with the present embodiment described above.
<Embodiment 8>
The aforesaid preferred embodiments have illustrated the video data or the drive waveforms in the pixel array when the pixels are mainly displayed in black with the blanking data. In the present embodiment, there will be described a blanking data including a data area having different display colors of pixels in one picture in reference to a variation of the video image inputted to the display device or video data sent to the pixel array for each frame period or field period as another setting format of the blanking data.
In
The picture having a displayed video with the field period n displays a video image with the field period n in an impulse manner while being displayed in black over its entire area with a blanking video image n+1′, and then the video image with the field period n+1 is displayed. Such an impulse display of video image is carried out by 2-line simultaneous write-in operation of video data into the pixel array described in the aforesaid embodiment, for example. In the picture where the blanking video image n+1′ is displayed, the aforesaid area 3403 varying from the dark halftone to the light halftone is indicated as an area 3401 enclosed by a blank dotted line, and the aforesaid area 3404 varying from the light halftone to the dark halftone is indicated as an area 3402 enclosed by a blank dotted line.
When not only data write-in into the pixel array by 2-line simultaneous write-in but also an impulse-type display through black displaying over an entire area of a pixel array of the video image written into the pixel array for each field period is carried out, it has been assumed that all the video images written into the pixel array in the field period upon completion of one field period are once reset. However, in the liquid crystal display device or an electroluminescent type display device, its optical response characteristic is dependent on a manner of change in a gray scale signal supplied to the pixel, so that it is hard to make the uniform reset of the video displayed in the previous field period (the period n with respect to the period n+1, for example) from the picture.
One example of such a phenomenon as above will be described as follows in reference to the liquid crystal display device. An optical response in the liquid crystal layer (for example, a variation in its light transmission) in the liquid crystal display device becomes fast when an electric field in the liquid crystal layer is intensified as described above, and the optical response becomes slow when it is weakened. Due to this fact, in the case of the normally black mode type liquid crystal display device in which a potential difference applied to the liquid crystal layer is made small so as to decrease a light transmission of the liquid crystal layer (in other words, a display color of pixel is approached to black), it shows a tendency that a response speed when a pixel display is changed from its bright gray scale display to its dark gray scale display (resulting in black display) is made slow. In the video image with a field period n+1, this is apparent from the fact that a response characteristic of the area 3404 where its gray scale is changed from a gray scale of background at the picture to a gray scale of the belt pattern is slightly deteriorated as compared with the area 3403 where its gray scale is changed from a gray scale of the belt pattern to a gray scale of background in a picture.
In the liquid crystal display panel of IPS mode, which is one of the liquid crystal display devices of normally black mode, there is an area of halftone not reaching a black displayed state with the blanking data because an optical response from a halftone to another half tone is also slow.
In regard to the aforesaid problems,
The moving image generated over a video image with a field period n to a video image with a field period n+1 is displayed in an impulse manner by generating such a video image in a video display period and then a transition of belt pattern contour moved between the video images is made clearer.
In
This method provides an effect when an optical response in an area transferred from a dark halftone display state to a light halftone state is slow, and this method is preferable for the TN type liquid crystal display device of normally white mode as well as an IPS mode liquid crystal display device with a slow changing-over speed in a halftone display state.
An operation for setting an area having different brightness such as the area 3401 to the blanking video data with the blanking display period n+1′ is carried out by a display control circuit 114 of the display device or a circuit arranged around it, for example. In accordance with the comparator described in the embodiment 7, for example, a result in which an original image to be displayed in a field period n is compared with an original image to be displayed in a field period n+1 can be attained in a pixel unit during a period in which the original image with the field period n+1 is taken into a frame memory from outside, so that it is possible to process the blank video data written into the pixel array in the blanking display period n+1′ on the basis of the result above. The processed blank video data is transferred to the drain line drive circuit 105, and a blanking signal of voltage different from that of another pixel group, the so-called pseudo video signal is supplied to a pixel (pixel group) corresponding to the aforesaid area 3401 in the pixel array.
In
As described above, both the methods for correcting a displayed state at a varying portion of the video image in the picture described in reference to
<Embodiment 9>
As described in the embodiment 2 in reference to
Each of the drive waveforms shown in
In view of such circumstances as described above, in order to keep the drive waveform shown in
In order to hold a video image at the upper part of a picture, the video-varying areas 3501, 3502 generated in the blanking video displayed in black are displayed at a gray scale of halftone between a gray scale displayed in this area in the frame period n and black in place of displaying of black to cause a reduction in light transmission at the liquid crystal layer at the upper part of a picture to be delayed. Also at the lower part of the picture, the video-varying areas 3501, 3502 are displayed at a gray scale of halftone between black and a gray scale displayed in this area in the frame period n+1 in place of displaying of black. That is, the video data (video image with the frame period n+1) displayed just after the blanking video image n+1′ is written in advance in the video-varying areas 3501, 3502 on the lower side of the picture. Since the central part of the picture is also applied as a standard for setting the blink pulse, the blanking video image n+1′ is displayed in black and the video-varying areas 3501, 3502 are also displayed in black.
In this way, an interface condition is set at each of the video-varying areas 3501, 3502 in the blanking video n+1′ at the upper part, lower part and central part of the picture, respectively (displayed in gray scales different from each other), and a gradated image region in a vertical direction as shown in
With such an operation, even if a blink pulse is set to the central part of the picture, the liquid crystal layer at the upper part of the picture is kept in a light transmission corresponding to the video image already written at the time of turning-on of a lamp, resulting in that a dark display is restricted. In addition, since a light transmission of the liquid crystal layer at the lower part of the picture already starts to increase in response to the video image to be written at the time of turning-on of the lamp, the pixel rows at the lower part of the picture are displayed in a luminance corresponding to the video image. As a result, a non-uniform luminance of the liquid crystal display panel generated at each of the upper and lower portions of a picture becomes scarcely noticeable.
<Embodiment 10>
A blanking video image n+1′ is displayed at a picture in a period in which each of a video image with a frame period n and a video image with a frame period n+1 is displayed at the picture, and a blanking video image n+2′ is displayed at a picture in a period in which each of a video image with a frame period n+1 and a video image with a frame period n+2 is displayed at the picture. When the present embodiment is combined with the embodiment 1, the blanking video image n+1′ is written into the pixel array in a frame period n together with the video image with a frame period n, and the blanking video image n+2′ is written into the pixel array in a frame period n+1 together with the video image with a frame period n+1.
The blanking video n+1′ displays each of a background displayed by a video image with a frame period n and a belt pattern in a lower gradation than that displayed by the video image with a frame period n. This blanking video image n+1′ is generated as the so-called pseudo video data, which display a middle gradation between the image data with the frame period n and the blanking data displaying the entire picture in a low gradation (e.g., black) by superposing the blanking data on the image data with the frame period n. It is noted that this pseudo video data may be generated by either the display control circuit 114 or its peripheral circuit, or may be generated by a drain line drive circuit similar to the drain driver IC described in the embodiment 5 while the mask logic is replaced with a circuit synthesizing the aforesaid blanking data and the video data.
The blanking video n+2′ displays each of a background displayed by a video image with a frame period n+1 and a belt pattern BP in a lower gradation than that displayed by the video image with a frame period n+1 in the same manner as that of the blanking video n+1′.
When the blanking video image is not displayed in uniform black, but displayed by middle data generated by combination the video data displayed before this blanking video and the blanking data as disclosed in the present embodiment, a response characteristic to apparent black displayed state is delayed and the video image is generated in a state similar to the hold display as compared with a case in which the blanking video image is displayed in uniform black. With such an operation, the video image is displayed bright in the present embodiment, so that this embodiment is effective in displaying a video image with a less amount of motion.
<Embodiment 11>
There will be described below as to an optical response of the liquid crystal display panel and its improvement in a hold drive of the liquid crystal display device in which a display picture of the liquid crystal display panel is kept in a displayed state of a video image corresponding to the video data, and an impulse drive of the liquid crystal display device (refer to the aforesaid embodiment) in which it is replaced with the blanking video displayed state (a black displayed state, for example) after being set to this video displayed state, for each frame period (or field period) of the video data inputted to the liquid crystal display device.
These gray scale voltage waveforms and the response waveform for a light transmission are drawn for the liquid crystal display device for displaying a video image in a normally black mode. Accordingly, the potentials of the gray scale voltage waveforms 3701, 3702 are increased with a rise along the ordinate. The light transmission response waveforms 3703, 3704 in the liquid crystal layer show a high light transmission as they rise along the ordinate, thereby increasing a luminance at the picture of the liquid crystal display panel. When the light transmission of the liquid crystal layer and the video display according to its modulation are controlled in a normally black mode, the light transmission at the liquid crystal layer is theoretically increased as an electric field intensity generated in the liquid crystal layer is increased.
Each of a plurality of ordinates indicated by a solid line in
A potential of the gray scale voltage waveform 3701 for hold driving the liquid crystal layer is fixed to a value corresponding to the video data for each frame period to cause electric field intensity in the liquid crystal layer to be held at each of the frame periods. In contrast to this, the optical response waveform 3703 at the liquid crystal layer does not necessarily follow a potential of the gray scale voltage waveform, and the optical response waveform 3703 does not reach a low light transmission corresponding to the gray scale voltage of low-level even at the time of end of the frame period 3711 with respect to a variation from the high level (corresponding to a light halftone) of the frame period 3710 of the gray scale voltage waveform 3701 to a low level (corresponding to a dark halftone), for example. Conversely to this, the light transmission response waveform 3703 is kept at a lower light transmission than the light transmission indicated at the frame period 3710 at the time of end of the frame period 3712 where the gray scale voltage waveform 3701 is returned again to the same high-level as that of the frame period 3710 after four frame periods held at a low-level.
A potential of the gray scale voltage waveform 3702 for impulse driving a liquid crystal layer is fixed to a value corresponding to the video data at the front half for each frame period and fixed to a value corresponding to the blanking data (displaying the pixel in black, for example) at the rear half part. With such an operation, an electric field generated in the liquid crystal layer in intensity corresponding to the video data at the front half of the frame period is cancelled at the rear half of the frame period to decrease a light transmission at the liquid crystal layer (when the liquid crystal layer is driven in a normally white mode, an electric field in the liquid crystal layer is made maximum at the rear half of the frame period in opposition to the former). In contrast to this, a light transmission response waveform 3704 in the liquid crystal layer does not sufficiently follow a potential of the gray scale voltage waveform 3702 even in the frame period 3710 and it does not reach the minimum value even at the time of end of the frame period 3710.
The gray scale voltage waveform 3702 varies, similarly to the gray scale voltage waveform 3701, in such a way that the pixel is displayed in a light halftone subsequently to the frame period 3710 and frame period 3712 and the pixel is displayed in a dark halftone in four frame periods including a frame period 3711 between the frame period 3710 and the frame period 3712. Accordingly, the gray scale voltage waveform 3702 provides the aforesaid high-level or low-level gray scale voltage at the front half of each of the frame periods. In addition, the gray scale voltage waveform 3702 is kept at the lowest-level gray scale voltage lower than the aforesaid low-level at the rear half of each of the frame periods so as to display the pixel in black. Accordingly, it is expected that a light transmission of the liquid crystal layer is decreased in writing of the blanking data at the rear half of the frame period 3710 at a transition from the frame period 3710 for displaying the pixel bright to the frame period 3711 for displaying the pixel dark. However, as described above, since the light transmission response waveform 3704 in the frame period 3710 does not sufficiently follow the gray scale voltage waveform 3702 for impulse driving the liquid crystal layer, the maximum value of light transmission in the liquid crystal layer at the frame period 3711 becomes higher than that in the subsequent three frame periods. In addition, the light transmission of the liquid crystal layer cannot follow a rapid rising of the gray scale voltage waveform 3702 in the frame period 3712 for displaying the pixel displayed dark over four frame periods bright. Accordingly, the maximum value of the light transmission of the liquid crystal layer in the frame period 3712 is lowered as compared with the maximum value of the light transmission at the liquid crystal layer in the next frame period subsequent to the blanking data writing in the frame period 3712.
As described above, a light transmission at a liquid crystal layer indicates an approximately logarithmic response with a given time constant with respect to a variation of the gray scale voltage (electric field intensity in the liquid crystal layer) indicated as a rectangular wave extending along a time axis irrespective of a driving mode of the liquid crystal layer. In other words, it takes a time in which a light transmission of the liquid crystal layer indicates a value corresponding to its gray scale voltage with respect to a certain time where the gray scale voltage rapidly changes. The liquid crystal display device forces the liquid crystal molecules oriented by an initial condition to orient in a desired direction in accordance with the intensity of the electric field at the liquid crystal layer and weakens the electric field to return the liquid crystal molecules into their initial orientation so as to control the light transmission of the liquid crystal layer for displaying an image. Accordingly, the light transmission of the liquid crystal layer shows a hysteresis with respect to an increased or decreased state of the electric field intensity therein as described above and the response (variation in an orientation) to a variation of electric field intensity is made different also in accordance with an orientation of the liquid crystal molecules at a time where the electric field in the liquid crystal layer is changed. Accordingly, even in the impulse drive of the liquid crystal layer allowing a light transmission at the liquid crystal layer to drop in the writing of blanking data into the pixel array for each frame period, the data written into the pixel array before this frame period (in other words, an orientation of liquid crystal molecules due to the variation of the electric field applied in accordance with these data) appear as hysteresis in macroscopic view in the variation of a light transmission of the liquid crystal layer corresponding to each of the video data and blanking data written into the pixel array in the frame period. Therefore, the black level (blanking display color) a picture of the liquid crystal display device reaches by writing of the blanking data into the pixel array depends on the frame period.
In view of the aforesaid phenomena, even if the video data in the first frame period or its previous frame period is reset by the blanking data in the so-called video varying period or transit from the frame period (the first frame period) to the subsequent frame period (the second frame period) when the liquid crystal layer is impulse driven, its effect cannot probably be achieved sufficiently. For example, even if the picture is displayed in black in a video varying period (hereinafter called a black level reset), the bright video image displayed in the first frame period is left in a dark video image displayed in the second frame period, and, the dark video displayed in the first frame period is left in the bright video image displayed in the second frame period. In this way, a phenomenon in which the video image displayed prior to a certain frame period is generated at a video image displayed in the certain frame period is called image retention. This image retention makes a contour of an item moving in the picture blurred for each frame period, as already described in the embodiment 3 in reference to
Meanwhile, a total amount of response times required for rising and decreasing of the light transmission in the liquid crystal material mass produced at present is approximately in a range of 35 ms to 40 ms. As already described in the embodiment 1 or the embodiment 7, since the frame period of the original image inputted to the liquid crystal display device with a frequency of 60 Hz is 16.7 ms, it is no exaggeration to say that many kinds of liquid crystal materials cannot indicate a sufficient response in one frame period. In particular, liquid crystal materials used in the IPS type liquid crystal display device driven in a normally black mode have a delay response to the black level reset in the aforesaid video varying period and also has a delay response for a light transmission corresponding to the halftone display, so that the aforesaid image retention may be liable to appear after a special bright video image is displayed. In the case of the impulse drive for the liquid crystal layer for generating repeatedly an electric field corresponding to the video signal for each half period of the first frame period and an electric field corresponding to the blanking signal at the liquid crystal layer including the liquid crystal material described above, a light transmission of the liquid crystal layer cannot be responded sufficiently to a gradation corresponding to the black level as well as a gradation corresponding to the video signal as indicated by the optical response waveform 3704.
In the present embodiment, the aforesaid problems are overcome by processing each of the gray scale voltage waveforms 3701, 3702 and suppressing an image retention generated at the liquid crystal display panel hold driven or the liquid crystal display panel impulse driven.
The so-called liquid crystal material with a low response speed requiring time more than one frame period for a rising and a decreasing of the light transmission shows a superior hold characteristic. However, when the liquid crystal layer including this liquid crystal material is impulse driven, the hold characteristic has generated the aforesaid image retention. Accordingly, in the present embodiment, as shown in the frame periods 3713, 3714 in
In the present embodiment, when brightness of the video is changed at transition from the frame period (the first frame period) to the next frame period (the second frame period), the video data displayed in the second frame period is subjected to the aforesaid video processing. For example, in the case where the video in a light halftone is displayed in the first frame period and the video image of dark halftone is displayed in its subsequent second frame period, the video signal is set to a lower low-level than the low-level corresponding to the video image of dark halftone like the gray scale voltage waveforms 3705, 3706 in the frame period 3713 in
When the gray scale voltage waveforms 3705, 3706 are set as described above in the frame period 3713, an electric field in the liquid crystal layer varies substantially at the time of starting of the frame period 3713, so that liquid crystal molecules in the liquid crystal layer are released from the orientation to predetermined orientation and are likely to return to the initial orientated state. Although a variation in environment around the liquid crystal molecules as described above is also generated in the frame period 3711 in
In the case where the liquid crystal layer is impulse driven, an orientation of liquid molecules at the time of finishing of the frame period 3710 approaches the initial orientation state in accordance with the blanking signal applied in the frame period 3710 before the frame period 3713. At the time of end of the frame period 3710, the liquid crystal molecules driven by an electric field with the gray scale voltage waveform 3702 in
On the other hand, in the case where the dark halftone video image is displayed at the first frame period and a light halftone video image is displayed at its subsequent second frame period, the video signal is set to a higher-level than the high-level corresponding to the light halftone video as found in the gray scale voltage waveforms 3705, 3706 at the frame period 3714 in
The pixel in the frame period 3714 in
As described above, some deterioration causes for motion picture quality such as image retention, shear in color and reduction in contrast or the like caused by video hysteresis at the liquid crystal display panel are reduced by intensifying (setting a variation large) a variation in brightness of video data (pixel data) accompanied by a transition of the frame period in the present embodiment as compared with that of the original image inputted to the liquid crystal display device.
Processing (the so-called video processing) of the gray scale voltage waveform in accordance with the aforesaid present embodiment can be carried out as follows by a data processing system arranged in the liquid crystal display device (a liquid crystal display module) such as the display control circuit 114 or its peripheral circuit or the like shown in
As already been described in the embodiment 1 or the embodiment 7, a frame memory storing the original image inputted to the liquid crystal display device (a liquid crystal display module) is connected to the display control circuit 114. The original image in the first frame period (the first original image) and the original image in the second frame period (the second original image) are inputted in sequence from the interface of the liquid crystal display device (a terminal receiving video information from outside the liquid crystal display device) into the liquid crystal display device for each continuous pair of frame periods (the first frame period and the second frame period subsequent to the first frame period). In the first frame period, the first original image is inputted to the liquid crystal display device and stored in the frame memory. In the second frame period, the second original image is inputted to the liquid crystal display device and at the same time, the first original image is read out of the frame memory and the second original image is stored in the frame memory. This process has already been described in the embodiment 1 or the embodiment 7, and in the third frame period subsequent to the second frame period, an operation for reading out the second original image from the frame memory while the third original image is being inputted to the liquid crystal display device and for storing the third original image in the frame memory is repeated for each frame period.
In view of the second frame period in this case, the first original image read out of the frame memory and the second original image stored in the frame memory can be compared with each other by a comparator installed in the display control circuit 114 around the frame memory or its peripheral circuit, for example. Therefore, it is possible to specify an area where the display gray scale varies as compared with that of the first original image, in the second original image (video data). The gray scale variation area of the second original image is subjected to enhancement by the scanning data generator circuit 102 (refer to
In this way, in accordance with the present embodiment, it is possible to subject the gray scale voltage waveform outputted from the drain line drive circuit 105 to the drain line of the pixel array (a liquid crystal display panel) to correction preferable for suppressing the aforesaid image retention by a system installed in the liquid crystal display device (a liquid crystal module).
In accordance with the present invention, since the video data and the blanking data are displayed in one frame period by inserting the blanking data into the video data corresponding to one frame period, an effect of suppressing deterioration in video quality caused by the moving image blur and the like is provided. Further, in accordance with the present invention, since an increase in the number of drain driver is suppressed by selecting lines so as to cause the video data and the blanking data to be displayed at optional display elements in one frame period, an effect of suppressing a large-sized formation or a complex assembly of a structure of the display device.
Hirakata, Junichi, Kawabe, Kazuyoshi
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