A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.
|
1. A probe unit substrate comprising:
(a) an electrical insulating substrate having a surface;
(b) a first conductor layer formed on the surface of the substrate, the first conductor layer including:
first conductor patterns;
flatness improvement rings surrounding the first conductor patterns with first clearances therebetween; and
a second conductor pattern surrounding the flatness improvement rings with second clearances therebetween;
(c) a first insulating layer covering over the first conductor layer;
(d) at least one other conductor layer formed above the first insulating layer, and at least one other insulating layer covering over the other conductor layer; and
(e) probe mounting pads formed on a surface of an uppermost insulating layer of the at least one other insulating layer,
wherein
at least one of the at least one other conductor layer has a third conductor pattern and planarization patterns insulated from the third conductor pattern,
each of the planarization patterns has a plane size greater than the probe mounting pad, and
the planarization patterns are located beneath the probe mounting pads.
2. The probe unit substrate according to
|
The present invention relates to a probe unit substrate having a feature of planarization or leveling of probe mounting pads.
In this specification, the phrase “probe unit” signifies a unit having plural probes for testing electronic parts or electrical parts, and thus it corresponds to, for example, a probe card used for testing an electrical circuit on a semiconductor wafer or a probe unit used for testing a liquid crystal display. Further, the phrase “probe unit substrate” signifies a substrate for the probe unit, which has an internal wiring and is possible to support plural probes.
A clearance between the through-hole junction pad 24 and a grounding region 26 is filled with the first insulating layer 14 deposited therein. Accordingly, the surface of the first insulating layer 14 becomes not flat but shows undulation. Such undulation spreads to the second conductor layer 16 and the second insulating layer 18. Besides, if the second conductor layer 16 is formed in a predetermined pattern, other undulation resulting from the pattern is also added. As a result, undulation appears on the surface of the second insulating layer 18. If the probe mounting pad 20 rests on such an uneven surface of the second insulating layer 18, the surface of the probe mounting pad 20 would be in danger of being non-flat or being inclined from the horizontal condition even with flatness. Further, if the micro cantilever type probes 22 are fixed to the respective such probe mounting pads 20, it could lead to variation in heights of tips 30 of a number of probes 22.
The surface undulation of the first insulating layer 14 will be alleviated if the clearance between the through-hole junction pad 24 and the grounding region 26 is reduced. However, there is a restriction in reduction of the clearance, as will be described below.
Since the surface undulation of the first insulating layer 14 is caused by existence of the clearance 32, it would be possible to alleviate such undulation if the distance d is reduced. That is, as shown in
By the way, the technique regarding planarization of a multilayer wiring substrate is known as described below. Concerning the technique for fixing a probe to a conductor layer (which corresponds to the probe mounting pad) formed on the uppermost layer of the multilayer wiring substrate, an improvement in the surface flatness of the multilayer wiring substrate is disclosed in Japanese Patent Publication No. 2006-210473 A (the first publication).
In the first publication, a covering resin layer having through-holes is formed on an insulating base, and the through-holes are filled with conductor layers. Accordingly, the height of the surface of the covering resin layer is almost the same as the heights of the surfaces of the conductor layers, resulting in no irregularity. Then, an insulating resin layer and a wiring conductor layer can be formed above a combination of the above-described covering resin layer and the conductor layers. Accordingly, the surface irregularity of the multilayer wiring substrate is alleviated, and a conductor layer is formed on the surface of the multilayer wiring substrate and a number of probes are fixed to the conductor layer without variation in heights of the tips of the probes.
According to the above-described technique disclosed in the first publication, the surface irregularity of the multilayer wiring substrate is reduced, but the manufacturing process will be complicated to form “a covering resin layer having through-holes”. According to the first publication, formation of the through-hole in the covering resin layer requires 1) oxygen plasma treatment on the top side of the covering resin layer with the use of a metal layer as a mask, or 2) laser processing for removing a part of the covering resin layer to form through-holes.
It is an object of the present invention to provide a probe unit substrate in which the surface irregularity is alleviated without a complicated manufacturing process so that the probe mounting pads neither undulate nor slope. The probe unit substrate according to the present invention is characterized in formation of flatness improvement rings or planarization patterns in the multilayer wiring division so that the probe mounting pads keep the flat and horizontal conditions. The probe unit substrate according to the first aspect of the present invention has flatness improvement rings, and thus comprises: (a) an electrical insulating substrate having a surface; (b) a first conductor layer formed on the surface of the substrate, the first conductor layer including: first conductor patterns; flatness improvement rings surrounding the first conductor patterns with first clearances therebetween; and a second conductor pattern surrounding the flatness improvement rings with second clearances therebetween; (c) a first insulating layer covering over the first conductor layer; (d) at least one other conductor layer formed above the first insulating layer, and at least one other insulating layer covering over the other conductor layer; and (e) probe mounting pads formed on a surface of an uppermost insulating layer of the at least one other insulating layer.
It should be noted, in the present specification, that the words “above” and “beneath” signify the directions described below. The word “above” signifies a direction from the electrical insulating substrate toward the probe mounting pads, and the word “beneath” signifies the opposite direction. Therefore, the words “above” and “beneath” have no connection to the posture of the probe unit substrate and its components against the gravity.
The probe unit substrate according to the second aspect of the present invention has planarization patterns, and thus comprises: (a) an electrical insulating substrate having a surface; (b) a first conductor layer formed on the surface of the substrate; (c) a first insulating layer covering over the first conductor layer; (d) at least one other conductor layer formed above the first insulating layer, and at least one other insulating layer covering over the other conductor layer; and (e) probe mounting pads formed on a surface of an uppermost insulating layer of the at least one other insulating layer. Further, the probe unit substrate according to the second aspect has a feature in which: at least one of the at least one other conductor layer has a conductor pattern and planarization patterns insulated from the conductor pattern; each of the planarization patterns has a plane size greater than the probe mounting pad; and the planarization patterns are located beneath the probe mounting pads.
The probe unit substrate according to the third aspect of the present invention has both flatness improvement rings and planarization patterns, and thus comprises: (a) an electrical insulating substrate having a surface; (b) a first conductor layer formed on the surface of the substrate, the first conductor layer including: first conductor patterns; flatness improvement rings surrounding the first conductor patterns with first clearances therebetween; and a second conductor pattern surrounding the flatness improvement rings with second clearances therebetween; (c) a first insulating layer covering over the first conductor layer; (d) at least one other conductor layer formed above the first insulating layer, and at least one other insulating layer covering over the other conductor layer; and (e) probe mounting pads formed on a surface of an uppermost insulating layer of the at least one other insulating layer. Further, the probe unit substrate according to the third aspect has a feature in which: at least one of the at least one other conductor layer has a third conductor pattern and planarization patterns insulated from the third conductor pattern; each of the planarization patterns has a plane size greater than the probe mounting pad; and the planarization patterns are located beneath the probe mounting pads.
The probe unit substrate according the present invention has an advantage that the surface irregularity of the multilayer wiring division is alleviated so that the probe mounting pads on its surface neither undulate nor slope because of the formation of the flatness improvement rings or the planarization patterns as described above. Therefore, there is no variation in heights of the tips of the probes that are fixed to a number of the probe mounting pads respectively.
Embodiments of the present invention will be described in detail below with reference to the drawings.
Now, the risk of short circuit will be described. As shown in
The first conductor layer 12 includes the through-hole junction pads 24 and the grounding region 26 that surrounds the through-hole junction pads 24, but has no flatness improvement ring. The second conductor layer 16, the third conductor layer 54 and the fourth conductor layer 58 are wiring layers. On the other hand, the fifth conductor layer 62 is a grounding layer. The second conductor layer 16 includes planarization patterns 66 and a predetermined conductor pattern 67. The predetermined conductor pattern 67 corresponds to the third conductor pattern in the present invention. The fourth conductor layer 58 also includes planarization patterns 68 and a predetermined conductor pattern 69. The predetermined conductor pattern 69 also corresponds to the third conductor pattern in the present invention. The planarization patterns 66 and 68 are located beneath the probe mounting pads 20. The planar sizes of these planarization patterns 66 and 68 are larger than the planar size of the probe mounting pad 20. Further, the planar size of the lower planarization pattern 66 is larger than the planar size of the upper planarization pattern 68. Namely, comparing these planar sizes, there is a relationship that the probe mounting pad 20 is smaller than the planarization pattern 68, which is further smaller than the planarization pattern 66. For example, the probe mounting pad 20 is 120 micrometers square in planar size, the planarization pattern 68 is 150 micrometers square, and the planarization pattern 66 is 180 micrometers square. The planarization patterns 66 and 68 are intended to erase the boundary (which is the planar boundary between the conductor layer and the insulating layer) beneath the probe mounting pads 20. The planarization patterns 66 and 68 reduce, in the vicinity of the planarization patterns 66 and 68, the surface undulation of the second insulating layer 18 located above the planarization pattern 66 and the surface undulation of the fourth insulating layer 60 located above the planarization pattern 68. As a result, the surface undulation of the fifth insulating layer 64 is reduced in the vicinity of the probe mounting pads 20. Accordingly, the probe mounting pads 20 never undulate and keep almost horizontal. Therefore, the probes 22, which are fixed to such probe mounting pads 22, have no variation in heights of their tips 30. The planarization patterns 66 and 68 are preferably electrically connected with different patterns made of respective identical conductor layers, noting that it does not matter what kind of an electrical potential for the different pattern.
Next, the planar shape of the planarization pattern will be described.
Patent | Priority | Assignee | Title |
8378705, | Feb 29 2008 | NHK SPRING CO , LTD | Wiring substrate and probe card |
Patent | Priority | Assignee | Title |
5576630, | Jun 16 1993 | Nitto Denko Corporation | Probe structure for measuring electric characteristics of a semiconductor element |
6229095, | Oct 01 1998 | NEC Corporation | Multilayer wiring board |
6521843, | May 13 1998 | NEC Infrontia Corporation | Multilayer printed circuit board having signal, power and ground through holes |
6548858, | Mar 06 2001 | Mitac International Corp. | Multi-layer circuit board |
JP2006210473, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Dec 18 2007 | FUKAMI, YOSHIYUKI | MICRONICS JAPAN CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020365 | /0176 | |
Dec 27 2007 | Micronics Japan Co., Ltd. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Mar 11 2009 | ASPN: Payor Number Assigned. |
Jul 28 2012 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Aug 06 2012 | ASPN: Payor Number Assigned. |
Aug 06 2012 | RMPN: Payer Number De-assigned. |
Jul 19 2016 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Sep 08 2020 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Mar 17 2012 | 4 years fee payment window open |
Sep 17 2012 | 6 months grace period start (w surcharge) |
Mar 17 2013 | patent expiry (for year 4) |
Mar 17 2015 | 2 years to revive unintentionally abandoned end. (for year 4) |
Mar 17 2016 | 8 years fee payment window open |
Sep 17 2016 | 6 months grace period start (w surcharge) |
Mar 17 2017 | patent expiry (for year 8) |
Mar 17 2019 | 2 years to revive unintentionally abandoned end. (for year 8) |
Mar 17 2020 | 12 years fee payment window open |
Sep 17 2020 | 6 months grace period start (w surcharge) |
Mar 17 2021 | patent expiry (for year 12) |
Mar 17 2023 | 2 years to revive unintentionally abandoned end. (for year 12) |