A source drive circuit which drives a source line group (source lines) of a liquid crystal display, includes a source driver group (source drivers) which outputs drive signals, an analog switch group which connects the outputs of the source driver group to the source line group and disconnects the same from the source line group, an analog switch group which shortcuts the source line group to a common power supply and disconnects the same from the common power supply, and a switch control circuit which controls switch operations of both the analog switch groups. The switch control circuit turns ON the analog switch group after it has detected that all analog switches of the analog switch group have been turned OFF, and turns ON the analog switch group B after it has detected that all analog switches of the analog switch group have been turned OFF.
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1. A drive circuit for driving matrix lines of a matrix line group of a liquid crystal device, comprising:
a driver group having a plurality of drivers, each of which outputs a drive signal;
a first switch group having a plurality of first switches, each of which has conductive and non-conductive states, the first switch connecting an output of the driver to the matrix line in the conductive state and disconnecting the output of the driver from the matrix line in the non-conductive state;
a second switch group having a plurality of second switches, each of which has conductive and non-conductive states, the second switch connecting the matrix line to a precharge power supply in the conductive state and disconnecting the precharge power supply in the non-conductive state; and
a switch control circuit which controls the conductive states of the first and second switch groups,
wherein the switch control circuit sets the second switches to the conductive state when detecting all first switches of the first switch group have been made non-conductive states, and sets the first switches to the conductive state when detecting all second switches of the second switch group have been made non-conductive states.
11. A drive circuit for driving matrix lines of a matrix line group of a liquid crystal device and fanned on a semiconductor chip, comprising:
a driver group having a plurality of drivers, each of which outputs a drive signal, the driver group being formed on a central region of the semiconductor chip;
a first switch group having a plurality of first switches, each of which has conductive and non-conductive states, the first switch connecting an output of die driver to the matrix line in the conductive state and disconnecting the output of the driver from the matrix line in the non-conductive state, the first switch group being formed on the central region of the semiconductor chip;
a second switch group having a plurality of second switches, each of which has conductive and non-conductive states, the second switch connecting the matrix line to a precharge power supply in the conductive state and disconnecting the precharge power supply in the non-conductive state, the second switch group being formed on the central region of the semiconductor chip; and
a switch control circuit which controls the conductive states of the first and second switch groups and formed on a peripheral region of the semiconductor chip,
wherein the switch control circuit sets the second switches to the conductive state when detecting all first switches of the first switch group have been made non-conductive states, and sets the first switches to the conductive state when detecting all second switches of the second switch group have been made non-conductive states.
2. A drive circuit according to
wherein the switch control circuit sets the second switches of the second switch group to the conductive state when the input control signal is of the second logic value and the switch control circuit detects all the first switches of the first switch group have been made non-conductive states,
wherein the switch control circuit sets the second switches of the second switch group to the non-conductive state when the input control signal changes from the second logic value to the first logic value, and wherein the switch control circuit sets the first switches of the first switch group to the conductive state when the input control signal is of the first logic value and the switch control circuit detects all the second switches of the second switch group have been made non-conductive states.
3. A drive circuit according to
wherein the switch control circuit includes,
a first NOR gate which receives the input control signal as one input,
a first inverter which inputs an output of the first NOR gate,
a second inverter which inputs the input control signal,
a second NOR gate which receives an output of the second inverter as one input, and
a third inverter which inputs an output of the second NOR gate,
wherein the output of the first NOR gate is connected to NMOS gates of all the analog switches of the first switch group and the input of the second NOR gate,
wherein the output of the first inverter is connected to PMOS gates of all the analog switches of the first switch group,
wherein the output of the second NOR gate is connected to NMOS gates of all the analog switches of the second switch group and the input of the first NOR gate, and
wherein the output of the third inverter is connected to PMOS gates of all the analog switches of the second switch group.
4. A drive circuit according to
wherein when a second input control signal is of the first logic value, the switch control circuit holds the non-conductive state of the second switches even if the first input control signal is of the second logic value and the switch control circuit detects all the first switches of the first switch group have been made non-conductive states,
wherein when the second input control signal is of the second logic value, the switch control circuit sets the second switches of the second switch group to the conductive state when the first input control signal is of the second logic value and the switch control circuit detects all the first switches of the first switch group have been made non-conductive states,
wherein the switch control circuit sets the second switches of the second switch group to the non-conductive state when the second input control signal is of the second logic value and the first input control signal changes from the second logic value to the first logic value, and
wherein the switch control circuit sets the first switches of the first switch group to the conductive state when the first input control signal is of the first logic value and the switch control circuit detects all the second switches of the second switch group have been made non-conductive states or are being held non-conductive states.
5. A drive circuit according to
wherein the switch control circuit includes,
a first NOR gate which receives the first input control signal as one input,
a first inverter which inputs an output of the first NOR gate,
a second inverter which inputs the first input control signal,
a second NOR gate which receives an output of the first inverter as one input,
an AND gate which inputs the second input control signal and an output of the second NOR gate, and
a third inverter which inputs an output of the AND gate,
wherein the output of the first NOR gate is connected to NMOS gates of all the analog switches of the first switch group and the input of the second NOR gate,
wherein the output of the first inverter is connected to PMOS gates of all the analog switches of the first switch group,
wherein the output of the AND gate is connected to NMOS gates of all the analog switches of the second switch group and the input of the first NOR gate, and
wherein the output of the third inverter is connected to PMOS gates of all the analog switches of the second switch group.
6. A drive circuit according to
7. A drive circuit according to
8. A drive circuit according to
9. A drive circuit according to
10. A drive circuit according to
12. A drive circuit according to
13. A drive circuit according to
14. A drive circuit according to
15. A drive circuit according to
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1. Field of the Invention
The present invention relates to a liquid crystal drive circuit (source drive circuit and gate drive circuit or the like) which drives a matrix line group (gate line group and source line group or the like) placed in a liquid crystal panel of a liquid crystal device (liquid crystal display).
This application is counterpart of Japanese patent application, Serial Number 164786/2003, filed Jun. 10, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
As a conventional liquid crystal drive circuit, there has been proposed one wherein high-speed liquid crystal driving is realized by a precharge operation which upon 1-dot inversion driving or plural-dot inversion driving, disconnects output terminals (matrix lines) of the liquid drive circuit from outputs of drivers thereof and short-circuits the same to a common power supply or other output terminals disconnected from their corresponding drivers in like manner (see, for example, Japanese Laid Open Patent Application JP-A-11-30975.
In the conventional source drive circuit 3, the analog switch group A is turned OFF and the analog switch B is turned ON when an input signal PC is “0 and an output signal PCB of the inverter I is “1”. Thus, output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 3 are connected to their corresponding outputs of the source drivers SD1 through SDm so that signals outputted from the source drivers SD1 through SDm are respectively outputted to the source lines S1 through Sm.
Then, when the input signal PCB is brought to “1” and the output signal PCB of the inverter I reaches “0”, the analog switch group A is turned ON and the analog switch group B is turned OFF so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 3 are respectively disconnected from the outputs of the source drivers SD1 through SDm. Thus, the output terminals OUT1 through OUTm thereof are short-circuited to a common power supply Vcom so that precharge is carried out.
When the input signal PC is returned to “0” and the output signal PCB of the inverter I is returned to “1”, the analog switch group A is turned OFF and the analog switch group B is turned ON so that the output terminals OUT1 through OUTm (source line S1 through Sm) of the source drive circuit 3 are disconnected from the common power supply Vcom and connected to the outputs of the source drivers SD1 through SDm again, respectively.
In the conventional liquid crystal drive circuit, however, the two analog switch groups are controlled by the same one input signal PC. Therefore, a delay is developed in switching timing between both analog switch groups due to the capacitance of each analog switch and wiring capacitance or the like. The analog switches of the other analog switch group might be turned ON before the analog switches of one analog switch group are perfectly turned OFF.
In such a case, a problem arises in that the matrix lines are short-circuited before they are respectively disconnected from the outputs of the drivers, or the matrix lines are respectively connected to the outputs of the drivers before the short circuit of the matrix lines are cut off, whereby the outputs of the drivers are instantaneously short-circuited to cause a flow of overcurrent, thus no obtaining the original effect of the precharge operation.
The present invention has been made to resolve such a conventional problem. Therefore, an object of the present invention is to provide a liquid crystal drive circuit capable of preventing overcurrent developed upon precharge and a liquid crystal driving method.
According to one aspect of the present invention, for achieving the above object, there is provided a drive circuit for driving matrix lines of a matrix line group of a liquid crystal device and formed on a semiconductor chip, comprising:
a driver group having a plurality of drivers, each of which outputs a drive signal, the driver group being formed on a central region of the semiconductor chip
a first switch group having a plurality of first switches, each of which has conductive and non-conductive states, the first switch connecting an output of the driver to the matrix line in the conductive state and disconnecting the output of the driver from the matrix line in the non-conductive state, the first switch group being formed on the central region of the semiconductor chip;
a second switch group having a plurality of second switches, each of which has conductive and non-conductive states, the second switch connecting the matrix line to a precharge power supply in the conductive state and disconnecting the precharge power supply in the non-conductive state, the second switch group being formed on the central region of the semiconductor chip; and
a switch control circuit which controls the conductive states of the first and second switch groups and formed on a peripheral region of the semiconductor chip,
wherein the switch control circuit sets the second switches to the conductive state when detecting all first switches of the first switch group have been made non-conductive states, and sets the first switches to the conductive state when detecting all second switches of the second switch group have been made non-conductive states.
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:
Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.
[Matrix Line Group]
The source line group comprises m (where m: arbitrary integer greater than or equal to 2) source lines S1, S2, . . . , Sm. The gate line group comprises n (where n: arbitrary integer greater than or equal to 2) gate lines G1, G2, . . . , Gn. These source line and gate line groups constitute a matrix line group for driving switch transistors of m×n liquid crystal cells arranged in matrix form.
[Liquid Crystal Panel 1]
The liquid crystal panel 1 comprises m×n switch transistors TR11, TR21, . . . , TRm1, TR12, TR22, . . . TRm2, . . . . TR1n, TR2n, . . . , TRmn, and m×n liquid crystal cell capacitors CX11, CX21, . . . , CXm1, CX12, CX22, . . . , CXm2, . . . , CX1n, CX2n, . . . , CXmn. The switch transistors TRij (where i: any of integers from 1 to m, and j: any of integers from 1 to n), and the liquid cell capacitor CXij constitute each individual liquid crystal cell. These m×n liquid crystal cells are arranged in the liquid crystal panel in matrix form.
The source and drain of the switch transistor TRij are connected between the source line Si and a cell electrode of the liquid crystal cell capacitor CXij. The gate of the switch transistor TRij is connected to its corresponding gate line Gj. A common electrode of the liquid crystal cell capacitor CXij is connected to a common power supply Vcom.
[Gate Drive Circuit 2]
The gate drive circuit 2 is equipped with n gate drivers GD1, GD2, . . . , GDn. The gate drive circuit 2 drives the gate line Gj of the gate line group by means of the gate driver GDj.
[Source Drive Circuit 10]
As shown in
[Source Driver Group]
The source driver group comprises m source drivers SD1, SD2, . . . , SDm. The source driver group drives the corresponding source line Si of the source line group by means of the source driver SDi.
[Analog Switch Group A]
The analog switch group A comprises m analog switches (MOS switches) A1, A2, . . . , Am. The analog switch Ai is provided between an output terminal OUTi (source line Si) of the source drive circuit 10 and the common power supply Vcom (potential at the common electrode of each liquid crystal cell capacitor). The analog switch Ai short circuits the output terminal OUTi (source line Si) to the common power supply Vcom and disconnects it from the common power supply Vcom in accordance with signal levels applied to the signal lines a and a′, respectively. A position on the signal line A located near the output terminal of the NOR gate N1 is shown as position a. A position on the signal line A located near the input terminal of the NOR gate N2 is shown as position a′. The signal line A is provided in a direction in which the output terminals OUT are arranged. That is, the signal line A is extended in a direction parallel to the long side of the semiconductor chip. The point a is located at a left side of the semiconductor chip and the point a′ is located at a right side of the semiconductor chip. In the first embodiment, a precharge power supply for short-circuiting each output terminal (source line) of the source drive circuit for the purpose of precharge is set as the common power supply Vcom.
[Analog Switch Group B]
The analog switch group B comprises m analog switches (MOS switches) B1, B2, . . . , Bm. The analog switch Bi is provided between the output of the source driver SDi and the output terminal OUTi (source line Si of the source drive circuit 10. The analog switch Bi connects the output terminal OUTi (source line Si) to the output of the source diver SDi and disconnects it from the output of the source driver SDi in accordance with signal levels of the signal line B and B′, respectively. A position on the signal line B located near the input terminal of the NOR gate N1 is shown as position b. A position on the signal line B located near the output terminal of the NOR gate N2 is shown as position b′. The signal line B is provided in the direction in which the output terminals OUT are arranged. That is, the signal line B is extended in the direction parallel to the long side of the semiconductor chip. The point b is located at the left side of the semiconductor chip and the point b′ is located at the right side of the semiconductor chip.
[Switch Control Circuit 100]
As shown in
The input signal PC is inputted to the NOR gate N1 and the inverter I3. The output of the inverter I3 is connected to the input of the NOR gate N1. The input signal PC is a control signal which triggers the switch operations of the analog switch groups A and B.
The output of the NOR gate N1 is connected to the input of the inverter I1, the input of the NOR gate N2 and the gates of NMOSs of the analog switches A1 through Am. Also the output of the inverter I1 is connected to the gates of PMOSs of the analog switches A1 through Am.
The output of the NOR gate N2 is connected to the input of the inverter I2, the input of the NOR gate N1 and the gates of NMOSs of the analog switches B1 through Bm. Also the output of the inverter I2 is connected to the gates of PMOSs of the analog switches B1 through Bm.
In the switch control circuit 100, the NOR gates N1 and N2 and the inverter I3 constitute a flip-flop circuit. The analog switches A1 through Am of the analog switch group A are turned OFF when the signals appeared on the point a (output signal of NOR gate N1) and the point a′ (input signal of NOR gate N2) of the signal line Line A are “0”, and are turned ON when the signals appeared on the point a and the point a′ are “1”. Further, the analog switches B1 through Bm of the analog switch group B are turned OFF when the signals appeared on the point b′ (output signal of NOR gate N2) and the point b (input signal of NOR gate N1) of the signal line Line B are “0”, and are turned ON when the signals appeared on the point b′ and the point b are “1”. As shown in
[Operation of First Embodiment]
The operation of the source drive circuit 10 of the first embodiment will be explained below with reference to
[Driver Output Period]
During a driver output period, the input signal PC (input signal of NOR gate N2 and inverter I3) is “0”, and the signal PCB (input signal of NOR gate N1 and output signal of inverter I3) is “1”. Thus, since the point a (output signal of NOR gate N1) and the point a′ (input signal of NOR gate N2) is “0”, and the output signal of the inverter I1 is “1”, the analog switch group A is held OFF so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are disconnected from the common power supply Vcom.
Further, since the point b′ (output signal of NOR gate N2) and the point b (input signal of NOR gate N1) are “1”, and the output signal of the inverter I2 is “0”, the analog switch group B is held ON so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are respectively connected to the outputs of the source drivers SD1 through SDm. Thus, the output signals of the source drivers SD1 through SDm are outputted to their corresponding source lines S1 through Sm.
[Operation for Switching from Driver Output Period to Precharge Period]
Next, when the input signal PC is brought to “1”, the point b′ reaches “0” at first, and the signal b also becomes “0” with being delayed due to wiring capacitance or the like (see FIGS. 4(1) and 4(3)). Since the output signal of the inverter I2 is also brought to “1” in like manner, the analog switch group B is turned OFF so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are respectively disconnected from the outputs of the source drivers SD1 through SDm) thus resulting in high impedance.
When the input signal PC is brought to “1”, the signal PCB reaches “0” (see FIGS. 4(1) and 4(2)). When the signal PCB is “0” and the point b becomes “0”, the point a reaches “1” at first and the point a′ also becomes “1” with being delayed due to wiring capacitance or the like (see FIGS. 4(3) and 4(4)). Since the output signal of the inverter I1 also becomes “0” similarly, the analog switch group A is turned ON so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are short-circuited to the common power supply Vcom.
When the point b is brought to “1”, the analog switch group B is all already held OFF. Thus, since the point a is not brought to “1” unless the point b reaches “0” even if the signal PCB is brought to “0” in the switch control circuit 100, the analog switch group B is all turned OFF. Unless the source line group is all disconnected from the source driver group, the analog switch group A is not brought to ON and the source line group is not short-circuited to the common power supply Vcom. That is, the switch control circuit 100 detects that the signal PCB has reached “0” (the input signal PC has been brought to “1”) and the point b has reached “0” (that is, the analog switch group B has all been brought to OFF) and thereafter brings the point a to “1” to turn ON the analog switch group A.
[Precharge Period]
During the precharge period, the input signal PC (input signal of NOR gate N2 and inverter I3) is “1” and the signal PCB (input signal of NOR gate N1 and output signal of inverter I3) is “0”. Thus, since the point b′ (output signal of NOR gate N2) and the point b (input signal of NOR gate N1) are “0” and the output signal of the inverter I2 is “1”, the analog switch group B is held OFF and hence the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are respectively disconnected from the source drivers SD1 through SDm.
Since the point a (output signal of NOR gate N1) and the point a′ (input signal of NOR gate N2) are “1”, the analog switch group A is held ON and hence the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are short-circuited to the common power supply Vcom, whereby precharge is carried out.
[Operation for Switching from Precharge Period to Driver Output Period]
Next, when the input signal PC is brought to “0”, the signal PCB reaches “1” (see FIGS. 4(1) and 4(2)). When the signal PCB is brought to “1”, the point a reaches “0” at first and the point a′ also becomes “0” with being delayed due to wiring capacitance or the like (see FIGS. 4(2) and 4(4)). Since the output signal of the inverter I1 is also brought to “1” in like manner, the analog switch group A is turned OFF so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are disconnected from the common power supply Vcom, thus resulting in high impedance.
When the signal PC is “0” and the point a′ reaches “0”, the point b′ is brought to “1” and the point b also becomes “1” with being delayed due to wiring capacitance or the like (see FIGS. 4(4) and 4(3)). Since the output signal of the inverter I2 also becomes “0” in like manner, the analog switch group B is turned ON so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are respectively connected to the outputs of the source drivers SD1 through SDm. Thus, the output signals of the source drivers SD1 through SDm are respectively outputted to the source lines S1 through Sm.
When the point a′ is brought to “0”, the analog switch group A is all already held OFF. Thus, since the point b′ is not brought to “1” unless the point a′ reaches “0” even if the signal PC is brought to “0” in the switch control circuit 100, the analog switch group A is all turned OFF. Unless the source line group is all disconnected from the common power supply Vcom the analog switch group B is not brought to ON and hence the source line group is not connected to the outputs of the source driver group. That is, the switch control circuit 100 detects that the signal PC has reached “0” and the point a′ has reached “0” (that is, the analog switch group A has all been turned OFF) and thereafter brings the point b′ to “1” to turn ON the analog switch group B.
According to the first embodiment as described above, the switch control circuit 100 detects that the analog switch group B has been all turned OFF and thereafter turns ON the analog switch group A, and detects that the analog switch group A has been all turned OFF and thereafter turns ON the analog switch group B. Thus, the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 10 are disconnected from the outputs of the source driver group or the common power supply Vcom, thus definitely resulting in high impedance for a moment, followed by being connected to the common power supply Vcom or the outputs of the source driver group. It is, therefore, possible to prevent overcurrent developed between the outputs of the source driver group and the common power supply Vcom upon precharge and realize liquid crystal driving of low power consumption at high speed, which exhibits the original effect of the precharge.
Since the flip-flop circuit detects that the analog switch group has been all brought to OFF, the amount of a delay due to the resistance/capacitance can automatically be complemented.
Further, according to the first embodiment, the flip-flop circuit of the switch control circuit is divided into two regions on the semiconductor chip so as to across the analog switch groups. As a result, resistance value, wiring capacitance and parasitic capacitance of the wrings (signal lines Line A and Line B) which connect between the divided elements of the flip-flop circuit are set to the same value. Therefore, time period in which the analog switch group A is brought to the OFF state (time period between the time when the point a is changed to “0” and the time when the point a′ is changed to “0”) and the time period in which the analog switch group B is brought to the OFF state (time period between the time when the point b′ is changed to “0” and the time when the point b is changed to “0”) can be set to substantially the same value without using a particular circuit. Therefore, the situation that the two switch groups are conductive states (ON state) at the same time can be prevented. Also, high speed operation can be obtained easily.
The liquid crystal display according to the second embodiment shown in
[Source Drive Circuit 20]
As shown in
[Switch Control Circuit 200]
As shown in
The AND gate AN outputs a signal to the point a with the input signal LP and a signal appeared at a point c (output signal of NOR gate N1) as inputs. The input signal LP is a control signal which permits/inhibits ON operations of the analog switch group A.
[Operation of Second Embodiment]
The operation of the source drive circuit 20 of the second embodiment will be explained below with reference to
A basic operation of the source drive circuit 20 of the second embodiment is similar to the source drive circuit 10 of the first embodiment. The second embodiment is different from the first embodiment in that the switch control circuit 200 is capable of permitting inhibiting the ON operations of the analog switch group A in accordance with the input signal LP.
[Driver Output Period]
During a driver output period, the input signal PC (input signal of NOR gate N2 and inverter I3) is “0”, the signal PCB (input signal of NOR gate N1 and output signal of inverter I3) is “1”, and the point c (output signal of NOR gate N1) is “0”. Thus, since the point a (output signal of AND gate AN) and the point a′ (input signal of NOR gate N2) is “0”, and the output signal of the inverter I1 is “1”, the analog switch group A is held OFF so that output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are disconnected from a common power supply Vcom.
Further, since the point b′ (output signal of NOR gate N2) and the point b (input signal of NOR gate N1) are “1”, and the output signal of the inverter I2 is “0”, the analog switch group B is held ON so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are connected to their corresponding outputs of source drivers SD1 through SDm. Thus, the output signals of the source drivers SD1 through SDm are respectively outputted to the source lines S1 through Sm.
[Operation for Switching from Driver Output Period to Precharge Period]
Next, when the input signal PC is brought to “1”, the point b′ reaches “0” at first, and the point b also becomes “0” with being delayed due to wiring capacitance or the like (see FIGS. 8(2) and 8(4)). Since the output signal of the inverter I2 is also brought to “1” in like manner, the analog switch group B is turned OFF so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are respectively disconnected from the outputs of the source drivers SD1 through SDm, thus resulting in high impedance.
When the input signal PC is brought to “1”, the signal PCB reaches “0” (see FIGS. 8(2) and 8(3)). When the signal PCB is “0” and the point b becomes “0”, the point c reaches “1” (see FIGS. 8(4) and 8(5)). If the input signal LP is “1” at this time (see FIG. 8(1)), the point a reaches “1” at first when the point c becomes “1”, and the point a′ also becomes “1” with being delayed due to wiring capacitance or the like (see FIGS. 8(5) and 8(6)). Since the output signal of the inverter I1 also becomes “0” similarly, the analog switch group A is turned ON so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are short-circuited to the common power supply Vcom.
When the point b is now brought to “1”, the analog switch group B is all held OFF. Thus, since the point a is not brought to “1” unless the signal b reaches “0” even if the signal PCB is brought to “0” in the switch control circuit 200, the analog switch group B is all turned OFF. Unless the source line group is all disconnected from the source driver group, the analog switch group A is not brought to ON and hence the source line group is not short-circuited to the common power supply Vcom. That is, the switch control circuit 200 detects that the signal PCB has reached “0” and the signal b has reached “0” (that is, the analog switch group B has all been brought to OFF) and thereafter brings the signal a to “1” to turn ON the analog switch group A.
[Precharge Period]
During the precharge period, the input signal PC (input signal of NOR gate N2 and inverter I3) is “1” and the signal PCB (input signal of NOR gate N1 and output signal of inverter I3) is “0”. Thus, since the point b′ (output signal of NOR gate N2) and the point b (input signal of NOR gate N1) are “0” and the output signal of the inverter I2 is “1”, the analog switch group B is held OFF and hence the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are respectively disconnected from the outputs of the source drivers SD1 through SDm.
Since the point a (output signal of NOR gate N1) and the point a′ (input signal of NOR gate N2) are “1” if the input signal LP is “1”, the analog switch group A is held ON and hence the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are short-circuited to the common power supply Vcom, whereby precharge is carried out.
[Operation for Switching from Precharge Period to Driver Output Period]
Next, when the input signal PC is brought to “0”, the signal PCB reaches “1” (see FIGS. 8(2) and 8(3)). When the signal PCB is brought to “0”, the point c reaches “0” (see FIGS. 8(3) and 8(5)). If the input signal LP is “1” at this time (see FIG. 8(1)), the point a reaches “0” at first when the point c is brought to “0”, and the point a′ also becomes “0” with being delayed due to wing capacitance or the like (see FIGS. 8(5) and 8(6)). Since the output signal of the inverter I1 is also brought to “1” in like manner, the analog switch group A is turned OFF so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are disconnected from the common power supply Vcom, thus resulting in high impedance.
When the signal PC is “0” and the point a′ reaches “0”, the point b′ is brought to “1” at first and the point b also becomes “1” with being delayed due to wiring capacitance or the like (see FIGS. 8(6) and 8(4)). Since the output signal of the inverter I2 also becomes “0” in like manner, the analog switch group B is turned ON so that the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 are respectively connected to the outputs of the source drivers SD1 through SDm. Thus, the output signals of the source drivers SD1 through SDm are respectively outputted to the source lines S1 through Sm.
When the point a′ is brought to “0”, the analog switch group A is all already held OFF. Thus, since the point b′ is not brought to “1” unless the point a′ reaches “0” even if the signal PC is brought to “0” in the switch control circuit 200, the analog switch group A is all turned OFF. Unless the source line group is all disconnected from the common power supply Vcom, the analog switch group B is not brought to ON and hence the source line group is not connected to the outputs of the source driver group. That is, the switch control circuit 200 detects that the signal PC has reached “0” and the point a′ has reached “0” (that is, the analog switch group A has all been turned OFF) and thereafter brings the point b′ to “1” to turn ON the analog switch group B.
Further, if the input signal LP is “0” during the precharge period in the switch control circuit 200, the points a and a′ remain at “0” if the point c is brought to “1” (see FIG. 7(7)). Since the output signal of the inverter I1 remains at “1” in like manner, the analog switch group A remains OFF and hence the output terminals OUT1 through OUTm (source lines S1 through Sm) of the source drive circuit 20 remain disconnected from the common power supply Vcom, thus resulting in no precharge (see FIG. 7(1)). Thus, the switch control circuit 200 is capable of controlling based on the input signal LP (control signal for permitting/inhibiting ON operations of the analog switch group A) whether the precharge operation should be done during the precharge period.
For instance, a polarity inversion signal or the like can be used as the input signal LP. Incidentally, if the input signal LP is fixed to “1”, then the operation of the switch control circuit 200 becomes similar to that of the switch control circuit 100 of the first embodiment.
In the conventional source drive circuit 3, as shown in
On the other hand, as shown in
According to the second embodiment as described above, an effect similar to the first embodiment is obtained, and whether the precharge operation should be done during the precharge period (the analog switch group A should be turned ON) is controlled based on the input signal LP, whereby a needless precharge operation at the plural-dot inversion driving can be eliminated, thereby making it possible to reduce power consumption.
Incidentally, although the switch control circuits 100 and 200 are respectively constituted of the NOR gates and the inverters in the first and second embodiments, they can be realized even by other logic circuits equivalent thereto. Although the switch control circuits 100 and 200 are configured with the logic “0” as the “L” level and the logic “1” as the “H” level, they can be realized even with the logic “0” as the “H” level and the logic “1” as the “L” level.
The switch control circuit 1000 shown in
The analog switch group A of the third embodiment comprises m analog switches (MOS switches) A1, A2, . . . , Am, and m resistors R1, R2, . . . , Rm. The analog switch Ai and the resistor Ri are provided in series between a source line Si (output terminal of source drive circuit) and a common power supply Vcom (potential at common electrode of liquid crystal cell capacitor). The analog switch A, short-circuits the source line Si (output terminal of source drive circuit) to the common power supply Vcom via the resistor Ri in accordance with signals a and a′ to thereby disconnect it from the common power supply Vcom.
According to the third embodiment as described above, an effect similar to the first or second embodiment is obtained, and precharge is carried out via the resistors to thereby make it possible to reduce a peak current and noise at the precharge.
As shown in
In the analog switch group A of the fourth embodiment, an analog switch Ai is provided between a source line Si (output terminal of source drive circuit) and a power supply VDS/2. The analog switch Ai short-circuits an output terminal OUTi (source line Si) to the power supply VDS/2 in accordance with signals a and a′ to thereby disconnect it from the power supply VDS/2.
Now, the power supply VDS/2 is equal to a power supply equivalent to one-half the power supply VDS supplied to source drivers SD1 through SDm. The power supply VDS/2 is a power supply having a potential which becomes the center of amplitude of each of the outputs of the source drivers SD1 through SDm.
Although the precharge power supply for short-circuiting the source line Si (output terminal of source drive circuit) for the purpose of precharge has been set as the common power supply Vcom, the common power supply Vcom might be set to a potential shifted from the power supply VDS/2 to carry out elimination of flicker or the like. It is desirable that in such a case, the precharge power supply is set to the power supply VDS/2 to realize liquid crystal driving of low power consumption at high speed.
According to the fourth embodiment as described above, an effect similar to the first or second embodiment is obtained, and the precharge power supply is set to the power supply VDS/2 to thereby make it possible to realize liquid crystal driving of low power consumption at higher speed.
As shown in
The analog switch group A of the fifth embodiment comprises m−1 analog switches (MOS switches) A1, A2, . . . , Am−1. An analog switch Ak (where k: any of integers from 1 to m−1) is provided between a source line Sk (output terminal of source drive circuit) and a source line Sk+1 (output terminal of source drive circuit). The analog switch Ak short-circuits between the source line Sk (output terminal of source drive circuit) and the source line Sk+1 (output terminal of source drive circuit) and cuts off a short circuit between the source lines (output terminals of source drive circuits) in accordance with signals applied to signal lines Line A and A′, respectively. Incidentally, a precharge power supply is set as other source line (other output terminal of source drive circuit) in the fifth embodiment.
According to the fifth embodiment as described above, an effect similar to the first or second embodiment is obtained, and the source lines (output terminals of source drive circuit) are short-circuited therebetween to perform precharge. Thus, since there is no need to supply the common power supply Vcom to the source drive circuit, power consumption can further be reduced.
As shown in
The analog switch A of the sixth embodiment comprises m−1 analog switches (MOS switches) A1, A2, . . . , Am−1, and m−1 resistors R1, R2, Rm−1. An analog switch Ak and a resistor Rk are provided in series between a source line Sk (output terminal of source drive circuit) and a source line Sk+1 (output terminal of source drive circuit). The analog switch Ak short-circuits between the source line Sk (output terminal of source drive circuit) and the source line Sk+1 (output terminal of source drive circuit) via the resistor Rk and cuts off the short circuit between the source lines (output terminals of source drive circuit) in accordance with signals a and a′, respectively.
According to the sixth embodiment as described above, an effect similar to the fifth embodiment is obtained, and precharge is done via the resistors to thereby make it possible to reduce a peak current and noise at the precharge.
As shown in
The analog switch group A of the seventh embodiment comprises m/2 (where m: even number in the present seventh embodiment) analog switches (MOS switches) A1, A3, . . . , Am−3, Am−1. An analog switch Ak is provided only between a source line Sk (output terminal of source drive circuit) whose k is an odd number, and a source line Sk+1 (output terminal of source drive circuit) whose k is an odd number. No analog switch is provided between source lines Sk and Sk+1 whose k is an even number. That is, the analog switch group A of the seventh embodiment is one wherein the analog switches corresponding to the number (m/2) equivalent to one-half the number (m) of the source lines are provided at the rate of one per two source lines.
According to the seventh embodiment as described above, an effect similar to the fifth embodiment is obtained, and the analog switch Ak is provided only between the source lines Sk (output terminal of source drive circuit) and Sk+1 (output terminal of source drive circuit) whose each k is the odd number, thereby making it possible to reduce the number of the analog switches of the analog switch group A.
Incidentally, although each of the first through seventh embodiments has explained the example in which the liquid crystal drive circuit of the present invention has been applied to the source drive circuit, the liquid crystal drive circuit of the present invention can also be applied to the gate drive circuit in like manner.
According to the present invention as described above, an effect is brought about in that overcurrent at precharge can be prevented from occurring and liquid crystal driving of low power consumption can be realized at high speed.
While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
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