In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.
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2. A semiconductor integrated circuit comprising:
a combinational circuit connected with a plurality of flip flop circuits;
the plurality of flip flop circuits for capturing a plurality of output signals from the combinational circuit and for forming at least a scan chain;
power source wiring for supplying power supply voltage to the plurality of flip flop circuits and the combinational circuit; and
a variable power supply circuit for varying the power supply voltage to the power source wiring;
wherein the variable power supply circuit supplies lower voltage to the combinational circuit during shift operation for scan testing than during capture operation.
1. A semiconductor integrated circuit comprising:
a combinational circuit connected with a plurality of flip flop circuits;
the plurality of flip flop circuits for capturing a plurality of output signals from the combinational circuit and for forming at least a scan chain;
flip-flop-circuit power source wiring for supplying first power supply voltage to the plurality of flip flop circuits; and
combinational-circuit power source wiring for supplying second power supply voltage to the combinational circuit,
wherein the flip-flop-circuit power source wiring and the combinational-circuit power source wiring are electrically separate from each other at least during scan testing and provide the first power supply voltage to the plurality of flip flop circuits and the second power supply voltage to the combinational circuit, respectively.
18. A semiconductor integrated circuit comprising;
a combinational circuit connected with a plurality of flip flop circuits;
the plurality of flip flop circuits for capturing a plurality of output signals from the combinational circuit and for forming at least a scan chain;
a flip-flop-circuit power source wiring for supplying first power supply voltage to the plurality of flip flop circuits; and
a combinational-circuit power source wiring for supplying second power supply voltage to the combinational circuit,
wherein the flip-flop-circuit power source wiring and the combinational-circuit power source wiring are electrically separate from each other and provide the first power supply voltage to the plurality of flip flop circuits and the second power supply voltage to the combinational circuit, respectively, and the first power supply voltage to the plurality of flip flop circuits and the second power supply voltage to the combinational circuit are independently adjustable.
3. The circuit of
4. The circuit of
during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the second power supply voltage to the combinational-circuit power source wiring is set to a voltage lower than the given voltage.
5. The circuit of
during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the first power supply voltage to the flip-flop-circuit power source wiring is set to a voltage higher than the given voltage.
6. The circuit of
7. The circuit of
a measuring circuit for measuring a period of restoring time required for variation in the power supply voltage supplied from the power source wiring to be restored to a steady state, and
a stop control circuit for stopping supply of a clock signal to the plurality of flip flop circuits during the period of restoring time.
8. The circuit of
a first region, in which a plurality of flip-flop-circuit standard cells are provided;
a second region, in which a plurality of combinational-circuit standard cells are provided;
the flip-flop-circuit power source wiring for supplying power to the plurality of flip-flop-circuit standard cells that form the first region; and
the combinational-circuit power source wiring for supplying power to the plurality of combinational-circuit standard cells that form the second region.
9. The circuit of
the rows of the plurality of flip-flop-circuit standard cells and the rows of the plurality of combinational-circuit standard cells are arranged alternately.
10. The circuit of
a combinational-circuit standard cell which includes a power source cut-off circuit.
11. The circuit of
a first power source wiring for supplying power to the plurality of flip flop circuits; and
a second power source wiring for supplying power to the combinational circuit,
wherein the power supply from the flip-flop-circuit power source wiring to the first power source wiring in each of the plurality of standard cells, and the power supply from the combinational-circuit power source wiring to the second power source wiring in each of the plurality of standard cells are performed independently of each other.
12. A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of
the first step of lowering the second power supply voltage to the combinational circuit;
the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed;
the third step of raising the second power supply voltage to the combinational circuit, after the second step has been performed; and
the fourth step of operating the combinational circuit, after the third step has been performed.
13. The method of
14. A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of
the first step of lowering the power supply voltage to the combinational circuit;
the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed;
the third step of raising the power supply voltage to the combinational circuit, after the second step has been performed;
the fourth step of stopping supply of a clock signal to the plurality of flip flop circuits for a certain period of time, after the third step has been performed; and
the fifth step of operating the combinational circuit, after the fourth step has been performed.
15. A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of
the first step of lowering the second power supply voltage to the combinational circuit;
the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed;
the third step of raising the second power supply voltage to the combinational circuit, after the second step has been performed;
the fourth step of stopping supply of a clock signal to the plurality of flip flop circuits for a certain period of time, after the third step has been performed; and
the fifth step of operating the combinational circuit, after the fourth step has been performed.
16. A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of
the first step of raising the first power supply voltage to the plurality of flip flop circuits;
the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed;
the third step of lowering the first power supply voltage to the plurality of flip flop circuits, after the second step has been performed; and
the fourth step of operating the combinational circuit, after the third step has been performed.
17. A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of
the first step of raising the power supply voltage to the plurality of flip flop circuits;
the second step of setting scan test data in the plurality of flip flop circuits, after the first step has been performed;
the third step of lowering the power supply voltage to the plurality of flip flop circuits, after the second step has been performed;
the fourth step of stopping supply of a clock signal to the plurality of flip flop circuits for a certain period of time, after the third step has been performed; and
the fifth step of operating the combinational circuit, after the fourth step has been performed.
19. The circuit of
20. The circuit of
during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the second power supply voltage to the combinational-circuit power source wiring is set to a voltage lower than the given voltage.
21. The circuit of
during shift operation for scan test signals provided in scan testing, in which the plurality of flip flop circuits are serially connected one after another, the first power supply voltage to the flip-flop-circuit power wiring is set to a voltage higher than the given voltage.
22. The circuit of
23. The circuit of
a measuring circuit for measuring a period of restoring time required for variation in the first power supply voltage supplied to the flip-flop-circuit power source wiring and the second power supply voltage supplied to the combinational-circuit power source wiring to be restored to a steady stage, and
a stop control circuit for stopping supply of a clock signal to the plurality of flip flop circuits during the period of restoring time.
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This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2005-24149 filed in Japan on Jan. 31, 2005, the entire contents of which are hereby incorporated by reference.
The present invention relates to semiconductor integrated circuits and methods for testing the same.
In recent years, progress in technology for microscaling semiconductor fabrication processes has continued without a letup, and the semiconductor technology has consequently moved into the era of the 90 nm and 65 nm generations. This progress has enabled a complex system conventionally composed of a plurality of LSIs to be integrated on a single silicon chip and realized as a system-on-a-chip. Since transistor integration per unit area and operating frequency have been increased rapidly, a plurality of IP cores having different functions and features can be incorporated into a single chip, thereby realizing a complex high-speed system-on-a-chip.
However, as the number of devices in a semiconductor circuit has increased, the amount of time required to test the circuit has increased. Also, the incorporation of cores having different features requires various types of tests to be performed. As a result, the test cost has been increasing. In addition, since current semiconductor circuits provide high-performance and high-speed operation, it has become difficult to assure high-quality test. Under these situations, system-on-a-chip venders have been studying semiconductor design technology and test techniques for realizing high-quality and low-cost test.
Popular methods conventionally used to test a logic circuit portion in a semiconductor integrated circuit include a scan test method. In order to perform a scan test, it is necessary to form a scan test circuitry in the semiconductor integrated circuit. A typical scan test circuitry is formed using a plurality of scan flip flop circuits in the semiconductor integrated circuit. Each scan flip flop circuit used has an input terminal D, an input terminal DT, a clock terminal CK, an input terminal NT, and a pair of output terminals Q and NQ. At the input terminal D, the flip flop circuit receives a data signal propagated through a circuit block (a combinational circuit). At the input terminal DT, the flip flop circuit receives a scan test signal. The clock terminal CK is used to receive a clock signal. At the input terminal NT, either the signal at the input terminal D or the signal at the input terminal DT is selected as data to be input to the flit flop circuit. From the pair of output terminals Q and NQ, the flip flop circuit outputs data signals.
The scan test circuitry has two modes. These modes are switched according to the value at the terminal NT. Specifically, when the value of the signal at the terminal NT is 1 (this state is called shift mode), the signal at the terminal DT is received by the flip flop circuit as input data. When the value of the signal at the terminal NT is 0 (this state is called capture mode), the signal at the terminal D is received by the flip flop circuit as input data.
The scan test circuitry, which is configured by sequentially connecting the terminals DT and the terminals Q (or NQ) of the scan flip flop circuits with one another, functions as a shift register during shift mode (NT=1) in scan test. An external input terminal, functioning as a scan-test-signal input terminal, is connected to the terminal DT of the scan flip flop circuit provided at the head of the shift register, while an external output terminal, acting as a scan-test-signal output terminal, is connected to the terminal Q or NQ of the scan flip flop circuit disposed in the last stage of the shift register. The terminals CK and NT of the scan flip flop circuits are directly controlled by external input terminals. The scan test circuitry thus configured is also called a scan chain, because the scan flip flop circuits are connected in the form of a chain. The semiconductor integrated circuit may include a plurality of scan chains.
In a typical scan test, an LSI tester supplies scan test signals to the scan-test-signal input terminal. The LSI tester also directly supplies a clock signal and a scan enable signal to the terminals CK and the terminals NT of the scan flip flop circuits, respectively.
While supplying a signal value of 1 as a scan enable signal, the LSI tester applies a clock signal during a period of time in which the number of rising edges of the clock signal is equal to the number of scan flip flop circuits in the scan chain, whereby scan test signals are supplied to all of the scan flip flop circuits forming the scan chain. Thereafter, the scan enable signal is switched to 0, and then one clock is input, whereby signals from the circuit block are captured by the terminals D of the scan flip flop circuits. Then, the scan enable signal is switched again to 1, and a clock signal is applied during a period of time in which the number of rising edges of the clock signal is equal to the number of scan flip flop circuits in the scan chain, whereby the signal values captured by the respective scan flip flop circuits are captured into the LSI tester.
The signal values captured into the LSI tester are then compared with expected values stored beforehand in the LSI tester so as to determine whether or not the captured signal values are appropriate.
In recent years, a logic circuit portion in a semiconductor integrated circuit is being tested using a built-in self-test (BIST) device, instead of performing a typical scan test. The most popular BIST architectures for testing a logic circuit portion include STUMPS (hereinafter, BIST for logic circuit portion will be referred to as “logic BIST”). STUMPS is a BIST architecture based on multiple scan designs. Like a scan test system, a STUMPS architecture uses a scan chain formed in the semiconductor integrated circuit, when performing a test.
The differences between logic BIST and scan test are a test-signal producing circuit and an output-response-signal comparison circuit. In scan testing, test signals are produced and an output-response-signal comparison circuit functions in the manners as described above. On the other hand, in logic BIST, control signals, such as a BIST seizure signal, a clock signal and the like, are applied from an LSI tester, whereby a test signal is produced from a pattern generation circuit included in the semiconductor integrated circuit, and the test signal is then applied to the target circuit to be tested. An output response signal from the circuit under test is input into an output compression circuit, in which the output response signal is converted into compressed data called signature. Finally, the signature is read into the LSI tester so as to be compared with the expected value thereof stored beforehand in the LSI tester, thereby determining whether or not the output signature is appropriate.
The number of devices included in a semiconductor integrated circuit has been increasing recently. Along with this increase, the amount of necessary test data has also been increasing. Furthermore, as technology for microscaling semiconductor fabrication processes has progressed, operation of a system-on-a-chip is adversely affected by small defects, which did not cause any problems before. High-resistance vias, short circuits, crosstalk, and other defects have manifested themselves as delay faults. Therefore, in addition to conventionally needed test data for stack-fault detection, test data for delay-fault detection is also required to be provided. Herein, the amount of test data required in scan test or in logic BIST means the amount of binary data obtained by multiplying the number of bits corresponding to the number of all scan flip flop circuits by the number of captures.
In order to complete a test on a semiconductor integrated circuit (whether typical scan testing or typical logic BIST) in a short time, shift operation has to be performed at high speed for quick setting of test data in the scan chain, so that as many circuit blocks as possible can be tested simultaneously. Since the running cost of an LSI tester is very high, if the tester is used for a long time, the final manufacturing cost of the semiconductor integrated circuit will be affected significantly.
However, in scan test or logic BIST conducted in a semiconductor integrated circuit including numerous devices, high-speed shift operation of the scan chain formed for testing many blocks in the semiconductor integrated circuit causes the semiconductor integrated circuit to consume a significant amount of power, such that normal operation and thus appropriate test cannot be performed. In view of this, it is very important to reduce the power consumption required by shift operation performed in scan test or in logic BIST.
Therefore, Japanese Laid-Open Publication No. 2001-59856, for example, discloses a conventional method to overcome this problem. In this method, when shift operation is performed, output terminals (terminals Q), which transmit data from scan flip flop circuits to a function block (combinational circuit), are fixed, thereby reducing power consumption during the scan test.
In previous scan testing circuitry configurations, the signal value at the terminal Q of each scan flip flop circuit varies during shift mode according to a scan test signal applied to the scan flip flop circuit. At this time, many transistors within the combinational circuit simultaneously perform switching, thereby momentarily consuming a considerable amount of power. On the other hand, in the circuit shown in
The flip flop circuit shown in
In this configuration, when the HOLD signal is 1, the output of the AND circuit 24 is always 0 irrespective of whether the clock signal CLK is 1 or 0. Therefore, at this time, the output Q of the third latch circuit 25 is fixed at the value (0 or 1) held at the previous time regardless of the output value of the first latch circuit 22.
A scan flip flop circuit 11A′ shown in
In these conventional techniques, power consumption can be suppressed, but penalties are likely to occur in the circuit area and the speed of performing function. Specific penalties are described in the following.
For example, in the conventional flip flop circuit shown in
In the conventional flip flop circuit shown in
Therefore, the conventional flip flop circuits shown in
It is therefore an object of the present invention to effectively reduce power consumption during shift operation in scan testing and in logic BIST without increasing the circuit area and without adversely affecting the speed of performing function.
In order to achieve the above object, the present invention employs a structure in which only power supply voltage to a combinational circuit can be lowered during shift operation in scan testing and in logic BIST, thereby reducing power consumption in the combinational circuit.
Specifically, an inventive semiconductor integrated circuit includes: a combinational circuit; a plurality of flip flop circuits for holding a plurality of output signals from the combinational circuit; flip-flop-circuit power source wiring for supplying power supply voltage to the flip flop circuits; and combinational-circuit power source wiring for supplying power supply voltage to the combinational circuit, wherein the flip-flop-circuit power source wiring and the combinational-circuit power source wiring are separate from each other and provide the power supply to the flip flop circuits and the power supply to the combinational circuit, respectively.
Another inventive semiconductor integrated circuit includes: a combinational circuit; a plurality of flip flop circuits for holding a plurality of output signals from the combinational circuit; power source wiring for supplying power supply voltage to the flip flop circuits and the combinational circuit; and a power source cut-off circuit for cutting off the power supply voltage of the power source wiring to the combinational circuit.
In one embodiment of the present invention, the combinational circuit includes a plurality of blocks, and the power source cut-off circuit is disposed in each of the blocks.
In another embodiment of the present invention, an input terminal of each flip flop circuit is connected to an output terminal of the combinational circuit, and the semiconductor integrated circuit includes an intermediate-potential prevention circuit for preventing the input terminals of the flip flop circuits from having an intermediate potential.
In another embodiment of the present invention, the circuit further includes a variable power supply circuit for varying the power supply voltage of the flip-flop-circuit power source wiring and the power supply voltage of the combinational-circuit power source wiring.
In another embodiment, the flip flop circuits form a scan chain.
In another embodiment, during capture operation in which the output signals from the combinational circuit are captured into the flip flop circuits, the power supply voltage of the combinational-circuit power source wiring is set to a given voltage, and during shift operation for scan test signals provided in scan testing, in which the flip flop circuits are serially connected one after another, the power supply voltage of the combinational-circuit power source wiring is set to a voltage lower than the given voltage.
In another embodiment, during capture operation in which the output signals from the combinational circuit are captured into the flip flop circuits, the power supply voltage of the flip-flop-circuit power source wiring is set to a given voltage, and during shift operation for scan test signals provided in scan testing, in which the flip flop circuits are serially connected one after another, the power supply voltage of the flip-flop-circuit power source wiring is set to a voltage higher than the given voltage.
In another embodiment, the circuit further includes a built-in self-test device for performing a self-test of the combinational circuit.
In another embodiment, the circuit further includes: a measuring circuit for measuring a period of restoring time required for variation in the power supply voltage supplied from each power source wiring to be restored to a steady state, and a stop control circuit for stopping supply of a clock signal to the flip flop circuits during the period of restoring time.
In another embodiment, the circuit further includes: a first region, in which a plurality of flip-flop-circuit standard cells are provided; a second region, in which a plurality of combinational-circuit standard cells are provided; first power source wiring for supplying power to the flip-flop-circuit standard cells that form the first region; and second power source wiring for supplying power to the combinational-circuit standard cells that form the second region.
In another embodiment, the flip-flop-circuit standard cells are arranged in rows and the combinational-circuit standard cells are arranged in rows, the rows of the flip-flop-circuit standard cells and the rows of the combinational-circuit standard cells extending in the same direction; and the rows of the flip-flop-circuit standard cells and the rows of the combinational-circuit standard cells are arranged alternately.
In another embodiment, the circuit further includes a flip-flop-circuit standard cell and a combinational-circuit standard cell, and the combinational-circuit standard cell includes a power source cut-off circuit.
In another embodiment, the circuit further includes a plurality of standard cells, each of which includes therein: first power source wiring for supplying power to the flip flop circuits; and second power source wiring for supplying power to the combinational circuit, wherein power supply from the flip-flop-circuit power source wiring to the first power source wiring in each standard cell, and power supply from the combinational-circuit power source wiring to the second power source wiring in each standard cell are performed independently of each other.
An inventive semiconductor integrated circuit testing method for testing the semiconductor integrated circuits includes: the first step of lowering the power supply voltage to the combinational circuit; the second step of setting scan test data in the flip flop circuits, after the first step has been performed; the third step of raising the power supply voltage to the combinational circuit, after the second step has been performed; and the fourth step of operating the combinational circuit, after the third step has been performed.
Another inventive semiconductor integrated circuit testing method for testing the semiconductor integrated circuit includes: the first step of lowering the power supply voltage to the combinational circuit; the second step of setting scan test data in the flip flop circuits, after the first step has been performed; the third step of separately raising the power supply voltage to each block in the combinational circuit, after the second step has been performed; and the fourth step of operating the combinational circuit, after the third step has been performed.
In one embodiment of the present invention, in the first step, the power supply to the combinational circuit is cut off.
Another inventive semiconductor integrated circuit testing method for testing the semiconductor integrated circuit includes: the first step of lowering the power supply voltage to the combinational circuit; the second step of setting scan test data in the flip flop circuits, after the first step has been performed; the third step of raising the power supply voltage to the combinational circuit, after the second step has been performed; the fourth step of stopping supply of a clock signal to the flip flop circuits for a certain period of time, after the third step has been performed; and the fifth step of operating the combinational circuit, after the fourth step has been performed.
Another inventive semiconductor integrated circuit testing method for testing the semiconductor integrated circuit includes: the first step of lowering the power supply voltage to the combinational circuit; the second step of setting scan test data in the flip flop circuits, after the first step has been performed; the third step of separately raising the power supply voltage to each of blocks in the combinational circuit, after the second step has been performed; the fourth step of stopping supply of a clock signal to the flip flop circuits for a certain period of time, after the third step has been performed; and the fifth step of operating the combinational circuit, after the fourth step has been performed.
In one embodiment of the present invention, in the second step, the power supply to the combinational circuit is cut off.
Another inventive semiconductor integrated circuit testing method for testing the semiconductor integrated circuit includes: the first step of raising the power supply voltage to the flip flop circuits; the second step of setting scan test data in the flip flop circuits, after the first step has been performed; the third step of lowering the power supply voltage to the flip flop circuits, after the second step has been performed; and the fourth step of operating the combinational circuit, after the third step has been performed.
Another inventive semiconductor integrated circuit testing method for testing the semiconductor integrated circuit includes: the first step of raising the power supply voltage to the flip flop circuits; the second step of setting scan test data in the flip flop circuits, after the first step has been performed; the third step of lowering the power supply voltage to the flip flop circuits, after the second step has been performed; the fourth step of stopping supply of a clock signal to the flip flop circuits for a certain period of time, after the third step has been performed; and the fifth step of operating the combinational circuit, after the fourth step has been performed.
In the inventive semiconductor integrated circuits and the inventive test methods, during shift operation in scan testing, the power supply voltage to the combinational circuit is cut off or set to a lower voltage as compared with capture operation, thereby effectively suppressing the amount of power consumed by the combinational circuit during the shift operation. If, during the shift operation, the power supply voltage to the flip flop circuits is set to a higher voltage as compared with capture operation, the shift operation by the flip flop circuits is performed at higher speed, thereby effectively reducing the test time.
In the present invention, the reduction in the power consumed by the combinational circuit during the shift operation, and the reduction in the test time are achieved just by lowering the power supply voltage to the combinational circuit and by raising the power supply voltage to the flip flop circuits. Therefore, unlike in the conventional circuits and conventional test methods, these advantages can be obtained without increasing the circuit area or decreasing the operating speed. In addition, since the power to the combinational circuit is cut off during shift operation, it is possible to reduce not only the amount of power consumed by the switching operation by the transistor in the combinational circuit, but also the amount of power consumed by leakage current occurring in the CMOS transistor being in a static state. Such leakage current is caused by the thinning of the gate insulating film of the transistor and has been arising as a problem recently.
Also, according to one embodiment of the present invention, an intermediate-potential prevention circuit prevents the input terminals of the flip flop circuits from having an intermediate potential while the power supply voltage to the combinational circuit is cut off, thereby effectively preventing excessive leakage current flow in, and damage to, the combinational circuit.
Moreover, according to one embodiment of the present invention, during shift operation in scan testing, the power supply voltage to the combinational circuit is lowered or cut off, or the power supply voltage to the flip flop circuits is raised, whereby the power consumption is reduced, or the test time is shortened. Then, supply of a clock signal to the flip flop circuits is stopped only for a certain period of time before the following capture operation is performed, thereby providing a certain waiting time before the capture operation. The presence of waiting time allows the combinational circuit and the flip flop circuits to operate in normal operation mode with normal power supply voltage being supplied, whereby stable test on the combinational circuit is ensured.
Hereinafter, semiconductor integrated circuits and methods for testing the same according to preferred embodiments of the present invention will be described with reference to the accompanying drawings.
Hereinafter, a semiconductor integrated circuit and a method for testing the same according to a first embodiment of the present invention will be described.
In this configuration, the value of the voltage applied to the flip flop circuits and the value of the voltage applied to the combinational circuit can be individually adjusted in accordance with operation of the flip flop circuits and operation of the combinational circuit, respectively, whereby power consumption during the operation can be controlled. For example, the voltage applied to the flip flop circuits 102a to 102f can be adjusted according to variations in the clock frequency that occur during operation of the flip flop circuits 102a to 102f, or the voltage applied to the combinational circuit 101 can be adjusted in accordance with whether or not the combinational circuit 101 is performing necessary operation, whereby power consumption during the operation can be effectively reduced.
The above-mentioned advantage can be obtained in shift operation in scan testing, for example. The flip flop circuits 102a to 102f shown in
Nevertheless, such reduction in the operating frequency becomes a problem in cases in which high-speed shift operation is desired to reduce the test time. During shift operation, from the scan-in terminal, desired test data is serially set in the shift register, in which the flip flop circuits 102a to 102f are connected in a serial manner. The number of clock cycles required by this test data setting is equal to the number of flip flop circuits connected in the scan chain. Therefore, if the operating frequency during the shift operation is low, the amount of test time is increased, resulting in increase in the product cost. In view of this, it is desired that the operating frequency during shift operation be as high as possible.
In the semiconductor integrated circuit shown in
Even in a semiconductor integrated circuit in which no scan design has been implemented, if data can be set in flip flop circuits 102a to 102f from external input terminals as shown in
A scan test conducted in the semiconductor integrated circuit of
A typical semiconductor integrated circuit is not always designed so as to be capable of withstanding high-speed shift operation when the power supply voltage for normal operation is applied to the semiconductor integrated circuit. Even so, since the semiconductor integrated circuit of
A case in which the test methods of
In the semiconductor integrated circuit of the first embodiment, the two power supply voltages VDD1 and VDD2 may be supplied from devices external to the semiconductor integrated circuit, or may be supplied by a variable power supply circuit included in the semiconductor integrated circuit.
Moreover, in the semiconductor integrated circuit of the first embodiment of the present invention, the test data to the scan chain may be supplied from a device external to the semiconductor integrated circuit, or may be supplied from a built-in self-test (BIST) device included in the semiconductor integrated circuit.
Furthermore, the semiconductor integrated circuit of the first embodiment of the present invention may be provided with a counter for measuring a certain period of time required for voltage newly selected in power-supply-voltage switching to become stable, and a circuit for stopping supply of a clock signal during that measured time period.
The configuration of
Next, a semiconductor integrated circuit and a method for testing the same according to a second embodiment of the present invention will be described.
The configuration mentioned above makes it possible to independently cut off the power supply voltage applied to the combinational circuit 301, thereby reducing the power consumed when the combinational circuit 301 performs unnecessary operation.
The above-mentioned advantage can be obtained in shift operation in scan testing, for example. The flip flop circuits 302a to 302f shown in
A scan test conducted in the semiconductor integrated circuit of
The semiconductor integrated circuit of the second embodiment may be provided with a counter for measuring a certain period of time required for voltage newly selected in the power supply voltage switching step in
In the combinational-circuit standard cell 411 shown in
In the combinational-circuit standard cell 411 shown in
Similarly, in the flip-flop-circuit standard cell 412 shown in
As shown in
In this embodiment, the layout design that enables only the power supply to the combinational circuits to be cut off is facilitated without imposing any restrictions on the locations of the flip-flop-circuit cells and combinational-circuit cells.
Next, a semiconductor integrated circuit and a method for testing the same according to a third embodiment of the present invention will be described.
In
In the configuration mentioned above, the power supply voltage VDD applied to the block 501a and the power supply voltage VDD applied to the block 501b can be cut off independently of each other, thereby reducing the amount of power consumed when either the block 501a or 501b performs unnecessary operation. In addition, since it is possible to independently cut off and resume the supply of the power supply voltage VDD to each of the blocks 501a and 501b, the transistor switches 504a and 504b can be controlled so as to prevent a momentary change in the power supply voltage VDD in the entire combinational circuit 501, whereby abnormal operation in the combinational circuit 501 can be avoided.
The above-mentioned advantage can be obtained during shift operation in scan testing, for example. The flip flop circuits 502a to 502f shown in
A scan test conducted in the semiconductor integrated circuit of
The semiconductor integrated circuit of the third embodiment may be provided with a counter for measuring a certain period of time required for voltage newly selected in power-supply-voltage switching to become stable, and a circuit for stopping supply of a clock signal to the flip flop circuits.
In the above-described configuration, the supply of a clock signal to the flip flop circuits is stopped during the certain time period, causing the semiconductor integrated circuit to stop its operation. In this stop period, the supply of the power supply voltage VDD is resumed.
In
Therefore, it is possible to independently control the power cutoff and the power supply for each of the blocks 501a and the blocks 501b. This circuit configuration facilitates the layout design of the semiconductor integrated circuit in which only the power to the combinational circuits can be cut off, without imposing any restrictions on the locations of the flip-flop-circuit cells and combinational-circuit cells.
Next, a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described.
The gate signal SW is input into the terminals SW of the flip flop circuits 902a to 902f. When a logical value of 0 is applied to the gate signal SW, the potential of the terminals D of the flip flop circuits 902a to 902f is pulled down to ground potential VSS. When a logical value of 1 is applied to the gate signal SW, the pulling down is cancelled.
In the above-described configuration, even if an intermediate potential is generated within the combinational circuit 901 while the supply of the power supply voltage VDD to the combinational circuit 901 is cut off, it is possible to prevent the input terminals D of the flip flop circuits 902a to 902f from being at the intermediate potential, thereby preventing excessive leakage current in, and damage to, the combinational circuit.
Takeoka, Sadami, Ishimura, Takashi
Patent | Priority | Assignee | Title |
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