A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (pcm) and a heating device proximate the pcm. The heating device is configured to switch the conductivity of a transformable portion of the pcm between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
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1. A method for programming a programmable link structure of a three dimensional integration (3DI) semiconductor devices, comprising:
passing a current through a heating device, said heating device proximate a via filled at least in part with a phase change material (pcm), said via thereby defining a programmable link between an input connection located at one end thereof and an output connection located at another end thereof;
wherein said input connection of said programmable link is formed on a first metal level, input and output terminals for said heating device are located on a second metal level, and said output connection of said programmable link is formed on a third metal level;
wherein said via filled at least in part with said pcm is disposed between said input connection of said programmable link and a top side of said heating device, and wherein another via is disposed between a bottom surface of said heating device and said output connection of said programmable link, with said another via being disposed directly beneath one of the input and output terminals for said heating device, said another via filled with a metal material; and
wherein said heating device is configured to switch the conductivity of a transformable portion of said pcm between a lower resistance crystalline state and a higher resistance amorphous state.
2. The method of
3. The method of
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This invention was made with U.S. Government support under Government Contract No.: N66001-04-C-8032, awarded by the Defense Advance Research Projects Agency (DARPA). The U.S. Government has certain rights in this invention.
The present invention relates generally to field programmable circuits as related to three-dimensional integration and, more particularly, to a programmable via structure suitable for use in three-dimensional integration technology.
Traditionally, application specific integrated circuit (ASIC) devices have been used in the integrated circuit (IC) industry to reduce cost, enhance performance or meet space constraints. The generic class of ASIC devices falls under a variety of sub classes such as custom ASICs, standard cell ASICs, Gate Array, and Field Programmable Gate Array (FPGA), wherein the degree of user allowed customization varies.
In recent years, there has been a move away from custom, semi-custom and Gate Array ICs toward field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf FPGA products greatly simplify the design cycle and are fully customized by the user. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to improve silicon performance. While such programmability is expensive in terms of silicon real estate, it reduces design cycle time, time to solution (TTS) and upfront non-recurring engineering (NRE) costs to the designer.
Reconfigurable circuits, such as FPGAs, are also anticipated to play a significant role in the new Three Dimensional Integration (3DI) technology currently under development. In planar circuit technologies (i.e., the individual circuit elements are formed on a single, planar substrate), an FPGA 100 (as shown in
In contrast, 3DI structures (such as shown in
Existing field-programmable logic and memory repair technology utilizes several methods to physically make/break the connections between logic blocks; unfortunately, none of these existing methods provides a fully adequate solution to the requirements of a 3DI application. For instance, a laser-fusible link is an early approach, but has now replaced by electrical techniques entirely internal to the chip. Electromigration fuses, such as those in IBM's eFUSE technology for rerouting chip logic, are also currently in use. However, an electromigration fuse takes up a large circuit area and requires a high current to blow the fuse. Moreover, the process is “one-shot,” i.e., once the fuse is blown, it cannot thereafter be returned to a conducting state. Further, the distribution of eFuse characteristics is relatively broad, requiring that the state of each fuse be sensed by a discriminating circuit with the digital result stored in a latch.
Another existing approach for FPGA is the use of flash bits to control a pass transistor for each interconnection. A flash bit takes up space in the logic level, is formed by a process that is incompatible with standard CMOS processing, and requires a special high voltage to charge the gate oxide. As compared to a laser-blown fuse or an eFuse, the flash approach is considered limited multi-shot technique (e.g., about 20,000 reversals).
An anti-fuse approach used for some DRAM repair typically involves a very thin dielectric material such as silicon dioxide, or the sandwich combination silicon oxide-nitride-oxide (ONO), between two conductors. The anti-fuse is programmed by applying a relatively high voltage through the conducting terminals, thus causing dielectric breakdown in the dielectric. As a result, the resistance of the anti-fuse permanently changes from high to low. Accordingly, this represents another example of a one-shot technique, one that requires a high voltage.
The controllable link technologies described above do not have optimal properties for programmable logic applications in 3DI (or even for planar applications for that matter). In particular, a dependency on the use of high voltages (whether for gate charging in flash bit applications or for dielectric antifuses) is undesirable. In the case of flash bits, their presence in the logic level real estate may cause process incompatibilities, as described above. Electromigration fuses driven by relatively high current are large-area, require undesirably high power, and require an additional discriminator and latch circuitry. Furthermore, devices incorporating static RAM latches are subject to soft error arising from alpha particles or cosmic rays, which in a 3DI application may also have the effect of randomly altering the logic configuration. With the exception of flash bit technology (which has limited multi-shot capability), conventional fuse-based approaches are one-shot.
Accordingly, it would therefore be desirable to be able to configure a programmable link for a 3DI application that does not require high current or voltage to program, that is compatible with standard CMOS processing at the device level, that avoids the need for an SRAM latch to minimize space and avoid soft errors, and that is reprogrammable for a significant number of multiple instances (i.e., not single-shot).
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a programmable link structure for use in three dimensional integration (3DI) semiconductor devices. In an exemplary embodiment, the structure includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
In another embodiment, a method for programming a programmable link structure of a three dimensional integration (3DI) semiconductor devices includes passing a current through a heating device, the heating device proximate a via filled at least in part with a phase change material (PCM), the via thereby defining a programmable link between an input connection located at one end thereof and an output connection located at another end thereof. The heating device is configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state.
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
Disclosed herein is a programmable via structure suitable for use in 3DI technology. Briefly stated, a phase change material (PCM) is incorporated into a programmable via structure wherein the conductivity of the via is altered by a thermal SET or RESET process that changes the crystal properties of the PCM, and therefore the conductivity of the same. Thus configured, the PCM-based programmable vias provide such desirable advantages as, for example: spatial compactness, the elimination of a need for latches, multiple-shot reprogrammability, immunity from soft errors, and the elimination of the need for high voltage/current/power switching capability. Such advantages in turn provide improved function and lower costs in 3D applications. As will be further appreciated, the advantages of PCM programmable vias are not necessarily limited to 3DI structures, but rather the PCM programmable links may also be used in planar silicon environments so as to provide an alternative to FPGA.
As described in further detail, a PCM programmable via is formed within the metal layers of a semiconductor device, and may have a standard via cross section for the particular node (e.g., about 0.2 μm×0.2 μm). The PCM via material may be switched between resistive and conductive states by using an external heating element operated in a programmed heat cycle. The power requirement for switching of the PCM from a non-conductive, amorphous state to a conductive, crystalline state (and vice versa) is within available line voltage supplies. In addition, because the “on” and “off” impedances are suitable for direct interfacing with logic inputs, no latch devices are required. Furthermore, the PCM via structure may be reprogrammed a very large number of times (e.g., PCM memory elements test up to on the order of about 1011 cycles).
In one embodiment, the phase change material (PCM) is a ternary alloy of germanium (Ge), antimony (Sb) and tellurium (Te) (hereinafter referred to as “GST”), with an exemplary composition of Ge2Sb2Te5; however, other compositions such as GeSb4, (including substitution/addition of other elements) are also possible for the PCM. Table I below illustrates a comparison of resistivity, specific heat and thermal conductivity of various insulative, conductive and phase change materials associated with via level materials in a semiconductor device:
TABLE I
Resistivity, Specific Heat and Thermal
Conductivity of Key Materials
Material
ρ(Ω · cm)
Cp(J/(K · cm3)
K(J/(K · cm · sec))
SiO2
3
0.013
TaSiN
4 × 10−4
0.02
Ge2Sb2Te5
0.04 *
1.3
0.005
(crystalline)
Ge2Sb2Te5
8 × 103 *
1.3
0.0017
(amorphous)
GeSb4 (crystalline)
5 × 10−4
GeSb4 (amorphous)
1.0
* 12% N-doping
At room temperature (and up to moderately elevated temperatures), the PCM material is stable in two phases: a crystalline phase which is a moderately good conductor of electricity, and an amorphous phase which is insulating as shown in Table I. Thus, in the crystalline phase, the state of a PCM link is “on,” while in the amorphous phase the state is “off.” The phases are switched from one to another by one of two thermal cycling operations as illustrated in
As also indicated above, the ternary GST alloy is nitrogen doped in order to raise the crystallization temperature thereof, so that the material remains bistable at an operating temperature of approximately 85-95° C. In other words, it is undesirable for the GST alloy to be susceptible to phase change once programmed, where the circuit is operating at temperatures normally designed for.
Referring generally now to
As particularly shown in
In the first embodiment of
In most cases (except for a later embodiment presented hereinafter;
The insulating layer 910 on top of the transformable section of PCM 906 and between the input and output contacts is selected so as to have a low thermal conductivity (e.g., 0.002-0.007 J/(K·cm·sec)) for satisfactory operation. One suitable material in this regard is NBLOK (nitrogen doped silicon carbide).
For each of the above described embodiments, using both the geometry of the designs and the material properties shown in Table I, the “on” and “off” resistances of the embodiments may be estimated approximately, as shown in Table II below:
TABLE II
ON and OFF Resistances for different Design Configurations
Figure #
x, y, z in GexSbyTez
Ron (KΩ)
Roff (MΩ)
5
2, 2, 5*
2.2
8
6
2, 2, 5*
2.2
8
7
2, 2, 5*
2.0
16
8
2, 2, 5*
2.4
16
9
1, 4, 0
1.2
24
10
2, 2, 5*
2.0
>20
*12% N-doping
The above approximations further take into account a via square cross-ion section with dimension αvia=0.2 μm, a total via height hvia=0.2 μm, a thickness of transformable PCM layer, ttransf=4.0 nm or larger, and a spacing between vias dvia=0.2 μm.
The “on” and “off” resistance requirements are appreciated upon consideration of a logic configuration such as shown in
In evaluating the “off” link resistance, it is assumed that inverter outputs A and B are logically low, and that inverter output C is high. In this case, inverter 1104 is (through line D) driving two “off” PCM vias in parallel. This should be a light load in order to maintain CMOS functionality. It is also desirable for this path to draw as small a parasitic current as possible. The relatively high “off” resistances indicated in Table I should ensure these conditions adequately. Thus, the programmable via designs along with the chosen materials should be embeddable in CMOS logic without requiring additional latches. Timing studies may be performed in order to take into account the parasitic capacitance of the heater circuits, except for the embodiment of
Processing Operations
Referring once again to the programmable via structures of
In the embodiment of
In the embodiment of
In the embodiment of
In the embodiment of
In the embodiment of
Alternatively, tungsten only may be used in the contact vias, and the metal lines are fabricated by damascene processing, using copper. For example, the process flow for the embodiment of
Power Requirements
In the embodiments of
where the diffusion constant is
The solution for constant power W applied up to a switch-off time t0 is given by:
where ζ=z/√{square root over (4Dt)}, Tα is ambient temperature, and T0 is the temperature rise at switch-off. The temperature evolution at the surface z=0 is given by:
and rises as the square root of time. The power is given by:
where A is heater surface area in the xy-plane. Thermal properties of some of the key materials are given in Table I above.
Application of this formula to an area of 0.2×0.2 μm2 (αvia=0.2 μm), T0=700 C, and t0=2.0 ns, including the Table I parameters, gives (for heater powers into a semi-infinite medium): WG=0.35 mW for GST, WO=1.1 mW for SiO2 (the relative magnitudes of WG and WO track the KC product, which is much smaller for GST than for SiO2).
In considering the design of the
with τh=20 nm, and assuming Ch≈2 JK−1cm−3, gives τh=0.1 ns, which is very short compared with other times of interest. However, this will not necessarily be the case in all situations; 3D simulations confirm this fast equilibrium in a more realistic geometry. Estimated heat loss in the TaSiN 0.1 μm leads, with a maximum temperature drop of 700° C. along the length, would be about 60 μW per lead. However, in practice, the leads also heat up to nearly T0, making the heat loss from the leads relatively low compared with the heater power. Hence, an approximate analysis may be made based on treating the heater as a sheet source of power with uniform power per unit area.
Proceeding on this assumption, the heater powers emitted from each side of the heater strip are summed to obtain the total heater power. In the structure of
In the embodiment of
In the embodiment of
TABLE IIIa
Estimated Power requirements for 0.2 μm PCM Vias
Figure #
W (mW)
Rh (KΩ)
I(mA)
V (V)
5, 6
0.35 + 3 × 1.1 = 3.65
0.4
3.1
1.2
7
2 × 0.35 + 2 × 1.1 = 2.9
0.4
2.7
1.1
8
2 × 0.35 + 6 × 1.1 = 7.3
0.8
3.0
2.4
9
0.35 + 3 × 1.1 = 3.65
0.4
3.1
1.2
By way of comparison, the results shown in Table IIIb below are those corresponding to a via of width 0.1 μm and to a TaSiN heater composition with a resistivity about 10 times than indicated in Table I, with a PCM resistivity of about 0.25 times that in Table I to maintain the “on” and “off” impedances in Table II. Alternatively, retaining the Table I PCM material, the PCM portion of the via may be reduced in height to about 50 nm, and filling the remaining portion with conventional conductor material (e.g., tungsten), thus keeping the same “on” with a higher “off” resistance. These modified resistivity values lie within the range achievable by composition control.
TABLE IIIb
Estimated Power requirements for 0.1 μm PCM Vias
Figure #
W (mW)
Rh (KΩ)
I (mA)
V (V)
5, 6
0.91
4.0
0.48
1.9
7
0.73
4.0
0.43
1.7
8
1.82
8.0
0.48
3.8
9
0.91
4.0
0.48
1.9
The heater voltage may, in some cases, require the option of using the available I/O line power supplies (e.g., 2-3 V). Current is also a significant consideration because it controls the width of the driving FET, which is typically larger than the via itself. Here, the smaller via dimensions (Table IIIb), combined with a higher resistivity heater material, is advantageous in this respect to the larger vias used in Table IIIa.
In considering scaling at constant programming power supply voltage and at fixed technology, the power needed to drive a via of diameter α scales as α2, where for the current I (C=constant):
I=Cα2.
The drive output transistor width w is proportional to the current (B=constant):
w=BI,
hence
w=BCα2.
The transistor width is typically the controlling dimension of the device, w>>α, hence the total device dimension scales as α2. There is thus a strong motivation, based on minimizing total programmable via device area, to make the via as small as possible, since device dimension goes as its square. Individual designs will also need to be optimized to the precise line voltage, so as to minimize current and hence device dimension.
1D Numerical Simulation of RESET and SET Processes
For an analysis of the programming of the PCM vias, certain additional factors that are taken into account (in addition to heat diffusion) include latent heat of melting of the PCM, as well as the kinetics of the propagating front corresponding to the melt interface. This is done through a numerical approach for heat and melt front propagation within the GST layer. First a one-dimensional model of a basic melt front is described because of its mathematical simplicity. In the following subsection, three-dimensional simulations of two designs (
Including latent heat, conservation of energy modifies the diffusion equation for temperature T(z,t) in the GST (subscripts G refer to GST) to:
where fG(z,t) is the fraction of melt in the material, and LG is the latent heat per unit volume.
The equation for the melt fraction dynamics is based on modified Wilson-Frenkel kinetics, with friction described by the Vogel-Fulcher form appropriate for “fragile glasses,” and is given as:
where the melt front velocity V(T) is given by
in which V0 is a characteristic velocity, Eα is the activation energy for the transition from the amorphous to the crystalline phase, ΔSm is the melt entropy, Tm is the melt temperature, Tg is a “glass” temperature, and temperatures are measured from absolute zero. Only propagation of the melt front xm, not homogeneous nucleation, is taken into account, due to the relatively long nucleation time (μs even in thick films of some materials, though it may be faster in others) anticipated in nanometer-thickness films relative to the ns time scales of interest in RESET (a fast SET process is also assumed here, although time scales may be more extended in optimal engineering operation). In practice, numerical requirements dictate certain modifications to the basic procedure.
It will be noted that low temperature crystallization rates obey Arrhenius kinetics: A exp(−Elowa/kT), where Elowa is a low-temperature activation energy of order 2-3 eV. This analysis is an appropriate one for considering archival storage lifetime.
The boundary condition at the PCM surface for RESET is obtained from the approximate analysis of the previous subsection, the temperature profile being extended beyond the turn-off-time t0 using the shift theorem, to give a profile qualitatively like that in
In this equation, t0=tquenchoff and T0=Tquenchmax−Tα in the notation of Table IV, below.
The boundary condition at the PCM surface for SET is:
In this equation, t0=tannealhold and T0=Tannealhold−Tα in the notation of Table IV. The parameters in Table IV are partly based on an experimental study of laser-annealed spot crystallization kinetics in rotating PCM-coated disks. The maximum recrystallization front velocity is 2.2 m/s.
The results of the simulation with the foregoing parameters are shown in
TABLE IV
Main Parameters in 1D Simulation
Symbol
value
Explanation
V0
900
ms−1
Velocity prefactor
LPCM
50
nm
Thickness of PCM film
Tm
560°
C.
Melt temp.
Tquenchmax
868°
C.
Max. transient quench temp.
tquenchoff
2.0
ns
Current turn-off time in quench
Tannealhold
480°
C.
Hold temp. in anneal
tannealhold
0.58
ns
Time for commence of hold in anneal
L
120
Jcm−3
Latent heat of melting
Ea
15000
J/mole
Activation energy
Tg
85°
C.
Glass temperature
Ta
27°
C.
Ambient temperature
The latent heat is relatively low, and thus for approximation purposes, it may be neglected completely (though simulations have also been successfully implemented in which significant latent heat values have been included).
3D Simulation of PCM Melt, Quench, and Anneal
Three-dimensional simulations of PCM encased in oxide with a metal heater were run to determine the geometry and time scale for the melt, quench, and anneal processes. In particular, a snapshot from a simulation with a solid slab of heating material in the separating plane between two PCM+oxide composites (embodiment of
The physical constants introduced in the previous section were used, along with 3D versions of the equations, which are, in dimensionless form:
Here, φ=T/Tm, CV, K and L are the dimensionless specific heat, thermal conductivity, and latent heat of fusion, t and are dimensionless time and gradient, fG is the melt fraction, and V is the speed of the melt front:
The temperature is controlled by the time- and position-dependent heat input, H. The rate of change of fG at any point depends on the distance δ between that point and the nearest melt front surface. The width of the melt front is taken to be r0; φG=TG/Tm is the normalized glass transition temperature. Dimensionless constants V0, and
were determined from the physical constants given in the previous sections.
The calculation is straightforward using finite differences for the derivatives with a rectilinear grid of cells; φ and fG are cell-centered quantities. The melt front is defined by the central points of all the cell walls that straddle cell volumes where fG<0.5 and fG>0.5. The nearest distance δ between a cell position and the melt front is determined by first finding the three nearest points on the melt front. These three points define a plane and the perpendicular distance between the cell position and the plane is determined by vector trigonometry.
For both the slab and ring heater models, the PCM is on the inside of an oxide shell. The PCM outer dimensions are 100×100×131.25 nm3, while the outer dimensions of the oxide shell are 200×200×231.25 nm3. Smaller samples were also simulated; they show the same behavior but have shorter timescales for all the phase changes.
The temperature structure inside the model is much smoother than the melt structure, which has sharp fronts separating the different phases. To resolve fG without doing unnecessary calculations for φ, the simulation uses a fine grid for fG and a coarse grid for φ. For temperature, the simulations in the ring case use a grid measuring 32×32×37 cells with PCM in the central 16×16×21 cells. The heater measures 32×32×3 cells with the central 16×16×3 cut out and filled with PCM connected to the rest of the PCM. In the slab case, the heater bifurcates the PCM by occupying the horizontal midplane in 32×32×3 cells. In all cases, the PCM has a grid for melt fraction, fG, which is 4 times finer than the temperature grid.
The heating function H is taken to be a constant for three intervals of time. During the melting phase, H is large enough to make the peak temperature in the heating zone increase to about φ=1.5. In the quench phase, H=0, so the material returns to room temperature. In the anneal phase, H comes back on for 200 ns but with a value slightly smaller than in the melt phase, now making the peak φ equilibrate to around 0.98.
The simulations indicate that the PCM in our configurations develop melted holes in the center during the SET phase, thereby changing the electrical conductivity from top to bottom as required by the device. The PCM is quenched when the heating rate is dropped suddenly, and it anneals when the temperature is raised to just below the melting temperature.
The power required to melt the PCM in the ring simulation was 2.8 mW for a heater measuring 0.2×0.2×0.01875 cubic microns; the power for the slab simulation was slightly less, 1.9 mW, for the same dimensions. The slab required less power than the ring because the slab has a greater area in contact with the PCM.
Finally, the considerations for selection of an appropriate PCM are summarized below. As was alluded to previously, suitable PCM materials include not only Ge, Sb, and Te, but also other elements such as Ag, In, Sn, for example, as well as dopants such as N. Generally speaking, desirable PCM properties include archival stability at about 85°-95° C., which tends to improve with Ge content. In addition, crystallization front speed may be on the order of about V0<45 m/s (with maximum recrystallization velocity on the order of about <1.1 m/s acceptable), which correlates with low Sb content. The nucleation rate of the PCM should be low enough to avoid nucleation during quench (i.e., at high temperature), although the specific mechanism of recrystallization is of no particular concern for application (in contrast to a compact disk read/write (CDRW) application).
As indicated above, the “on”/“off” ratio is preferably high, while the “on” resistance (depending upon the particular structural embodiment) preferably utilizes a high conductance material such as GeSb4 (e.g.,
While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
Wordeman, Matthew R., Newns, Dennis M., Lam, Chung Hon, Elmegreen, Bruce G., Young, Albert M., Krusin-Elbaum, Lia
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