A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of c, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
|
1. A process of forming an electronic device comprising:
forming a doped semiconductor layer over a substrate, wherein the doped semiconductor layer includes a dopant and at least two other different elements selected from a group consisting of c, Si, and Ge; and
performing an action to reduce a dopant content at an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer, wherein:
performing the action includes exposing the doped semiconductor layer to a plasma, radiation having an emission maximum at a wavelength no greater than approximately 400 nm, an energy beam, or any combination thereof; and
performing the action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient.
13. A process of forming an electronic device comprising:
forming an in-situ doped semiconductor layer over a substrate, wherein:
forming the in-situ doped semiconductor layer comprises reacting a dopant-containing gas and a semiconductor-containing gas at a reaction temperature; and
as formed, a dopant concentration within the in-situ doped semiconductor layer is higher than a solid solubility of the in-situ doped semiconductor layer at the reaction temperature; and
performing an action to reduce a dopant content at an exposed surface of a workpiece that includes the substrate and the in-situ doped semiconductor layer, wherein performing the action is performed after forming the in-situ doped semiconductor layer and before the in-situ doped semiconductor layer is exposed to a room ambient.
9. A process of forming an electronic device comprising:
epitaxially growing a doped semiconductor layer from a substrate, wherein the doped semiconductor layer is substantially monocrystalline and includes a dopant;
disrupting a crystal pattern of the doped semiconductor layer adjacent to an exposed surface of the doped semiconductor layer; and
performing an action to reduce a dopant content at an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer, wherein:
performing the action includes exposing the doped semiconductor layer to a plasma, radiation having an emission maximum at a wavelength no greater than approximately 400 nm, an energy beam, or any combination thereof; and
performing the action is performed after disrupting the crystal pattern of the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient.
2. The process of
3. The process of
4. The process of
5. The process of
6. The process of
7. The process of
forming the doped semiconductor layer comprises forming an in-situ phosphorus doped semiconductor layer at a first temperature; and
performing the action is performed at a second temperature, wherein the second temperature is as least as high as the first temperature.
8. The process of
10. The process of
11. The process of
12. The process of
14. The process of
the first gas comprises SiaH(2a+2), wherein a is 1, 2, or 3;
the second gas comprises SibccH(2(b+c)+2), wherein a sum of b+c is 1, 2, or 3, and c is greater than 0; and
the third gas comprises PH3X3-d, wherein X is a halogen, and d is 0, 1, 2, or 3.
15. The process of
16. The process of
17. The process of
18. The process of
19. The process of
the process further comprises:
forming a gate electrode over the substrate; and
etching a portion of the substrate to form a trench adjacent to the gate electrode, wherein etching the portion of the substrate is performed before forming the in-situ doped semiconductor layer; and
forming the in-situ doped semiconductor layer comprises forming a semiconductor layer including silicon, carbon, and phosphorus.
|
1. Field of the Disclosure
The present disclosure relates to processes, and more particularly to processes of forming electronic devices including doped semiconductor layers.
2. Description of the Related Art
Electronic devices can include phosphorus-doped semiconductor layers. Some of the earliest semiconductor devices include pnp bipolar transistors. After forming a heavily-doped p-type collector region within a monocrystalline silicon substrate, an n-type silicon layer can be epitaxially grown from the substrate. The n-type silicon layer can be in-situ doped using phosphine when the dopant is phosphorus. The dopant concentration of the n-type silicon layer is much lower than the p-type dopant concentration within the collector region. For example, the n-type silicon layer may have 1E15 to 1E17 phosphorus atoms/cm3.
In the 1970s and early 1980s, polycrystalline and amorphous silicon gate processes replaced the older aluminum-gate processes when forming metal-oxide-semiconductor transistors. The polysilicon or amorphous silicon gates were typically n-type doped and could form buried contacts with the substrate. Before high-current ion implanters were used in commercial production, the polysilicon or amorphous silicon gates were formed by depositing an undoped silicon deposition and furnace doping or by depositing an in-situ doped silicon layer. Regarding the former, after depositing an undoped silicon layer (typically at a temperature in a range of 600 to 650° C. for polysilicon or 560° C. for amorphous silicon), the workpiece, including the undoped silicon layer, would be exposed to a phosphorus-containing gas, such as PH3/O2 or POCl3, at a temperature of 800 to 900° C., and then a dopant drive would be performed at a temperature of 1000 to 1150° C. Alternatively, a heavily doped phosphosilicate glass would be grown or deposited onto the undoped silicon layer, and then a dopant drive would be performed at a temperature of 1000 to 1150° C. The oxide (whether from the POCl3 reaction or the heavily doped phosphosilicate glass) would be stripped from the silicon layer and processing would be continued. Regarding the in-situ doping, the doping would be performed using phosphine at the deposition temperature. For both, the phosphorus concentration would not exceed the solid solubility limit of silicon at the silicon deposition temperature. Regardless of which process was used, the workpieces with the phosphorus-doped silicon layer would be cleaned, and a nitride layer would be deposited before performing a gate electrode etch.
High-current ion implanters have replaced many of the furnace doping operations. Many high-current implants allow doped regions and layers to be formed that typically do not exceed 5E20 phosphorus atoms/cm3. Unlike furnace doping, the highest concentration immediately after ion implantation is not at an uppermost surface of the silicon layer or substrate, but at a projected range, which is spaced apart from that uppermost surface.
Embodiments are illustrated by way of example and are not limited in the accompanying figures.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.
A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
Embodiments described herein are useful in reducing odors that may be emitted from doped semiconductor layers. By performing the action after the doped semiconductor layer is formed and before exposing the doped semiconductor layer to a room ambient, the dopant content along an exposed surface of a workpiece can be significantly reduced. The action reduces the likelihood that humans would detect a foul odor from the doped semiconductor layer. Thus, the environmental and safety concerns can be significantly reduced. While much of the disclosure focuses on phosphorus, the concepts described herein may be applicable to other dopants that would be present in doped semiconductor layers.
The inventors believe that the problems described herein may not have occurred in conventional processing sequences for various reasons. If the doped semiconductor layer would be used as part of an active base region, the dopant concentration would be no higher than 1E18 atoms/cm3, and thus, no significant phosphorus odor would have been detected by humans. If the doped semiconductor layer would be doped using POCl3 or a phosphosilicate glass, the temperature used for the dopant drive (1000 to 1100° C.) would likely reduce the phosphorus concentration at the surface, and thus, no significant phosphorus odor would be detected by humans. If the doped semiconductor layer would be doped by ion implantation, the dopant profile is characterized by a generally Gaussian distribution having a highest dopant concentration at the projected range, which is at a distance spaced apart from the exposed surface. Thus, at the exposed surface, the dopant concentration is low enough that phosphorus odors would not be detected by humans. Therefore, the inventors believe that odors have not typically been generated by doped semiconductor layers used to form electronic devices in a production environment due to various reasons, as previously described.
Before addressing details of embodiments described below, some terms are defined or clarified. The term “elevation” is intended to mean a shortest distance to a reference plane. In one embodiment, the reference plane is a primary surface of a substrate before forming any features overlying the substrate.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Other features and advantages of the invention will be apparent from the following detailed description, and from the claims. To the extent not described herein, many details regarding specific materials, processing acts, and circuits are conventional and may be found in textbooks and other sources within the semiconductor and microelectronic arts.
The doped semiconductor layer 12 can include silicon, carbon, germanium, or any combination thereof. The semiconductor compositions of the substrate 10 and the doped semiconductor layer 12 can include the same semiconductor material or different semiconductor materials. For example, the substrate 10 can include a substantially monocrystalline silicon material adjacent to the doped semiconductor layer 12, and the doped semiconductor layer 12 can include a carbon-doped silicon material or a germanium-doped silicon material. In another embodiment, the substrate 10 can include a germanium-doped silicon material, and the doped semiconductor layer 12 can include substantially monocrystalline silicon. Other combinations are possible.
The doped semiconductor layer 12 can include phosphorus at a concentration of at least approximately 1E20 atoms per cubic centimeter. In a particular embodiment, the doped semiconductor layer 12 has a concentration of at least 1E21 atoms per cubic centimeter and can be used as part of a source/drain region of a field-effect transistor, an emitter region of a bipolar transistor, another suitable heavily doped region within an electronic device, or any combination thereof. In a more particular embodiment, the dopant concentration is at least approximately 3E21 atoms per cubic centimeter.
In the embodiment illustrated in
The temperature used to form the doped semiconductor layer 12 can depend on the gases chosen. The temperature needs to be high enough to cause the gases to react (e.g., decompose, react with each other, or any combination thereof) and deposit over the substrate 10. The temperature used for the deposition increases as the number of semiconductor atoms within the molecule decrease and as the number of halogen substituents (for otherwise H atoms) within the molecule increases. Thus the temperature may be as low as approximately 200° C. to as high as approximately 1200° C. The temperature of the deposition may also be affected by when in the process the doped semiconductor layer 12 is formed. If the doped semiconductor layer 12 is formed relative later in the process (e.g., after forming a gate structure or an active base region), a lower temperature may be chosen to reduce adverse affects to other portions of the workpiece for reasons not directly related to the doped semiconductor layer 12 (e.g., undesired diffusion of a dopant within a previously-formed doped region within a workpiece). In one embodiment, the temperature may be no higher than approximately 550° C., and in a particular embodiment, is in a range of approximately 450° C. to approximately 520° C.
All other parameters (e.g., chamber pressure, actual flow rates of the gases, etc.) used in the formation of the doped semiconductor layer 12 are conventional or proprietary. If the doped semiconductor layer 12 is deposited over and not epitaxially grown from the substrate 10, the deposition may or may not be plasma assisted. When the doped semiconductor layer 12 is formed, all of the semiconductor-containing and phosphorus-containing gases are terminated at substantially the same time. In other embodiments, a substantially undoped semiconductor layer can be formed and subsequently furnace doped or ion implanted.
In the embodiment as illustrated in
To reduce the phosphorus odor from the doped semiconductor layer 12, an action is performed after the doped semiconductor layer 12 is formed and before exposing the workpiece, including the doped semiconductor layer 12 and the substrate 10, to a room ambient. By performing the action, the phosphorus content at an exposed surface of the semiconductor layer can be reduced such that it cannot be detected by humans. Thus, the likelihood of an emergency evacuation due to the phosphorus odor is substantially eliminated. If desired, a growth interruption can occur between forming the doped semiconductor layer 12 and performing the action. For example, the doped semiconductor layer 12 can be formed by epitaxially growing the doped semiconductor layer 12, and the growth interruption can include disrupting the crystal pattern at the exposed surface of the doped semiconductor layer 12 before performing the action.
The action can include forming an encapsulating layer (
In one embodiment, the action includes forming an encapsulating layer 22 over the doped semiconductor layer 12, as illustrated in
In another embodiment, the action includes exposing the surface of the doped semiconductor layer 12 to a plasma, radiation, an energy beam, or any combination thereof, as illustrated by serpentine lines 32 in
In one embodiment, a plasma is used. The plasma can be an ionized gas directly exposed to the surface of the doped semiconductor layer or a downstream plasma including neutral (i.e., uncharged) species. A species in the plasma can include noble atoms (He, Ne, Ar, Xe, Rn), hydrogen atoms, oxygen atoms, nitrogen atoms, halogen atoms (F, Cl, Br, etc.), or any combination thereof. The doped semiconductor layer 12 may be directly exposed to ions in the plasma or may be exposed to an effluent from a plasma generator (i.e., a downstream plasma). Plasma processing can be performed at a significantly lower temperature than exposure to electromagnetic radiation or an energy beam. If charge build-up with a plasma is a concern, an electron flood may be used to neutralize the charge on the workpiece before it is removed from the chamber.
If a downstream plasma is used, reactive neutral species may exit the plasma generator and, by themselves or in conjunction with another species, can remove phosphorus from the surface of the doped semiconductor layer 12. In a particular embodiment, hydrogen gas is introduced into a plasma generator and produces an effluent including neutral hydrogen atoms. NF3 can be combined with the neutral hydrogen atoms to produce a N—H—F compound that can be used to remove phosphorus near the surface of the doped semiconductor layer. In another particular embodiment, a hydrogen halide (e.g., HCl, HBr, etc.) can be used with a downstream plasma to produce neutral hydrogen and halogen atoms. The halogen atoms can replace phosphorus atoms in the Si—P bonds to form Si—X bonds (where X is a halogen), which can passivate the exposed surface. The hydrogen atoms can react with the free (i.e., not chemically bonded) phosphorus or from a Si—P bond, to form PH3, which can be removed as a gas. After reading this specification, skilled artisans will appreciate that many other embodiments are possible.
The actual conditions used for the plasma processing can depend on what structures or layers are exposed at the time of the plasma processing. For example, if an oxide or nitride material is present and is not to be removed, the chemistry and other plasma parameters can be adjusted to allow sufficient selectivity so that the phosphorus concentration is reduced without significantly adversely affecting the oxide or nitride material. Skilled artisans appreciate that some erosion of the oxide or nitride material may be tolerated, and after reading this specification can select the actual conditions depending on the particular application.
In another embodiment, the doped semiconductor layer 14 can be exposed to energy that includes electromagnetic radiation. The energy source for the electromagnetic radiation can be lamp-based or laser-based, monochromatic or broadband. In one embodiment, the electromagnetic radiation is sufficient energy to break Si—P bonds, P—P bonds, or a combination thereof. In one embodiment, the emission maximum is at a wavelength greater than approximately 700 nm. In another embodiment, heat may be a concern, and therefore, the wavelength can be less than approximately 400 nm. The emission maximum may be at least approximately 200 nm to reduce the likelihood that the radiation would pass through quartz walls if a quartz liner was used within the chamber. The electromagnetic radiation is exposed at a dose and total exposure time to significantly reduce the phosphorus odor from the doped semiconductor layer 12.
In one embodiment, a flood exposure of the doped semiconductor layer 12 can be used, and in another embodiment, a selective exposure using a radiation beam (e.g., from a laser) can be used. The electromagnetic radiation can be continuous during the exposure or can be pulsed. Pulsing the energy source is useful if the dose and total exposure time of the electromagnetic radiation would heat the locally exposed portion of the doped semiconductor layer 12 above the temperature used to form the semiconductor material within the doped semiconductor layer 12. For example, if the doped semiconductor layer 12 is formed at a temperature of approximately 500° C., the local temperature of the doped semiconductor layer 12 (portion exposed to the electromagnetic radiation) should not be higher than approximately 500° C. Pulsing allows the workpiece to cool between pulses to better control the local temperature.
In another embodiment, the energy can come from an energy source that emits an energy beam of electrons or ions. The doped semiconductor layer 12 is exposed to the energy beam at a dose and total exposure time to significantly reduce the phosphorus odor from the doped semiconductor layer 12. The energy beam can be continuous on during the exposure or can be pulsed. Pulsing the energy source is useful if the dose and total exposure time of the electron beam would heat the locally exposed portion of the doped semiconductor layer 12 above the temperature used to form the semiconductor material within the doped semiconductor layer 12. Pulsing allows the workpiece to cool between pulses to better control the local temperature.
In still another embodiment, the workpiece including the doped semiconductor layer 12 can be annealed, as illustrated in
In an alternative embodiment, a combination of the actions may be performed. In one embodiment, neutral hydrogen atoms can be obtained from a downstream plasma and fed into an annealing chamber where the workpiece, including the doped semiconductor layer 12, is located. In another embodiment, the anneal can be performed with a reactive species that forms an encapsulating layer similar to encapsulating layer 22, as illustrated in
After the action has been performed, the amount of phosphorus odor from the doped semiconductor layer 12 is sufficiently low that phosphorus would not be detected by humans. At this time, the workpiece including the doped semiconductor layer 12 can be exposed to the room ambient. If desired, a wet clean after the action helps to reduce further the phosphorus content at the surface of the doped semiconductor layer 12.
The concepts described herein will be further described in the following Example, which does not limit the scope of the claims. The Example demonstrates that an action is performed after forming a doped semiconductor layer and can reduce the phosphorus odor from the doped semiconductor layer before the doped semiconductor layer is exposed to a human within the room ambient. More particularly,
The gate electrode 524 is formed from a gate electrode layer which may include a semiconductor-containing film, a metal-containing film, or any combination thereof. In one embodiment, the gate electrode layer includes polysilicon or amorphous silicon. In another embodiment, the gate electrode layer may include one or more other materials. In a particular embodiment, the thickness of gate electrode layer is not greater than approximately 200 nm, and in another particular embodiment is no greater than 90 nm. In yet another embodiment, the thickness of gate electrode layer is at least approximately 20 nm, and in another particular embodiment is at least 50 nm. In a finished device, the gate electrode layer can have a dopant concentration of at least 1E19 atoms/cm3 when gate electrode layer includes polysilicon or amorphous silicon. The gate electrode layer can be deposited by chemical vapor deposition, physical vapor deposition, or a combination thereof using a conventional or proprietary technique.
A capping layer 526 overlies the gate electrode layer. The capping layer 526 can protect the gate electrode layer during subsequent processing, be an anti-reflective coating, perform another suitable function, or any combination thereof. The capping layer 526 can include an oxide, a nitride, an oxynitride, or any combination thereof. The capping layer 526 has a thickness as described with respect to the thicknesses for the gate electrode layer. The capping layer 526 can have the same or different thickness as the gate electrode layer. The capping layer 526 can be thermally grown or deposited using a conventional or proprietary technique.
The capping layer 526 and the gate electrode layer are patterned to form the gate structure 52 that includes the gate electrode 524. The gate dielectric layer 522 can be patterned when patterning the capping layer 526 and the gate electrode layer, or portions (not illustrated) of the gate dielectric layer 522 (not covered by the gate electrode 524) can be removed at a later time. The patterning to define the sides of the gate structure 52 is performed using a conventional or proprietary lithographic and etch operation.
Exposed portions of the gate substrate 50 and gate electrode 524 are thermally oxidized to form oxide layers 542 and 544. Alternatively, a thin layer oxide (not illustrated) can be deposited over exposed portions of the workpiece, including the substrate 50 and gate structure 52. Extension regions 562 are formed within the substrate 50. The extension regions 562 are p-type doped or n-type doped, depending on the type of transistor being formed. For an n-channel transistor, the extension regions 562 are n-type doped. The doping concentration can be in a range of approximately 1E15 to approximately 1E18 atoms/cm3. The extension regions 562 are formed using a conventional or proprietary ion implantation process. A spacer 546 is formed adjacent to the sides of the gate structure 52. The spacer 546 can be formed by depositing a nitride layer and anisotropically etching the nitride layer using a conventional or proprietary process.
Portions of the substrate 50 not covered by the gate structure 52 or the spacer 546 are etched to form trenches 662, as illustrated in
The doped semiconductor layer 762 can be formed by epitaxially growing or depositing a semiconductor material previously described with respect to the doped semiconductor layer 12. The doped semiconductor layer 762 can be selectively formed such that it is formed only within the trenches 662, and not overlying the capping layer 526 and the spacer 546. If the doped semiconductor layer 762 is not to be formed within areas including p-channel transistors, existing insulating layers or an additional insulating layer can be formed over those areas.
The temperature at which the doped semiconductor layer 762 is formed can be limited by processing considerations not directly related to the formation of the doped semiconductor layer 762. For example, the extension regions 562 are not to be significantly diffused any further. Thus, the doped semiconductor layer 762 may be formed at a temperature no greater than 650° C. In a more particular embodiment, the doped semiconductor layer 762 is formed at a temperature no greater than approximately 550° C., at a temperature in a range of approximately 450° C. to approximately 520° C., or at another temperature. The semiconductor-containing gases can include any of the gases previously described with respect to the doped semiconductor layer 12. In one particular environment, the semiconductor gases can include SiH4 and SiH3CH3.
The doped semiconductor layer 762 can be in-situ doped or subsequently doped with an n-type dopant. If in-situ doped, a phosphorus-containing gas can be included with the semiconductor-containing gases. In a particular embodiment, the phosphorus containing gases can include PH3. When the doped semiconductor layer 762 is in-situ doped, the resulting dopant concentration within the doped semiconductor layer 762 can be substantially uniform. If the doped semiconductor layer 762 is subsequently doped, an appropriate dopant can be introduced within a furnace or ion implanted using an appropriate species. An activation cycle can be used to activate the dopant.
When the phosphorus content within the doped semiconductor layer 762 is very high (at least approximately 1E20 atoms/cm3), the doped semiconductor layer 762 could emit a phosphorus odor that would be detected by humans if the workpiece would be exposed to a room ambient. Thus, an action is performed to reduce or substantially eliminate the likelihood that the workpiece would emit a phosphorus odor that would be detected by humans. The action performed can be any of the actions previously described to reduce phosphorus odor from the doped semiconductor layer 12. For example, the action can include forming an encapsulating layer, exposing the doped semiconductor layer 762 to radiation, annealing the doped semiconductor layer 762, or any combination thereof. The action will be performed before the workpiece is exposed to a room ambient.
In an embodiment illustrated in
The workpiece is further processed to form silicide regions 926 and 962, as illustrated in
Conductive plugs 1062 and conductive lines 1162 are then formed. Other conductive plugs and conductive lines are formed but are not illustrated in
In one embodiment, the conductive plugs 1062 are formed before the conductive lines 1162. In one particular embodiment, a conductive layer (not illustrated) is formed over interlevel dielectric layer 102 and substantially fills contact openings therein. Portions of the conductive layer that lie outside the contact openings are removed to form the conductive plugs 1062. A conventional or proprietary chemical-mechanical polishing operation or a conventional or proprietary etching process can be performed.
An insulating layer 112 is then deposited and patterned to form interconnect trenches where the conductive lines 1162 are formed. The insulating layer 112 can include any of the materials previously described with respect to the interlevel dielectric layer 102. The insulating layer 112 can have the same or different composition as compared to the interlevel dielectric layer. Other interconnect trenches can be formed at locations but are not illustrated. In one embodiment, another conductive layer is formed over the interlevel dielectric layer 102 and substantially fills the interconnect trenches in the insulating layer 112. Portions of the conductive layer that lie outside the interconnect trenches within the insulating layer are removed to form the conductive lines 1162. In one embodiment, a conventional or proprietary chemical-mechanical polishing operation can be performed, and in another embodiment, a conventional or proprietary etching process can be performed. The insulating layer 112 lies at substantially the same elevation as and between the conductive lines 1162 and other conductive lines that are not illustrated. In another embodiment (not illustrated), the conductive plugs 1062 and the conductive lines 1162 are formed concurrently using a conventional or proprietary dual-inlaid process.
In another embodiment (not illustrated), additional insulating and conductive layers can be formed and patterned to form one or more additional levels of interconnects. After the last interconnect level has been formed, an encapsulating layer 122 is formed. The encapsulating layer 122 can include one or more insulating film, such as an oxide, a nitride, an oxynitride, or a combination thereof.
Embodiments described herein are useful in reducing odors that may be emitted from doped semiconductor layers. An action is performed before the doped semiconductor layer is exposed to humans to reduce the likelihood that humans would detect a foul odor from the doped semiconductor layer. Thus, the environmental and safety concerns can be significantly reduced. While much of the disclosure has focused on phosphorus, the concepts described herein may be applicable to other dopants that would be present in doped semiconductor layers.
Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that those aspects and embodiments are only illustrative and do not limit the scope of the present invention.
In a first aspect, a process of forming an electronic device can include forming a doped semiconductor layer over a substrate, wherein the doped semiconductor layer includes a dopant and at least two other different elements selected from a group consisting of C, Si, and Ge. The process can also include performing an action to reduce a dopant content at an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer, wherein performing the action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient.
In one embodiment of the first aspect, forming a doped semiconductor layer includes forming a doped semiconductor layer including carbon. In a particular embodiment, forming a doped semiconductor layer includes forming an in-situ, phosphorus doped semiconductor layer. In another particular embodiment, the process further includes etching a semiconductor material within a substrate to form a trench within the substrate, wherein forming the doped semiconductor layer includes forming the doped semiconductor layer within the trench. In a more particular embodiment, the process further includes forming a gate structure over the substrate before etching the semiconductor material.
In an even more particular embodiment, forming the doped semiconductor layer includes forming an in-situ phosphorus doped semiconductor layer at a first temperature, and performing the action is performed at a second temperature, wherein the second temperature is as least as high as the first temperature. In still an even more particular embodiment, performing the action includes annealing the doped semiconductor layer at a temperature of at least approximately 650° C. In another even more particular embodiment, performing the action includes forming a layer over the doped semiconductor layer.
In a second aspect, a process of forming an electronic device can includes epitaxially growing a doped semiconductor layer from a substrate, wherein the doped semiconductor layer is substantially monocrystalline and includes a dopant. The process can also include disrupting a crystal pattern of the doped semiconductor layer adjacent to an exposed surface of the doped semiconductor layer. The process can still also include performing an action to reduce a dopant content at an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer, wherein performing the action is performed after disrupting the crystal pattern of the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient.
In one embodiment of the second aspect, performing the action includes annealing the doped semiconductor layer. In a particular embodiment, annealing the doped semiconductor layer is performed using a gas including H2, a halogen-containing gas, or any combination thereof. In another embodiment, performing the action includes forming another layer over the doped semiconductor layer. In still another embodiment, performing the action includes exposing the doped semiconductor layer to a plasma, radiation having an emission maximum at a wavelength no greater than approximately 400 nm, an energy beam, or any combination thereof.
In a third aspect, a process of forming an electronic device can include forming an in-situ doped semiconductor layer over a substrate. Forming the in-situ doped semiconductor layer includes reacting a dopant-containing gas and a semiconductor-containing gas at a reaction temperature, and as formed, a dopant concentration within the in-situ doped semiconductor layer is higher than a solid solubility of the in-situ doped semiconductor layer at the reaction temperature. The process also includes performing an action to reduce a dopant content at an exposed surface of a workpiece that includes the substrate and the in-situ doped semiconductor layer, wherein performing the action is performed after forming the in-situ doped semiconductor layer and before the in-situ doped semiconductor layer is exposed to a room ambient.
In one embodiment of the third aspect, the process further includes introducing a first gas, a second gas, and a third gas into a chamber, wherein the first gas includes SiaH(2a+2), wherein a is 1, 2, or 3; the second gas includes SibCcH(2(b+c)+2), wherein a sum of b+c is 1, 2, or 3, and c is greater than 0; and the third gas includes PH3X3-d, wherein X is a halogen, and d is 0, 1, 2, or 3. In a particular embodiment, the first gas is SiH4, the second gas is SiH3CH3, and the third gas is PH3. In another particular embodiment, the process further includes forming a gate electrode over the substrate, and etching a portion of the substrate to form a trench adjacent to the gate electrode, wherein forming an in-situ doped semiconductor layer is performed after forming the trench. The in-situ doped semiconductor layer includes forming a semiconductor layer including silicon, carbon, and phosphorus. In a more particular embodiment, performing the action includes annealing the in-situ doped semiconductor layer at a temperature of at least approximately 650° C.
In another embodiment of the third aspect, performing the action includes forming another layer over the in-situ doped semiconductor layer. In still another embodiment, as formed, the dopant concentration within the in-situ doped semiconductor layer is at least 1E21 atoms/cm3.
Note that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which they are performed.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.
Many other embodiments may be apparent to those of skill in the art upon reviewing the disclosure. Other embodiments may be used or derived from the disclosure, such that a structural substitution, logical substitution, or another change may be made without departing from the scope of the disclosure. Although specific embodiments have been illustrated and described herein, it should be appreciated that any subsequent arrangement designed to achieve the same or similar purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the description. It is to be appreciated that certain features are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges includes each and every value within that range.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover any and all such modifications, enhancements, and other embodiments that fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Nguyen, Bich-Yen, Zollner, Stefan
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
6492216, | Feb 07 2002 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
6537369, | Mar 27 2000 | Pannova Semic, LLC | SiGeC semiconductor crystal and production method thereof |
6621131, | Nov 01 2001 | Intel Corporation | Semiconductor transistor having a stressed channel |
7029980, | Sep 25 2003 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method of manufacturing SOI template layer |
7183576, | Apr 20 2001 | GLOBALFOUNDRIES Inc | Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD |
20020011617, | |||
20030201461, | |||
20080224218, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 22 2007 | ZOLLNER, STEFAN | Freescale Semiconductor, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019698 | /0639 | |
Aug 02 2007 | NGUYEN, BICH-YEN | Freescale Semiconductor, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019698 | /0639 | |
Aug 08 2007 | Freescale Semiconductor, Inc. | (assignment on the face of the patent) | / | |||
Oct 25 2007 | Freescale Semiconductor, Inc | CITIBANK, N A | SECURITY AGREEMENT | 020518 | /0215 | |
Oct 30 2009 | Freescale Semiconductor, Inc | CITIBANK, N A | SECURITY AGREEMENT | 023882 | /0834 | |
Apr 13 2010 | Freescale Semiconductor, Inc | CITIBANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 024397 | /0001 | |
May 21 2013 | Freescale Semiconductor, Inc | CITIBANK, N A , AS NOTES COLLATERAL AGENT | SECURITY AGREEMENT | 030633 | /0424 | |
Nov 01 2013 | Freescale Semiconductor, Inc | CITIBANK, N A , AS NOTES COLLATERAL AGENT | SECURITY AGREEMENT | 031591 | /0266 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 053547 | /0421 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 053547 | /0421 | |
Dec 07 2015 | CITIBANK, N A , AS COLLATERAL AGENT | Freescale Semiconductor, Inc | PATENT RELEASE | 037354 | /0704 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 037486 | /0517 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051029 | /0387 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 042985 | /0001 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | SECURITY AGREEMENT SUPPLEMENT | 038017 | /0058 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051145 | /0184 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051029 | /0387 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051029 | /0001 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 039361 | /0212 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051029 | /0001 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 042762 | /0145 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051030 | /0001 | |
Feb 18 2016 | NXP B V | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145 ASSIGNOR S HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT | 051145 | /0184 | |
May 25 2016 | Freescale Semiconductor, Inc | MORGAN STANLEY SENIOR FUNDING, INC | SUPPLEMENT TO THE SECURITY AGREEMENT | 039138 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052915 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052915 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 040928 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052917 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V , F K A FREESCALE SEMICONDUCTOR, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 040925 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052917 | /0001 | |
Nov 07 2016 | Freescale Semiconductor, Inc | NXP USA, INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 040632 | /0001 | |
Nov 07 2016 | Freescale Semiconductor Inc | NXP USA, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001 ASSIGNOR S HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME | 044209 | /0047 | |
Sep 03 2019 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 050744 | /0097 |
Date | Maintenance Fee Events |
Jul 16 2009 | ASPN: Payor Number Assigned. |
Jan 14 2013 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Dec 13 2016 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Mar 01 2021 | REM: Maintenance Fee Reminder Mailed. |
Aug 16 2021 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
Jul 14 2012 | 4 years fee payment window open |
Jan 14 2013 | 6 months grace period start (w surcharge) |
Jul 14 2013 | patent expiry (for year 4) |
Jul 14 2015 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jul 14 2016 | 8 years fee payment window open |
Jan 14 2017 | 6 months grace period start (w surcharge) |
Jul 14 2017 | patent expiry (for year 8) |
Jul 14 2019 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jul 14 2020 | 12 years fee payment window open |
Jan 14 2021 | 6 months grace period start (w surcharge) |
Jul 14 2021 | patent expiry (for year 12) |
Jul 14 2023 | 2 years to revive unintentionally abandoned end. (for year 12) |