A memory system circuit and method therefor are included. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.
|
1. An indication circuit in a memory system within which a clock signal and a complement of the clock signal are generated, the clock signal of the type in which a series of regular pulses in voltage level of the clock signal are preceded by a preamble period having a beginning and an end, a transition in the clock signal from an indeterminate logic level to a selected one of a high logic level and a low logic level occurring at the beginning of the preamble period, a transition in the complement of the clock signal from the indeterminate logic level to the other of the logic levels occurring at the beginning of the preamble period, the circuit comprising:
a first comparator having first and second inputs, said first comparator for detecting, when said clock signal and a first reference voltage are received at said first and second inputs of the first comparator respectively, a change in polarity of a voltage difference between the voltage of said clock signal and said first reference voltage;
a second comparator having first and second inputs, said second comparator for detecting, when said complement of the clock signal and a second reference voltage are received at said first and second inputs of the second comparator respectively, a change in polarity of a voltage difference between the voltage of the complement of the clock signal and said second reference voltage; and
logic circuitry for generating indication, by way of an output signal of said logic circuitry transitioning to an active logic level, that said beginning of the preamble period has occurred, said indication generated when the transitions in the clock signals are detected,
wherein the output signal is asserted when at the active logic level.
2. The indication circuit as claimed in
3. The indication circuit as claimed in
4. The indication circuit as claimed in
5. The indication circuit as claimed in
6. The indication circuit as claimed in
|
Microelectronics circuits include a variety of different circuit components, and one type of circuit component that is often found in these circuits is a comparator. The comparator is a circuit element with two inputs labeled positive and negative and one output. The output goes either high or low depending upon which input is greater.
As will be appreciated by those skilled in the art, the signals being received by comparators are often noisy. When the input voltage of the received signal is close to the threshold voltage of the comparator, one potential problem is that a small amount of noise can make the voltage at the input rapidly fluctuate to values just above or just below the threshold voltage for the comparator. This can cause output “glitches” that may cause instability in the larger circuit, perhaps a control circuit, for example, that is impacted by the output of the comparator.
Existing solutions outside of the field of memory systems include solutions that employ a Schmidt Trigger. In this regard, one skilled in the art will appreciate that a Schmidt Trigger makes use of feedback, so that the current output state essentially “reinforces” the input value. For instance, if the output state is currently logic “high” (logic ‘1’) there will not be an output transition to logic “low” (logic ‘0’) unless the input voltage drops substantially below a low threshold voltage. Conversely, if the output state is currently logic ‘0’, there will not be an output transition to logic ‘1’ unless the input voltage rises substantially above a high threshold voltage. The difference in the two threshold voltages can be referred to as the hysteresis voltage.
A problem with Schmidt Triggers is that they are not designed to work in memory systems, and therefore the principles of hysteresis have apparently not previously been applied in the context of providing incorrupted strobe signals within a memory system.
It is an object of the invention to provide an improved memory system.
According to one aspect of the invention, there is provided a method for preamble detection within a microelectronics system. The method includes the step of receiving a clock signal of the type in which a series of regular pulses in voltage level of the clock signal are preceded by a preamble period having a beginning and an end. A transition in the clock signal from an indeterminate logic level to a selected one of a high logic level and a low logic level occurs at the beginning of the preamble period. The method also includes the step of receiving a complement of the clock signal. A transition in the complement of the clock signal from the indeterminate logic level to the other of the logic levels occurs at the beginning of the preamble period. The method also includes the step of generating indication that the beginning of the preamble period has occurred by: i) detecting the transition in the clock signal based on when the voltage level of the clock signal crosses through a first threshold of a voltage range; and ii) detecting the transition in the complement of the clock signal based on when the voltage level of the complement of the clock signal crosses through a second threshold of the voltage range.
According to another aspect of the invention, there is provided an indication circuit in a memory system within which a clock signal and a complement of the clock signal are generated. The clock signal is of the type in which a series of regular pulses in voltage level of the clock signal are preceded by a preamble period having a beginning and an end. A transition in the clock signal from an indeterminate logic level to a selected one of a high logic level and a low logic level occurs at the beginning of the preamble period. A transition in the complement of the clock signal from the indeterminate logic level to the other of the logic levels occurs at the beginning of the preamble period. The circuit includes a first comparator having first and second inputs. The first comparator is adapted to detect, when the clock signal and a first reference voltage are received at the first and second inputs of the first comparator respectively, a change in polarity of a voltage difference between the voltage of the clock signal and the first reference voltage. A second comparator has first and second inputs. The second comparator is adapted to detect, when the complement of the clock signal and a second reference voltage are received at the first and second inputs of the second comparator respectively, a change in polarity of a voltage difference between the voltage of the complement of the clock signal and the second reference voltage. The circuit also includes logic circuitry for generating indication, by way of an output signal of the logic circuitry transitioning to an active logic level, that the beginning of the preamble period has occurred. The indication is generated when the transitions in the clock signals are detected.
According to yet another aspect of the invention, there is provided a memory controller circuit for detecting a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. A signal from the output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the data timing signal and the reference voltage. The reference voltage is sufficiently close to the one of the logic levels, whereby at least substantial prevention of potential false positive detections is achieved.
Thus, improved signal transition detection circuits for memory systems have been provided.
Reference will now be made, by way of example, to the accompanying drawings:
Similar or the same reference numerals may have been used in different figures to denote similar components.
Referring now to the drawings,
As will be appreciated by those skilled in the art, DQS is a special clock signal, which is, in turn, a type of data timing signal. Also, DQS is employed in read and write operations. Partly in keeping with a typical clock signal, DQS is a sequence of electronic pulses for a portion of a read or write operation; however at other times when a read or write operation is not occurring, DQS is in high-impedance and at an indeterminate logic level (in between logic ‘1’ and logic ‘0’). In a write operation, DQS is generated synchronously with the write data by the memory controller 20, and also DQ for the write operation will be inputted, in some examples, to a suitable buffer in anticipation of being stored in a manner understood by those skilled in the art, in particular, in a data latch with the rising and falling edges of DQS. In a read operation, DQS and read data from the DDR SDRAM 22 are generated synchronously by the memory and, as will be appreciated by those skilled in the art, DQ for the read operation will, in some examples, be inputted to a suitable buffer in anticipation of being stored in a data latch with the rising and falling edges of DQS.
Before continuing with the present description of the SDRAM device 10, it should be noted that the memory controller 20 and the DDR SDRAM 22 comprise many individual circuits and components for carrying out their respective functions. Because one skilled in the art need not have an understanding of how to design or modify all components of the memory controller 20 and the DDR SDRAM 22 in order to obtain the benefits of the teachings disclosed herein, it will be understood that only relevant circuits and components are shown and described in detail.
With reference now to the memory controller 20 of
Reference will now be made to
For the purposes of the present discussion, it is fitting to divide the activity in the DQS waveform into five periods of time. During a first period of time, T1, DQS is in high-impedance. The next period is the preamble period labeled in
After T3 is the postamble period labeled in
Thus, for periods of time before and after a read operation, DQS will be in high-impedance. As mentioned, the voltage assigned to the state corresponding to high-impedance is roughly mid-level between logic ‘1’ and logic ‘0’; however in actual implementations the voltage of DQS (and the signal output of, for example, any comparator with mid-level voltage threshold that buffers DQS) will fluctuate significant above and below the aforementioned mid-level voltage. Ensuring that the signal fluctuations do not cause anomalous behavior, such as, for example, erroneous reading of DQ when data is not available, is known to be problematic.
Reference will now be made to
The PHY 302 is divided into a number of byte lanes in a manner known to those skilled in the art. In particular, the illustrated PHY 302 is divided into a byte lane 304 for I/Os, a byte lane 308 for Interface Timing Modules (ITMs), and a byte lane 312 for PLL(s). Conveniently, the illustrated byte lanes 304 and 308 are further divided into tileable cells (two of which are labeled 316 in
The illustrated enable circuit 32 includes a preamble indication circuit 326, DQS enable logic circuitry 330, DQS disable First In First Out (FIFO) circuitry 332, multiplexing circuitry 334, multiplexing circuitry 338, and the comparators 340 and 344. Input signals to the enable circuit 32 include a DQS signal, a DQS# signal, a write_data signal, a write_enable signal, and a system clock. Output signals from the enable circuit 32 include an output signal of the multiplexing circuitry 334, and an output signal of the multiplexing circuitry 338.
Reference will now be made to the preamble indication circuit 326. The indication circuit 326 includes comparators 350 and 354 and an AND logic gate 356 (with inversion at one of the gate inputs). The non-inverting and inverting inputs of the comparator 350 are electrically connected to, respectively, DQS and a lower threshold VIL of a voltage range. The non-inverting and inverting inputs of the comparator 354 are electrically connected to, respectively, DQS# and an upper threshold VIH of the VIL-VIH voltage range. The output of the comparator 350 is electrically connected to the input of the AND logic gate 356 with preceding inversion. The output of the comparator 354 is electrically connected to the other input of the AND logic gate 356. The output of the AND logic gate 356 is electrically connected to the enable logic circuitry 330.
The operation of the preamble indication circuit 326 during the DQS preamble period (period T2 in
Now with reference to time t1, which corresponds to a transition moment in time from the high-impedance period to the preamble period, it will be seen that the voltage of DQS begins falling towards logic low, and the voltage of DQS# begins rising towards logic high. As the voltage of DQS begins falling towards logic low, DQS subsequently crosses through voltage VIL (at time t2 in the illustrated example). Thus the DQS transition is detected, and in response output signal DL of the comparator 350 changes from logic high to logic low as indicated by transition arrow 402.
While the voltage of DQS begins falling towards logic low at time t1, the voltage of DQS# begins rising towards logic high at this time. DQS# then crosses through voltage VIH (at time t2 in the illustrated example). Thus the DQS# transition is detected, and in response output signal DH of the comparator 354 changes from logic low to logic high as indicated by transition arrow 406. Thus signals at logic levels necessary for producing logic high on output signal PI (output of the AND logic gate 356) are received at the inputs of the AND logic gate 356. Namely, logic low is received at the input with preceding inversion, and logic high is received at the other input. At logic high, the output signal PI provides indication that the preamble period has occurred as explained below. (It will be understood that example embodiments are not limited to those specific examples where the preamble indication is low-to-high logic level transition.)
In the illustrated example, the output signal PI is received by the DQS enable logic circuitry 330. Output 360 of the enable logic circuitry 330 is electrically connected to the selection inputs of the multiplexing circuitries 334 and 338, and thus a change in the output 360 on the next clock edge, that is brought about by preamble indication received from the preamble indication circuit 326, results in differential DQS-DQS# signals from the comparators 340 and 344 being selectively passed through the multiplexing circuitries 334 and 338 respectively.
In addition to being controlled in part by the output of the preamble indication circuit 326, the enable logic circuitry 330 is, in at least one example, also controlled in part by the output of the disable FIFO circuitry 332, which is in turn controlled in part by input signals ‘write_data’ and ‘write_enable’. ‘write_data’ defines the write data bit, and ‘write_enable’ causes the output buffer to be turned on when the signal is at an active logic level.
With respect to a first differential DQS signal passed through the multiplexing circuitry 334, delay circuit 364 (a DLL, for example) phase shifts the first differential DQS for proper alignment with DQ. In the illustrated example, the delay circuit 364 includes a slave DLL. In this regard, it will be understood that, for any slave DLL in a memory controller, there will exist a corresponding master DLL also within that memory controller. The master DLL derives a 0° clock which is phase locked to the main clock, and also 90°, 180°, and 270° phases. The slave DLL creates a constant 90° phase shift.
Phase shifted by the delay circuit 364, the first delayed differential DQS is made available along an electrical path 366, with a driver 368 facilitating this as understood by those skilled in the art. The clock input of a latch 370 (a D flip-flop in the illustrated example) is electrically connected to the path 366 to receive the delayed differential DQS signal.
With respect to a second differential DQS signal passed through the multiplexing circuitry 338, delay circuit 372 (a DLL, for example) phase shifts the second differential DQS for proper alignment with DQ. The second delayed differential DQS is then made available along an electrical path 376, with a driver 378 facilitating this as understood by those skilled in the art. The clock input of a latch 380 (a D flip-flop in the illustrated example) is electrically connected to the path 376 to receive the delayed differential DQS signal.
In the illustrated example, both the latches 380 and 370 receive DQ at their respective inputs as facilitated by driver 384 in a manner understood by those skilled in the art. Each next data of DQ is provided to a data capture FIFO in an alternating manner from either the latch 370 or 380, depending on which latch has its clock input brought active at that time.
The illustrated circuit 530 includes two comparators 532 and 536, an R-S latch 540 and a number of inverters. In operation, the circuit 530 corrects a signal VI (DQS signal) that is applied at inputs of the comparators 532 and 536, outputting a corrected signal at circuit output 544. It will be understood that the signal VI could be corrupted or distorted to at least some degree. For example, the signal VI may be noisy. Also, one skilled in the art will appreciate that the illustrated R-S latch 540 is an enable latch (level triggered); however it should be understood that in a number of contemplated embodiments any suitable storage circuitry that functions in a manner similar to an R-S latch could be employed.
With respect to the comparators 532 and 536, in at least some examples these are specialized comparators designed to be used as chip input buffers. In the illustrated circuit 530, non-inverting input 548 of the comparator 532 is coupled to the signal VI, and inverting input 552 is coupled to a reference voltage VR1 (high threshold of a hysteresis voltage). With respect to the comparator 536, inverting input 554 is coupled to the signal VI and non-inverting input 558 is coupled to a reference voltage VR0 (low threshold of the hysteresis voltage). Both the illustrated comparators 532 and 536 are provided with voltage sources MVDD and MVDDQ, the voltage source MVDD being intermediate MVDDQ and ground potential. In some examples, MVDDQ is the I/O signaling voltage, which is a selected one of 2.5V, 1.8V and 1.5V, and MVDD is the chip core voltage, which is a selected one of 1.0V and 1.2V.
Output 560 of the comparator 532 is coupled to a SET input of the R-S latch 540, which is input 562 of NAND gate 564 in the illustrated example embodiment. With respect to output 568 of the other comparator in the circuit 530, it is coupled to the input of inverter 572. The output of the inverter 572 is coupled to a RESET input of the R-S latch 540, which is input 576 of NAND gate 578 in the illustrated example embodiment. Two additional NAND gates within the R-S latch 540 are cross-coupled NAND gates 582 and 584. Output 586 of the NAND gate 564 is coupled to input 588 of the NAND gate 582, while output 590 of the NAND gate 578 is coupled to input 592 of the NAND gate 584. The illustrated R-S latch 540 also includes inverters 594 and 596 coupled to the outputs of the NAND gates 582 and 584 respectively. These inverters help prevent a glitch at the NAND gate outputs that might cause erroneous flipping. The inverters 594 and 596 also provide drive.
Still with reference to
Based on the above, whether the illustrated R-S latch 540 is ‘set’ or ‘reset’ will depend upon where the voltage of the signal VI falls relative to the reference voltages VR1 and VR0. If the voltage of the signal VI is above the reference voltage VR1, logic ‘1’ and logic ‘0’ will be applied to the SET and RESET inputs respectively. As will be appreciated by those skilled in the art, this condition ‘sets’ the R-S latch 540 (i.e. causes logic ‘1’ to appear at the output 544). If the voltage of the signal VI is in between the reference voltage VR1 and the reference voltage VR0, logic ‘0’ will be applied to both the SET and RESET inputs. As will be appreciated by those skilled in the art, this condition is the ‘hold’ condition for the R-S latch 540 (i.e. the state at the output 544 remains the same). Finally, if the voltage of the signal VI is below the reference voltage VR0, logic ‘0’ and logic ‘1’ will be applied to the SET and RESET inputs respectively. It will be understood that this condition ‘resets’ the R-S latch 540 (i.e. causes logic ‘0’ to appear at the output 544). With respect to an ENABLE signal received at an input of each of the NAND gates 564 and 578, the R-S latch 540 passes through latch inputs signals when this signal is logic low, and holds state when the signal is logic high.
The operation of the DQS transition detection circuit 530 with a noisy DQS signal applied as VI at the non-inverting input terminals of the comparators 532 and 536 will now be explained with reference to
It will be seen that at times tu and tv VI momentarily jumps above (sinks below) the reference voltage causing a corresponding momentary logic high-to-low transition in the signal at the RESET input (SET input). These short lived transitions do not produce an output value change in the R-S latch 540. In particular, the momentary logic high-to-low transition in the signal at the RESET input following the threshold crossing at tu does not result in a change in logic levels of the illustrated output signal Q because, as will be appreciated by those skilled in the art, logic low at both inputs of an R-S latch means that Q(t+Δ)=Q(t) (i.e. what is frequently referred to as the ‘hold’ state). Similarly (and for essentially the same reason) the momentary logic high-to-low transition in the signal at the SET input following the threshold crossing at tv does not result in a change in logic levels of the illustrated output signal Q.
With reference to both
With respect to the illustrated example, it will be seen that the preamble and postamble present in the input signal VI are missing in the output signal Q. It should be understood however that this is not characteristic of all examples of incorrupted strobe signals produced by contemplated circuit embodiments having similarity to the DQS transition detection circuit 530. For example, generation of an output strobe that includes a preamble could be accomplished with the addition of only some relatively non-complex circuitry to the DQS transition detection circuit 530.
With reference again to
Although example embodiments have been described with reference to DDR SDRAM, it will be understood that at least some example embodiments can be employed in other memory devices that might not be categorized as DDR SDRAM. For example, at least some example embodiments can be employed in Quad Data Rate SDRAM (QDR SDRAM) and Extreme Data Rate SDRAM (XDR SDRAM).
Various circuits and circuit components described in the preceding detailed description of example embodiments can be considered to be of a type performing known operations on electronic signals. Those skilled in the art will have knowledge of alternative circuits or circuit components which are recognized as equivalent because they provide the same operations on the signals.
Certain adaptations and modifications of the described embodiments can be made. Therefore, the above discussed embodiments are considered to be illustrative and not restrictive.
McKenzie, Robert, Millar, Bruce
Patent | Priority | Assignee | Title |
10083736, | Jun 23 2016 | Apple Inc. | Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage |
11226752, | Mar 05 2019 | Apple Inc.; Apple Inc | Filtering memory calibration |
7885127, | Jun 04 2008 | Hynix Semiconductor Inc. | Semiconductor memory device and operation method thereof |
7983112, | Jan 30 2007 | Renesas Electronics Corporation | Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system |
8630131, | Jul 30 2012 | Altera Corporation | Data strobe enable circuitry |
9001595, | Jul 30 2012 | Altera Corporation | Data strobe enable circuitry |
Patent | Priority | Assignee | Title |
6768698, | Mar 29 2002 | Renesas Technology Corp | Semiconductor memory device with internal clock generation circuit |
6889336, | Jan 05 2001 | Round Rock Research, LLC | Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal |
7143258, | Jul 15 2003 | Hynix Semiconductor Inc. | Method and device for masking ringing in a DDR SDRAM |
20030185088, | |||
20030200407, | |||
20050138277, | |||
20050206542, | |||
20080031079, | |||
CA2248731, | |||
JP2005026996, | |||
JP6046051, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 19 2007 | Mosaid Technologies Incorporated | (assignment on the face of the patent) | / | |||
Jul 20 2007 | MCKENZIE, ROBERT | Mosaid Technologies Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019624 | /0402 | |
Jul 20 2007 | MILLAR, BRUCE | Mosaid Technologies Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019624 | /0402 | |
Feb 09 2009 | Mosaid Technologies Incorporated | Mosaid Technologies Incorporated | CHANGE OF ADDRESS OF ASSIGNEE | 022542 | /0876 | |
Dec 23 2011 | Mosaid Technologies Incorporated | ROYAL BANK OF CANADA | U S INTELLECTUAL PROPERTY SECURITY AGREEMENT FOR NON-U S GRANTORS - SHORT FORM | 027512 | /0196 | |
Dec 23 2011 | 658868 N B INC | ROYAL BANK OF CANADA | U S INTELLECTUAL PROPERTY SECURITY AGREEMENT FOR NON-U S GRANTORS - SHORT FORM | 027512 | /0196 | |
Dec 23 2011 | 658276 N B LTD | ROYAL BANK OF CANADA | U S INTELLECTUAL PROPERTY SECURITY AGREEMENT FOR NON-U S GRANTORS - SHORT FORM | 027512 | /0196 | |
Jan 01 2014 | Mosaid Technologies Incorporated | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 032439 | /0638 | |
Jun 11 2014 | ROYAL BANK OF CANADA | CONVERSANT IP N B 276 INC | RELEASE OF SECURITY INTEREST | 033484 | /0344 | |
Jun 11 2014 | ROYAL BANK OF CANADA | CONVERSANT IP N B 868 INC | RELEASE OF SECURITY INTEREST | 033484 | /0344 | |
Jun 11 2014 | ROYAL BANK OF CANADA | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | RELEASE OF SECURITY INTEREST | 033484 | /0344 | |
Jun 11 2014 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | ROYAL BANK OF CANADA, AS LENDER | U S PATENT SECURITY AGREEMENT FOR NON-U S GRANTORS | 033706 | /0367 | |
Jun 11 2014 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | CPPIB CREDIT INVESTMENTS INC , AS LENDER | U S PATENT SECURITY AGREEMENT FOR NON-U S GRANTORS | 033706 | /0367 | |
Aug 20 2014 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | CHANGE OF ADDRESS | 033678 | /0096 | |
Jul 31 2018 | ROYAL BANK OF CANADA, AS LENDER | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | RELEASE OF U S PATENT AGREEMENT FOR NON-U S GRANTORS | 047645 | /0424 | |
Jul 31 2018 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | CPPIB CREDIT INVESTMENTS, INC | AMENDED AND RESTATED U S PATENT SECURITY AGREEMENT FOR NON-U S GRANTORS | 046900 | /0136 | |
Oct 28 2020 | CPPIB CREDIT INVESTMENTS INC | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 054444 | /0018 | |
Apr 01 2021 | CONVERSANT INTELLECTUAL PROPERTY INC | Mosaid Technologies Incorporated | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 057857 | /0200 | |
Apr 01 2021 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | Mosaid Technologies Incorporated | CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY S NAME PREVIOUSLY RECORDED AT REEL: 057857 FRAME: 0200 ASSIGNOR S HEREBY CONFIRMS THE CHANGE OF NAME | 064741 | /0347 |
Date | Maintenance Fee Events |
Mar 18 2013 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Jul 13 2017 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Jul 14 2021 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Jan 26 2013 | 4 years fee payment window open |
Jul 26 2013 | 6 months grace period start (w surcharge) |
Jan 26 2014 | patent expiry (for year 4) |
Jan 26 2016 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jan 26 2017 | 8 years fee payment window open |
Jul 26 2017 | 6 months grace period start (w surcharge) |
Jan 26 2018 | patent expiry (for year 8) |
Jan 26 2020 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jan 26 2021 | 12 years fee payment window open |
Jul 26 2021 | 6 months grace period start (w surcharge) |
Jan 26 2022 | patent expiry (for year 12) |
Jan 26 2024 | 2 years to revive unintentionally abandoned end. (for year 12) |