A method for forming a contact in a semiconductor device includes opening a contact hole exposing a surface of a substrate, performing a first post treatment to form a rough portion at a bottom surface of the contact hole, and performing a second post treatment. The first post treatment includes using a fluorocarbon gas and the second post treatment includes using a nitrogen trifluoride (NF3) gas.
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1. A method for forming a contact in a semiconductor device, the method comprising:
opening a contact hole exposing a surface of a substrate, wherein the contact hole is opened by using a plasma;
performing a first post treatment to form a first depression with a rough portion at a bottom surface of the contact hole; and
performing a second post treatment to form a second depression beneath the first depression, wherein the second depression has an increased surface roughness relative to the rough portion generated in the first post treatment,
wherein the ratio of a targeted etch loss in the substrate in the first post treatment to the second post treatment is approximately 2:1.
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The present invention claims priority of Korean patent application number 10-2006-0108385, filed on Nov. 3, 2006, which is incorporated by reference in its entirety.
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a contact in a semiconductor device with increased contact area and reduced leakage current.
As patterns in highly integrated memory devices below 0.100 μm become micronized, contact hole spacing has decreased. Accordingly, a high aspect ratio has caused margins to rapidly decrease, and thus, spacing distance between lines also have decreased. The source/drain contact resistance (Rc) increases substantially when the hole spacing and the spacing distance between lines decreases.
Referring to
A buffer oxide layer is formed over the resultant substrate structure. The buffer oxide layer is formed with poor step coverage. That is, the buffer oxide layer is formed to have a small thickness over upper surfaces of the substrate 11 and sidewalls of the gate patterns and have a large thickness over an upper portion of the gate patterns, having an overhang structure. An etch-back process is performed on the buffer oxide layer to form contact holes 17 exposing the upper surfaces of the substrate 11 between the gate patterns. This creates patterned buffer oxide layers 18. During the etch-back process, portions of the cell spacer layer over the upper surfaces of the substrate 11 are also etched away. This creates the cell spacers 15. Since the etch-back process of the buffer oxide layer includes a dry etching process using plasma, the substrate damage 19 is often generated by plasma ions during the etch-back process.
Referring to
The typical method increases the depth of the substrate depression 20 by the LET process which reduces contact resistance of the source/drain contacts, by increasing the contact area. However, the increased depth may cause leakage current, and refresh may be deteriorated. Also, although a certain depth in the substrate depression 20 is generally needed to control the cell threshold voltage (Vth) and the refresh, this is typically not enough to increase the contact resistance value. Thus, a method for forming a contact that can maintain a certain depth of the substrate depression and improve contact resistance may be necessary.
Embodiments of the present invention are directed towards providing a method for forming a contact in a semiconductor device that can reduce leakage current and improve contact resistance.
In accordance with an aspect of the present invention, there is provided a method for forming a contact in a semiconductor device, including: opening a contact hole exposing a surface of a substrate; performing a first post treatment to form a rough portion at a bottom surface of the contact hole; and performing a second post treatment.
In accordance with another aspect of the present invention, there is provided a method for forming a contact in a semiconductor device, including: forming a gate pattern over a substrate; forming a barrier layer over the gate pattern; forming an insulation layer over the barrier layer; etching the insulation layer to form a contact hole; forming a buffer layer overhanging from an upper portion of the gate pattern exposed by the contact hole; etching the buffer layer and the barrier layer to expose a surface of the substrate; performing a first post treatment to form a rough portion on the exposed surface of the substrate; and performing a second post treatment to remove contamination generated in the first post treatment.
The present invention relates to a method for forming a contact in a semiconductor device. According to embodiments of the present invention, a landing plug contact etching process is performed, a nitride-based layer used as a cell spacer is removed, and a light etch treatment (LET) is performed using a dry etch apparatus to remove substrate damages. A recipe of the LET process is controlled to improve the contact resistance value through increasing the surface area.
The source/drain contact resistance may be improved by creating a rough surface on the substrate depression while maintaining the depth for controlling the cell threshold voltage and refresh. Thus, an electrical characteristic of the device may be improved, and yield and reliability may be increased.
Referring to
An insulation layer is formed over the resultant substrate structure to sufficiently gap-fill between the gate patterns. The insulation layer may include borophosphosilicate glass (BPSG). An etching process for forming the landing plug contacts is performed on the insulation layer to form inter-layer insulation layers 26. That is, the insulation layer is etched until the etching stops at the cell spacer layer 25. Accordingly, contact holes 27 are formed after the insulation layer is etched, and the cell spacer layer 25 is exposed at the bottom of the contact holes 27. Generally, landing plugs are formed between gate patterns in a cell region. Thus, the contact holes 27 expose the gate patterns and spaces between the gate patterns.
Referring to
Referring to
A post treatment is performed to remove the substrate damage 29 generated during the etch-back process of the buffer oxide layer 28. The post treatment includes performing an etching process referred to as a light etch treatment (LET). For instance, the LET process applies a process using a chemical dry etching (CDE) apparatus. The LET process increases the surface area. In more detail, the post treatment for removing the substrate damage 29 includes a two-step LET process configured with a first post treatment and a second post treatment in accordance with an embodiment of the present invention.
Referring to
The first post treatment may use CF4 at a flow rate of approximately 10 sccm to 20 sccm, helium (He) at a flow rate of approximately 500 sccm to 1,000 sccm, and oxygen (O2) at a flow rate of approximately 20 sccm to 40 sccm. The first post treatment may also use CHF3 at a flow rate of approximately 10 sccm to 20 sccm, He at a flow rate of approximately 500 sccm to 1,000 sccm, and O2 at a flow rate of approximately 20 sccm to 40 sccm. As shown in the above recipes, a flow rate ratio of the fluorocarbon gas to the oxygen gas is approximately 1:2. The flow rate ratio of the fluorocarbon gas to the oxygen gas is controlled to be approximately 1:3 or less. By controlling the flow rate ratio, the substrate roughness of the rough portions 30A may be largely induced. Also, it is easy to control the depth D1 of the substrate depression 30 since the oxygen gas does not have a large flow rate. The rough portions 30A largely increase the substrate roughness on the surface of the substrate depression 30. However, the use of fluorocarbon gas may generate carbon contamination.
Referring to
Referring to the post treatment process, the first post treatment and the second post treatment both use a high pressure ranging from approximately 1,000 mTorr to 1,500 mTorr and a high source power of approximately 2,500 W or greater (i.e., ranging from approximately 2,500 W to 5,000 W). Thus, a mean free path and a residence time of the etchant is increased to further increase the surface area. The ratio of a targeted etch loss in the substrate in the first post treatment to the second treatment is approximately 2:1. The substrate depression generated in the first post treatment is controlled to approximately two times the substrate depression generated in the second post treatment. Thus, surface roughness is increased.
According to the embodiments of the present invention, applying the two-step LET process including the first post treatment and the second post treatment may allow maintaining the demanded substrate depression depth and reducing leakage current. At the same time, the contact resistance values may be improved by increasing the contact area by more than approximately 10% through increasing the surface roughness.
While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
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Dec 22 2006 | LEE, JUNG-SEOCK | Hynix Semiconductor Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019020 | /0743 | |
Dec 22 2006 | HAN, KY-HYUN | Hynix Semiconductor Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019020 | /0743 | |
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