The present invention relates to a method and apparatus for trimming a reference voltage. The method may include at least one steep of performing an erase operation of a flash memory resistor; performing a program operation of the flash memory resistor; performing a current read operation of the flash memory resistor; confirming the threshold voltage of the flash memory resistor by measuring the current flowing into a drain of the flash memory resistor; determining whether the threshold voltage of the flash memory resistor satisfies a reference voltage; and then completing the trimming operation if the threshold voltage of the flash memory resistor satisfies the reference voltage.
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7. A method comprising:
performing an erase operation of a flash memory resistor including a flash memory in a circuit for trimming a reference voltage, wherein the flash memory includes a drain connected to a source of a nmos transistor, a source connected to a system voltage, and a gate connected to a drain voltage;
performing a program operation of the flash memory resistor;
performing a current read operation of the flash memory resistor;
confirming the threshold voltage of the flash memory resistor by measuring the current flowing into a drain of the flash memory resistor;
determining whether the threshold voltage of the flash memory resistor satisfies a reference voltage; and then
completing the trimming operation if the threshold voltage of the flash memory resistor satisfies the reference voltage.
1. An apparatus comprising:
a circuit for trimming a reference voltage including a resistor dividing a drain voltage, a flash memory resistor including a flash memory, an nmos transistor turning on/off a drain of the flash memory, and an amplifier comparing the reference voltage and a node voltage, wherein the resistor includes one end connected to a v node, the nmos transistor has a drain connected to the v node and a source connected to the drain of the flash memory, the flash memory includes the drain connected to the source of the nmos transistor, a source connected to a system voltage, and a gate connected to a drain voltage, and the amplifier is connected to the v node to receive the node voltage;
an nmos gate switch turning on/off the nmos transistor;
a flash cell gate switch switching the gate voltage of the flash memory when the flash memory is in at least one of program, erase, and resistance states;
a flash cell source switch switching a source voltage of the flash memory for the erase operation of the flash memory; and
a flash cell drain switch switching the drain voltage of the flash memory for the program operation of the flash memory.
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This application claims the benefit of Korean Patent Application No. 10-2006-0117376, filed on Nov. 27, 2006, which is hereby incorporated by reference as if fully set forth herein.
In flash memory devices, the value of an internal voltage used for erasing and/or programming may be adjusted using a reference voltage. Because the reference voltage may be variable depending on the change in temperature, an external power supply, and a process, the reference voltage may be trimmed by a method using a fuse in order to adjust the reference voltage.
As illustrated in example
However, node voltage VNODE may be varied depending on the resistance values of first resistor R1 and second resistor R2. In essence, the resistance values of first resistor R1 and second resistor R2 may be varied depending on system voltage VDD and process conditions in the semiconductor manufacturing process so that the precision of the voltage detection may be degraded due to the change in node voltage VNODE.
As illustrated in example
Accordingly, although the trimming may be made to conform to the characteristics for every chip using metal option 200 including a poly fuse and a metal fuse, a separate laser cutting apparatus may be required after testing. When an electrical fuse is used, a defect chip may be generated by a fragment due to a blown fuse, and trimming work cannot be fully conducted after completing the trimming so that the flexibility of production is degraded.
While a small resistor has been used in the semiconductor process, a large resistor may be required in order to minimize power consumption. Therefore, in order to make a resistor with a large value, the resistor occupies a considerable portion of a chip size. In particular, when a circuit requiring a plurality of resistors is added, the number of chips producible per a unit area unit area is reduced.
Embodiments relate to an apparatus for trimming a reference voltage of a flash memory device insensitive to the change in a drain voltage and process conditions in a semiconductor process.
Embodiments relate to an apparatus for trimming a reference voltage of a flash memory device that may include a circuit for trimming a reference voltage including a resistor dividing a drain voltage, a flash memory resistor formed of a flash memory, an NMOS turning on/off the drain of the flash memory, and an amplifier comparing the reference voltage and a node voltage; an NMOS gate switch turning on/off the NMOS; a flash cell gate switch switching the gate voltage of the flash memory when the flash memory is in program, erase, and resistance states; a flash cell source switch switching the source voltage of the flash memory for the erase operation of the flash memory; and a flash cell drain switch switching the drain voltage of the flash memory for the program operation of the flash memory.
Embodiments relate to a method for trimming a reference voltage of a flash memory device using a resistor formed of a flash memory including at least one of the following steps: performing an erase operation of flash memory resistor; performing a program operation of the flash memory resistor; performing a read operation of the current of the flash memory resistor; confirming the threshold voltage of the flash memory resistor by measuring the current flowing into the drain of the flash memory resistor; determining whether the threshold voltage of the flash memory resistor satisfies the reference voltage; and completing the trimming operation if the threshold voltage of the flash memory resistor satisfies the reference voltage.
Example
Example
Example
Example
Example
Example
As illustrated in example
As illustrated in example
As illustrated in example
As illustrated in example
As illustrated in example
As illustrated in example
The erase operation may be performed as follows. When flash memory resistor F1 is in an erase state, Flash_EN input signal can be input to NMOS gate switch 410 to output source voltage VSS to second node ND2 so that NMOS transistor N1 is turned off. Moreover, ERASE_EN input signal can be input to flash cell gate switch 420 to output source voltage VSS to third node ND3 so that the source voltage can be applied to the gate of the flash memory. ERASE_EN input signal can be applied to flash cell source switch 430 to apply high voltage VPPI_ERASE to the source of the flash memory.
After completion of step S810, i.e., upon completion of the erase operation of flash memory resistor F1, flash memory resistor F1 may perform step S820, i.e., a program operation.
The program operation may be performed as follows. When flash memory resistor F1 is in a program state, Flash_EN input signal can be input to NMOS gate switch 410 to output source voltage VSS to second node ND2, thereby turning off NMOS transistor N1. PGM_EN input signal can be also applied to flash cell gate switch 420 to output high voltage VPPI_PGM to third node ND3 so that high voltage VPP_PGM can be applied to the gate of the flash memory. ERASE_EN input signal input to flash cell source switch 430 can be disabled to apply source voltage VSS to the source of the flash memory and PGM_EN input signal can be input to flash cell drain switch 440 to output drain voltage VDD to first node ND1 so that drain voltage VDD is applied to the drain of the flash memory.
After completion of step S820, i.e., upon completion of the program operation of flash memory resistor F1, flash memory resistor F1 may perform step S830, i.e., a current read operation.
The current read operation may be performed as follows. When the flash memory is in a current read state, Flash_EN input signal can be input to NMOS gate switch 410 to output source voltage VSS to second node ND2, thereby turning off NMOS transistor N1. PGM_EN input signal input to flash cell gate switch 420 can also be disabled to output drain voltage VDD to the third node ND3 so that drain voltage VDD can be applied to the drain of the flash memory. ERASE_EN input signal input to flash cell source switch 430 can also be disabled to apply source voltage VSS to the source of the flash memory and READ_EN input signal can be input to flash cell drain switch 440 to output drain voltage VDD to first node ND1 so that drain voltage VDD can be applied to the drain of the flash memory.
After completion of step S830, i.e., upon completion of the current read operation of flash memory resistor F1, the threshold voltage of flash memory resistor F1 can be confirmed in step S840 by measuring the current flowing into the drain of flash memory resistor F1.
When performing confirmation step S840, a determination is made in step S850 whether the threshold voltage of flash memory resistor F1 satisfies the reference voltage. If the threshold voltage of flash memory resistor F1 satisfies the reference voltage, the trimming operation is completed in step S860. As a result, the flash memory can be used as the resistor. If, however, the confirmed threshold voltage does not satisfy the reference voltage in the current read state of the flash memory, the program operation of the flash memory (i.e., step S820) and the current read operation of the flash memory (i.e., step S830) are repeatedly performed so that the threshold voltage conforms to the reference voltage.
In accordance with embodiments, a method and apparatus for trimming a reference voltage of a flash memory device is provided extending numerous advantages. For instance, use of a flash memory as a resistor so that a resistor insensitive to the change in drain voltage and process conditions in a semiconductor process can enhance the precision of the resistor and conform an optimal resistance value to the characteristics for every chip. Because a metal option is not utilized, separate mask manufacturing cost is not required, thereby reducing overall development costs. Separate testing or the use of a laser cutting apparatus due to the use of the fuse can be avoided. Flexibility of production can be enhanced by effectively coping with the demand of the rework of the trimming after completing the trimming work. The overall number of chips produced per unit area can be increased by reducing the area of a resistor that heretofore, occupied a considerable portion of the chip size in order to make a resistor with a large value.
Although embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
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