An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at vcmi.
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10. A method for rejecting common-mode input voltage variations in a differential sampler comprising:
sampling a first differential input voltage, Vinp, at a given time to provide a first sampled input voltage having a first common mode component;
sampling a second differential input voltage, Vinm, at the given time to provide a second sampled input voltage having a second common mode component;
sensing common-mode variations in the first and second differential input voltages, to detect such common-mode variations as a corresponding common mode voltage vcmi;
sampling the common mode voltage vcmi at the given time to provide a sampled common mode voltage;
discharging current from the first and second sampler via a common discharge node, Vdch, to provide a common path for discharging sampled current for each of the first and second samplers; and
maintaining the discharge node, Vdch, at a substantially constant voltage difference with respect to the common mode voltage, vcmi.
1. An apparatus for rejecting common-mode input voltage variations in a differential sampler, comprising:
a first sampler, for sampling a first differential input voltage, Vinp, at a given time, the first differential input voltage having a first common mode component;
a second sampler, for sampling a second differential input voltage, Vinm, at the given time, the second differential input voltage having a second common mode component;
a circuit for sensing common-mode variations in the first and second differential input voltages, the circuit detecting such common-mode variations as a corresponding common mode voltage vcmi;
a third sampler, for sampling the common mode voltage, vcmi, at the given time;
a discharge path connected to the first and second sampler and also connected to a common discharge node, Vdch, to provide a common path for discharging sampled current for each of the first and second samplers; and
a fixed voltage source, for maintaining the discharge node, Vdch, at a substantially constant voltage difference with respect to the common mode voltage, vcmi.
19. An apparatus for rejecting common-mode input variations in a differential sampler, comprising:
a first sampler switch, connected between a first differential input voltage terminal, Vinp, and a first sampler node capacitive element of capacitance Cs;
a first discharge switch connected between the first sampler node and a common discharge node, Vdch;
a second sampler comprising:
a second sampler switch, connected between a second differential input voltage terminal, Vinm, and a second sampler node capacitive element of capacitance Cs;
a second discharge switch connected between the second sampler node and the common discharge node, Vdch;
a first resistive element connected between the first differential input terminal and a common node, vcmi;
a second resistive element connected between the second differential input terminal and the common node, vcmi;
the second sampler, for sampling a second differential input voltage, Vinm, at the given time, the second differential input voltage having a second common mode component;
a third sampler comprising: a third sampler switch, connected to sample the common mode voltage, vcmi, at the given time and storing the same on a respective sampling capacitive element, Ccmc; and
a switch control circuit for (a) obtaining samples of the first and second differential input terminals and the common node vcmi by controlling the first, second and third sampler switches to operate at the same time according to a first clock signal, Ktp, and (b) discharging energy stored in both of the capacitive elements Cs via a common path by operating the first and second discharge switches according to a second clock signal, Kct, so that voltage at the common discharge node Vdch is held at a constant difference with respect to voltage on the common node vcmi by capacitive element Ccmc.
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This application claims the benefit of U.S. Provisional Application No. 60/898,216, filed on Jan. 30, 2007. The entire teachings of the above application are incorporated herein by reference.
In many (high-speed) analog-to-digital converters (ADCs), the analog input-signal is sampled onto input sampling-capacitors prior to conversion. Any intervening circuitry between the analog input and the sampling capacitors can be a source of degradation, adding distortion and/or noise. Therefore, to achieve the highest possible spurious-free-dynamic-Range (SFDR) and highest Signal-to-Noise-Ratio (SNR), many high-performance samplers and ADCs leave out active front-end differential amplifiers, resulting in topologies similar to those shown in
While a single-ended sampler/converter can be made from the circuits shown in
In practice, most analog inputs, even those intended to be fully differential, have some residual common-mode voltage variation as the differential-signal swings through its range. For example, the inputs of high-speed converters are often driven from transformer-based baluns that perform unbalanced (single-ended) to balanced (differential) conversion. These baluns are not perfect, resulting in a common-mode component at their outputs. Another way to say this is that if vinp and vinm do not have equal amplitudes and exactly 180° relative-phase, a residual time-varying common-mode component will appear at the sampler/converter inputs. The sampler converts input voltage to charge stored on the sampling capacitors, so any input common-mode-voltage variation will result in a common-mode charge variation on the two sampling capacitors. Downstream circuitry must then be able to accommodate this common-mode variation without a loss in performance.
A second approach to driving the converter inputs is to precede the converter with an active differential amplifier, as mentioned above. This differential amplifier can provide some degree of common-mode rejection, like the transformer. But again, real-life amplifiers are not perfect, and they too leave a residual common-mode voltage variation for the sampler/converter to deal with. Additionally, these active amplifiers add distortion and noise, often exceeding that of the sampler/converter itself.
What is needed is an approach to rejecting input common-mode voltage variations without the use of a differential amplifier in the signal path, and without any added distortion or noise. Embodiments of the present invention provide one such method. The input common-mode variations are sensed on a pair of matched resistors that straddle the analog inputs, on the node marked ‘Vcmi’ in the accompanying drawings. In an alternative embodiment, common mode variations may be sensed using switched-capacitor circuitry. Using this measured Vcmi, adjustments are made to the rest of the sampler/converter to take out any variations observed at Vcmi.
The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.
A description of example embodiments of the invention follows.
In the conventional (or “legacy”) sampler of
In contrast, the proposed common-mode-insensitive (Vcm-tracking) sampler of
Returning to the operation of the sampler circuit in
Upon completing sampling of the signals Vinp, Vinm and Vcmi, the sampling circuit may enter a transfer state to transfer the sampled charges via charge outputs Vfdp, Vfdm. Switches controlled by Kbp and Ktp are opened, and switches controlled by Kct are closed. As a result, the buffered-version of the sampled common-mode voltage, Vcmi_s, drives one side of the correction capacitor Ccmc, forcing the other node connected to this capacitor, Vdch, down to Vcmi−Vcmc_samp. This, in turn, drives the charge out of the sampling capacitors into the downstream circuitry. For large Ccmc (Ccmc>>Cc), there is minimal capacitive charge division, so Vdch is held at a constant voltage drop below the common mode input Vcmi, thereby tracking any common-mode variation of sampled charges at capacitors Cs (due to input common-mode changes at Vinp and Vinm). Thus, the sampling circuit provides sampled differential output charges at charge outputs Vfdp, Vfdm having a constant common-mode charge Qcm that is independent of the common mode input voltage Vcmi.
Note that in the legacy sampler of
The measured performance of the Vcm-tracking sampler of
Embodiments of the present invention may provide common-mode variation rejection for time-varying input signals.
In contrast, the Vcm-tracking sampler (
While most high-speed converters require a relatively low source impedance to achieve high bandwidths, some applications cannot tolerate resistor loads coupled directly to the sampler inputs. For those or other applications, the alternative common-mode sense circuit of
Embodiments of the present invention may also be applied to op-amp-based converters, as shown for example in
While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.
Fisher, John S., Anthony, Michael P., Kushner, Lawrence J.
Patent | Priority | Assignee | Title |
10187077, | Sep 11 2015 | Texas Instruments Incorporated | Precharge switch-capacitor circuit and method |
11611341, | Dec 11 2018 | Infineon Technologies AG | Sampling circuit and sampling method |
8456337, | Apr 10 2012 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | System to interface analog-to-digital converters to inputs with arbitrary common-modes |
8907703, | Mar 15 2013 | Analog Devices International Unlimited Company | Isolated high voltage sampling network |
9960782, | Sep 11 2015 | Texas Instruments Incorporated | Precharge switch-capacitor circuit and method |
Patent | Priority | Assignee | Title |
5963156, | Oct 22 1997 | National Semiconductor Corporation | Sample and hold circuit and method with common mode differential signal feedback for converting single-ended signals to differential signals |
6369729, | Oct 08 1999 | Cirrus Logic, Inc. | Common mode shift in downstream integrators of high order delta sigma modulators |
6486820, | Mar 19 2001 | Cisco Technology, Inc | Pipeline analog-to-digital converter with common mode following reference generator |
6515612, | Oct 23 2001 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Method and system to reduce signal-dependent charge drawn from reference voltage in switched capacitor circuits |
6768443, | Nov 30 2000 | NXP USA, INC | Switch capacitor circuit and applications thereof |
6774722, | Oct 16 2002 | HAIKU ACQUISITION CORPORATION; CENTILLIUM COMMUNICATIONS, INC | Frequency compensation of common-mode feedback loops for differential amplifiers |
6891487, | Jun 03 2003 | Silicon Laboratories Inc | Capacitor calibration in SAR converter |
7023373, | Sep 24 2003 | Infineon Technologies AG | Multi-stage ADC with shared amplifier and reference voltage selection |
20040075502, |
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