A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.
|
1. A method for forming a semiconductor device on a semiconductor material layer, comprising:
forming a gate structure over the semiconductor material layer having a metal layer directly on a gate dielectric;
forming a first nitride spacer directly on the gate structure, wherein the first nitride spacer has a width less than 90 angstroms;
forming source/drain extensions in the semiconductor material layer using the nitride spacer as a mask;
forming an oxide liner overlying the gate structure and the source/drain extensions and directly on the first nitride spacer;
forming a second nitride spacer directly on the oxide liner;
forming source/drain regions in the semiconductor material layer using the second nitride spacer as a mask;
using an etching process that is selective to the oxide liner, removing the second nitride spacer;
using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner;
forming silicide regions overlying the source/drain regions and the gate structure; and
forming a stressor layer overlying the silicide regions and the first nitride spacer to generate stress in a channel region of the semiconductor device.
8. A method for forming a semiconductor device over a semiconductor material layer, comprising:
forming a gate structure over the semiconductor material layer having a metal on a gate dielectric;
forming a first nitride spacer on the gate structure, wherein the first nitride spacer has a width less than 90 angstroms;
forming source/drain extensions in the semiconductor material layer substantially aligned to the first nitride spacer;
forming an oxide liner directly on the gate structure and the source/drain extensions;
forming a second nitride spacer directly on the oxide liner;
forming source/drain regions in the semiconductor material layer;
performing an anneal to extend the source/drain extensions
etching the second nitride spacer using an etchant having an etch chemistry such that the etchant has a minimal effect on the oxide liner;
etching the oxide liner using an etchant having an etch chemistry such that the etchant has a minimal effect on the first nitride spacer;
forming silicide regions overlying the source/drain regions and the gate structure substantially aligned to the first nitride spacer; and
forming a stressor layer over the gate structure and the silicide regions after etching the oxide liner.
13. A method for forming a semiconductor device over a semiconductor material layer, comprising:
forming a gate structure over the semiconductor material layer having a metal on a gate dielectric;
forming a first nitride spacer directly on the gate structure, wherein the first nitride spacer has a width less than 90 angstroms;
forming source/drain extensions in the semiconductor material layer;
forming an oxide liner directly on the gate structure and overlying the source/drain extensions;
forming a second nitride spacer directly on the oxide liner;
forming source/drain regions in the semiconductor material layer;
performing an anneal to extend the source/drain extensions
using an etching process that is selective to the oxide liner, removing the second nitride spacer;
using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner;
forming silicide regions using the first nitride spacer as a mask overlying the source/drain regions and the gate structure, wherein the width of the first nitride spacer and a width of a remaining oxide liner is selected in a manner that the silicide regions do not extend into a channel region of the semiconductor device; and
forming a stressor layer overlying the silicide regions and the first nitride spacer to generate stress in the channel region of the semiconductor device.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
9. The method of
10. The method of
11. The method of
12. The method of
14. The method of
15. The method of
16. The method of
|
1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to making transistors with a stressor.
2. Related Art
Increasing stress in the channel of MOS transistors has been found to improve performance by increasing carrier mobility. In the case of N channel transistors the improvement is found by increasing tensile stress. In the case of P channel transistors the improvement is found by increasing compressive stress. One technique for doing this is to provide a stressor layer of dielectric material over the gate and source drain after the transistor has been formed. This is convenient because there must be a dielectric layer over the transistor anyway to separate it from overlying interconnect layers. One desire is for the stressor layer to be as close as possible to the channel to provide as much as stress to the channel as possible. Techniques for doing this have had some difficulties due to causing adverse effects when removing sidewall spacers.
Thus there is a need for providing a stressor in close proximity to the channel in which the process avoids or reduces the adverse impact of doing so.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
In one aspect, a gate has a sidewall spacer of an inner layer of nitride, an intermediate layer of oxide, and an outer layer of nitride. These different layers are used for masking the deep source/drain implant and the extension implant. The outer nitride layer is removed using the intermediate oxide layer as an etch stop layer. The intermediate oxide layer is removed selective to the underlying inner nitride layer so that the inner nitride layer remains. A silicide is formed over the source/drain regions and the gate using the inner nitride layer as mask. The stressor layer is then applied over the gate and source/drains so that the relatively thick outer nitride layer and the intermediate oxide layer are not separating the stressor layer from the channel. The result is close coupling of the stress of the stressor layer to the channel which is beneficial in further improving carrier mobility of the transistor.
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
One reason that the resulting structure of
Semiconductor substrate 12 described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. In the case of being a bulk substrate as well as SOI, the top portion may be considered a semiconductor material layer.
By now it should be appreciated that there has been provided a method for forming a semiconductor device on a semiconductor material layer. The method includes forming a gate structure over the semiconductor material layer. The method includes forming a first nitride spacer adjacent to the gate structure. The method includes forming source/drain extensions in the semiconductor material layer. The method includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method includes forming a second nitride spacer adjacent to the oxide liner. The method includes forming source/drain regions in the semiconductor material layer. The method includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method includes forming silicide regions overlying the source/drain regions and the gate structure. The method includes forming a stressor layer overlying the silicide regions and the first nitride spacer to generate stress in a channel region of the semiconductor device. The method may be further characterized by the gate structure comprising a gate dielectric layer, a metal gate layer, and a polysilicon layer. The method may be further characterized by the step of using the etching process that is selective to the oxide liner, further comprising etching the second nitride spacer using an etchant having an etch chemistry such that the etchant has a minimal effect on the oxide liner. The method may be further characterized by the step of using the etching process that is selective to the first nitride spacer further comprising etching the oxide liner using an etchant having an etch chemistry such that the etchant has a minimal effect on the first nitride spacer. The method may further comprise performing a hydrofluoric acid (HF) clean after removing the oxide liner and before forming the silicide regions. The method may further comprise annealing the source/drain regions after forming the source/drain regions. The method may be further characterized by the step of forming the first nitride spacer being further characterized by a thickness of the first nitride spacer is selected in a manner that the silicide regions do not extend into the channel region of the semiconductor device. The method may further comprise forming a second oxide liner overlying the silicide regions and the gate structure prior to forming the stressor layer.
Also described is a method for forming a semiconductor device over a semiconductor material layer. The method includes forming a gate structure over the semiconductor material layer. The method includes forming a first nitride spacer adjacent to the gate structure. The method includes forming source/drain extensions in the semiconductor material layer. The method includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method includes forming a second nitride spacer adjacent to the oxide liner. The method includes forming source/drain regions in the semiconductor material layer. The method includes etching the second nitride spacer using an etchant having an etch chemistry such that the etchant has a minimal effect on the oxide liner The method includes etching the oxide liner using an etchant having an etch chemistry such that the etchant has a minimal effect on the first nitride spacer. The method includes forming silicide regions overlying the source/drain regions and the gate structure. The method may be further characterized by the gate structure comprising a gate dielectric layer, a metal gate layer, and a polysilicon layer. The method may further comprise performing a hydrofluoric acid (HF) clean after etching the oxide liner and before forming the silicide regions. The method may further comprise annealing the source/drain regions after forming the source/drain regions. The method may be further characterized by a thickness of the first nitride spacer is selected in a manner that the silicide regions do not extend into a channel region of the semiconductor device. The method may further comprise forming a stressor layer overlying the silicide regions and the first nitride spacer to generate stress in a channel region of the semiconductor device. The method may further comprise forming a second oxide liner overlying the silicide regions and the gate structure prior to forming the stressor layer.
Yet also described is a method for forming a semiconductor device over a semiconductor material layer. The method includes forming a gate structure over the semiconductor material layer. The method includes forming a first nitride spacer adjacent to the gate structure The method includes forming source/drain extensions in the semiconductor material layer. The method includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method includes forming a second nitride spacer adjacent to the oxide liner. The method includes forming source/drain regions in the semiconductor material layer. The method includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method includes forming silicide regions overlying the source/drain regions and the gate structure, wherein a thickness of the first nitride spacer and a thickness of a remaining oxide liner is selected in a manner that the silicide regions do not extend into a channel region of the semiconductor device. The method includes forming a stressor layer overlying the silicide regions and the first nitride spacer to generate stress in the channel region of the semiconductor device. The method may be further characterized by the step of using the etching process that is selective to the oxide liner, further comprising etching the second nitride spacer using an etchant having an etch chemistry such that the etchant has a minimal effect on the oxide liner. The method may be further characterized by the step of using the etching process that is selective to the first nitride spacer, further comprising etching the oxide liner using an etchant having an etch chemistry such that the etchant has a minimal effect on the first nitride spacer. The method may further comprise forming a second oxide liner overlying the silicide regions and the gate structure prior to forming the stressor layer. The method may be further characterized by the thickness of the first nitride spacer is less than 90 Angstroms.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, specific dimensions were provided and they may be changed. Also certain materials were specified in some cases and they may be varied. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Loiko, Konstantin V., Bo, Xiangzheng, Kolagunta, Venkat R.
Patent | Priority | Assignee | Title |
8324110, | Feb 02 2010 | ALSEPHINA INNOVATIONS INC | Field effect transistor (FET) and method of forming the FET without damaging the wafer surface |
8598664, | Feb 02 2010 | ALSEPHINA INNOVATIONS INC | Field effect transistor (FET) and method of forming the FET without damaging the wafer surface |
8871598, | Jul 31 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
8877568, | Oct 29 2010 | NXP USA, INC | Methods of making logic transistors and non-volatile memory cells |
8877585, | Aug 16 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration |
8901632, | Sep 30 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology |
8906764, | Jan 04 2012 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and logic integration |
8932925, | Aug 22 2013 | NXP USA, INC | Split-gate non-volatile memory (NVM) cell and device structure integration |
8951863, | Apr 06 2012 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and logic integration |
9006093, | Jun 27 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and high voltage transistor integration |
9082650, | Aug 21 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Integrated split gate non-volatile memory cell and logic structure |
9082837, | Aug 08 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Nonvolatile memory bitcell with inlaid high k metal select gate |
9087913, | Apr 09 2012 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
9111865, | Oct 26 2012 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method of making a logic transistor and a non-volatile memory (NVM) cell |
9112056, | Mar 28 2014 | NXP USA, INC | Method for forming a split-gate device |
9129855, | Sep 30 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
9129996, | Sep 10 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration |
9136129, | Sep 30 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology |
9231077, | Mar 03 2014 | NXP USA, INC | Method of making a logic transistor and non-volatile memory (NVM) cell |
9252152, | Mar 28 2014 | NXP USA, INC | Method for forming a split-gate device |
9252246, | Aug 21 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Integrated split gate non-volatile memory cell and logic device |
9257445, | May 30 2014 | NXP USA, INC | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor |
9275864, | Aug 22 2013 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates |
9343314, | May 30 2014 | NXP USA, INC | Split gate nanocrystal memory integration |
9379222, | May 30 2014 | NXP USA, INC | Method of making a split gate non-volatile memory (NVM) cell |
9472418, | Mar 28 2014 | NXP USA, INC | Method for forming a split-gate device |
Patent | Priority | Assignee | Title |
6214673, | Jul 09 1999 | Fairchild Semiconductor Corporation | Process for forming vertical semiconductor device having increased source contact area |
6680233, | Oct 09 2001 | Advanced Micro Devices, Inc. | Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication |
6727135, | Jul 19 2001 | GLOBALFOUNDRIES U S INC | All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS |
6737710, | Jun 30 1999 | BEIJING XIAOMI MOBILE SOFTWARE CO , LTD | Transistor structure having silicide source/drain extensions |
6777299, | Jul 07 2003 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for removal of a spacer |
6869839, | Nov 14 2002 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device having an L-shaped spacer |
7316960, | Jul 13 2004 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhanced ultra shallow junction formation |
7354838, | Apr 29 2005 | INNOVATIVE FOUNDRY TECHNOLOGIES LLC | Technique for forming a contact insulation layer with enhanced stress transfer efficiency |
20030006410, | |||
20050275034, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 06 2007 | BO, XIANGZHENG | Freescale Semiconductor, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019664 | /0503 | |
Aug 06 2007 | KOLAGUNTA, VENKAT R | Freescale Semiconductor, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019664 | /0503 | |
Aug 06 2007 | LOIKO, KONSTANTIN V | Freescale Semiconductor, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019664 | /0503 | |
Aug 08 2007 | Freescale Semiconductor, Inc. | (assignment on the face of the patent) | / | |||
Oct 25 2007 | Freescale Semiconductor, Inc | CITIBANK, N A | SECURITY AGREEMENT | 020518 | /0215 | |
Feb 19 2010 | Freescale Semiconductor, Inc | CITIBANK, N A | SECURITY AGREEMENT | 024085 | /0001 | |
Apr 13 2010 | Freescale Semiconductor, Inc | CITIBANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 024397 | /0001 | |
May 21 2013 | Freescale Semiconductor, Inc | CITIBANK, N A , AS NOTES COLLATERAL AGENT | SECURITY AGREEMENT | 030633 | /0424 | |
Nov 01 2013 | Freescale Semiconductor, Inc | CITIBANK, N A , AS NOTES COLLATERAL AGENT | SECURITY AGREEMENT | 031591 | /0266 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 053547 | /0421 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 041703 | /0536 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 053547 | /0421 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 037486 | /0517 | |
Dec 07 2015 | CITIBANK, N A , AS COLLATERAL AGENT | Freescale Semiconductor, Inc | PATENT RELEASE | 037354 | /0704 | |
May 25 2016 | Freescale Semiconductor, Inc | MORGAN STANLEY SENIOR FUNDING, INC | SUPPLEMENT TO THE SECURITY AGREEMENT | 039138 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052915 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 040928 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052915 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052917 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052917 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V , F K A FREESCALE SEMICONDUCTOR, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 040925 | /0001 | |
Nov 07 2016 | Freescale Semiconductor Inc | NXP USA, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001 ASSIGNOR S HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME | 044209 | /0047 | |
Nov 07 2016 | Freescale Semiconductor, Inc | NXP USA, INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 040632 | /0001 | |
Feb 17 2019 | MORGAN STANLEY SENIOR FUNDING, INC | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536 ASSIGNOR S HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 048734 | /0001 | |
Feb 17 2019 | MORGAN STANLEY SENIOR FUNDING, INC | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536 ASSIGNOR S HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 048734 | /0001 | |
Sep 03 2019 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 050744 | /0097 |
Date | Maintenance Fee Events |
Mar 21 2014 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Dec 12 2017 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Dec 14 2021 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Sep 21 2013 | 4 years fee payment window open |
Mar 21 2014 | 6 months grace period start (w surcharge) |
Sep 21 2014 | patent expiry (for year 4) |
Sep 21 2016 | 2 years to revive unintentionally abandoned end. (for year 4) |
Sep 21 2017 | 8 years fee payment window open |
Mar 21 2018 | 6 months grace period start (w surcharge) |
Sep 21 2018 | patent expiry (for year 8) |
Sep 21 2020 | 2 years to revive unintentionally abandoned end. (for year 8) |
Sep 21 2021 | 12 years fee payment window open |
Mar 21 2022 | 6 months grace period start (w surcharge) |
Sep 21 2022 | patent expiry (for year 12) |
Sep 21 2024 | 2 years to revive unintentionally abandoned end. (for year 12) |