A driver includes a parameter generation module configured to generate timing parameters based upon a received bit stream. A timing encoding module is configured to determine a plurality of pulse defining parameters based on the timing parameters. A pulse generation module is configured to determine a plurality of generic pulses based on the plurality of pulse defining parameters. The pulse generation module is configured to combine the plurality of generic pulses into a plurality of enable signals. The pulse generation module is configured to selectively invert a first enable signal of the plurality of enable signals. The pulse generation module is configured to output the plurality of enable signals including the first enable signal to a laser driver.
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1. A driver comprising:
a parameter generation module configured to generate timing parameters based upon a received bit stream;
a timing encoding module configured to determine a plurality of pulse defining parameters based on the timing parameters; and
a pulse generation module configured to
determine a plurality of generic pulses based on the plurality of pulse defining parameters,
combine the plurality of generic pulses into a plurality of enable signals,
selectively invert a first enable signal of the plurality of enable signals, and
output the plurality of enable signals including the first enable signal to a laser driver.
14. A driver comprising:
a parameter generation module configured to generate a set of timing parameters based upon a received bit stream;
a timing encoding module configured to create a plurality of pulse defining parameters based on the set of timing parameters; and
a pulse generation module configured to:
create a plurality of generic pulses using the plurality of pulse defining parameters,
combine the plurality of generic pulses into a plurality of enable signals,
selectively replace a first enable signal of the enable signals with an alternative signal, and
output the enable signals with the alternate signal to a laser driver.
16. An optical system comprising:
a laser,
a laser driver in communication with the laser,
a plurality of digital to analog converters configured to supply power information to the laser,
a read/write channel, and
a driver comprising
a parameter generation module configured to generate timing parameters based upon a received bit stream,
a timing encoding module configured to create a plurality of pulse defining parameters based on the timing parameters, and
a pulse generation module configured to
create a plurality of generic pulses using the plurality of pulse defining parameters,
combine the generic pulses into a plurality of enable signals, and
output the enable signals to the laser driver,
wherein the driver (i) receives the received bit stream from the read/write channel and (ii) outputs the enable signals to the laser driver.
2. The driver of
3. The driver of
4. The driver of
a plurality of generic pulse modules configured to generate the plurality of generic pulses, and
a pulse combination module configured to generate the plurality of enable signals by combining selected ones of the plurality of generic pulses.
5. The driver of
6. The driver of
7. The driver of
each the plurality of generic pulse modules is of a first type or a second type, and
the plurality of generic pulse modules of the first type are configured to hold the generic pulses constant after generating the first edges.
8. The driver of
9. The driver of
10. The driver of
11. The driver of
12. The driver of
a clock generator configured to generate a plurality of phase-shifted clocks; and
a coarse timing generator configured to generate the coarse signal based on (i) one of the plurality of phase-shifted clocks and (ii) a coarse parameter of one of the plurality of pulse defining parameters.
13. The driver of
15. The driver of
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This application is a continuation of U.S. patent application Ser. No. 11/455,533, filed Jun. 19, 2006, which claims the benefit of U.S. Provisional Application No. 60/798,598, filed May 8, 2006, and U.S. Provisional Application No. 60/725,968, filed Oct. 12, 2005 which are incorporated herein by reference in their entirety.
The present invention relates to flexible waveform generation, and more particularly to flexible waveform generation for optical systems.
Optical media such as CDs (compact discs) and DVDs (originally, digital versatile discs) are read and written by way of a laser. The laser is driven by a laser driver, which receives waveforms that differ based upon the bit stream to be written and the type and specifications of the optical media. In order to support writing to a wide variety of media, including CD-R, CD-RW, DVD-R, DVD+R, DVD-RW, DVD+RW, and DVD-RAM, a flexible waveform generation scheme is needed.
A driver comprises a parameter generation module, a timing encoding module, and a pulse generation module. The parameter generation module receives a bit stream and generates a set of timing parameters based upon contents of the bit stream. The timing encoding module receives the set of timing parameters from the parameter generation module and creates N sets of pulse defining parameters, wherein N is an integer greater than one. The pulse generation module creates N generic pulses using the sets of pulse defining parameters, combines the generic pulses into P enable signals, and outputs the enable signals to a laser driver, wherein P is an integer greater than one.
In further features, the set of timing parameters includes N edge time parameters, which each determine timing of an initial edge of a corresponding one of the generic pulses. Each of the edge time parameters represents a time delay of the initial edge of the corresponding one of the generic pulses from a previously occurring edge. The pulse generation module comprises N generic pulse modules, which each create a respective generic pulse of the generic pulses, and further comprises a pulse combination module that creates each of the enable signals by programmably combining selected ones of the generic pulses.
In other features, the pulse combination module combines the selected ones of the generic pulses using a logical XOR operation. The pulse combination module includes a first combination module that creates each of a plurality of intermediate pulses by combining at least one of the generic pulses, and the pulse combination module further includes a second combination module that creates each of the enable signals by combining at least one of the intermediate pulses.
In still other features, the pulse generation module further comprises an inversion module that selectively inverts polarity of one of the enable signals before the one of the enable signals is output to the laser driver. The pulse generation module further comprises an output selector module that selectively replaces one of the enable signals with an alternative signal before the one of the enable signals is output to the laser driver. The alternative signal is at least one of a derivative of the bit stream and a clock signal.
In other features, an optical system comprises a laser, a laser driver that communicates with the laser, a plurality of Digital to Analog Converters that supply power information to the laser, a read/write channel, and the driver that receives the bit stream from the read/write channel and that outputs the enable signals to the laser driver. Each of the generic pulse modules create the respective generic pulse by generating a first edge at a time specified by a respective set of the pulse defining parameters.
In further features, each of the generic pulse modules is one of a first type and a second type, and each of the generic pulse modules of the first type holds the respective generic pulse constant after generating the first edge. Each of the generic pulse modules of the second type is capable of generating further edges based upon the respective set of the pulse defining parameters. Each of the generic pulse modules of the second type generates a total number of edges defined by a number contained within the respective set of the pulse defining parameters. Each of the N generic pulse modules generates the first edge using a coarse signal and a fine signal.
In other features, a clock interpolator generates the fine signal based upon a fine parameter of a respective set of the sets of pulse defining parameters. A clock generator generates a plurality of phase-shifted clocks, and a coarse timing generator that generates the coarse signal from one of the plurality of phase-shifted clocks based upon a coarse parameter of a respective set of the sets of pulse defining parameters. The first edge is generated by transmitting the fine signal when the coarse signal is asserted.
In still other features, the timing encoding module includes a first encoder that receives the set of timing parameters, a second encoder that communicates with the first encoder, and a third encoder that communicates with the second encoder. A clock module generates a bit clock at a first frequency and a base clock at a second frequency, wherein the second frequency is a multiple of the first frequency. The first encoder communicates N sets of preliminary pulse defining parameters to the second encoder, and each of the sets of preliminary pulse defining parameters corresponds to one of the generic pulses and includes a coarse enable signal and a phase signal.
In further features, the first encoder asserts the coarse enable signal of one of the sets of preliminary pulse defining parameters during a period of the bit clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the phase signal of the one of the sets of preliminary pulse defining parameters indicates when within the period of the bit clock the edge is desired. The second encoder communicates N sets of intermediate pulse defining parameters to the third encoder, and each of the sets of intermediate pulse defining parameters corresponds to one of the generic pulses and includes a fine enable signal and a fine timing control signal.
In other features, the second encoder asserts the fine enable signal of one of the sets of preliminary pulse defining parameters during a period of the base clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the fine timing control signal of the one of the sets of intermediate pulse defining parameters indicates when within the period of the base clock the edge is desired. The third encoder generates the N sets of pulse defining parameters, each corresponding to one of the generic pulses and including a fine timing control signal and a coarse timing control signal, wherein the fine timing control signal indicates when within a time period described by the coarse timing control signal to generate an edge of the corresponding generic pulse.
In still other features, the parameter generation module generates the set of timing parameters for each mark present in the bit stream. The parameter generation module determines the set of timing parameters based upon at least one of a plurality of defining characteristics of the bit stream, wherein the defining characteristics include mark length, leading space length, and following space length. the parameter generation module includes a plurality of parameter tables and a table index register, wherein the set of timing parameters is generated by selecting parameters from respective ones of the plurality of parameter tables, and wherein the table index register determines which of the defining characteristics are used to select the parameters from the plurality of parameter tables.
In further features, the table index register includes a plurality of control values, each determining which of the defining characteristics are used to select parameters from a corresponding one of the plurality of parameter tables. For each table of the plurality of parameter tables, mark length and following space length are used to select the parameters from the table when the corresponding control value is in a first state, and mark length and leading space length are used to select the parameters from the table when the corresponding control value is in a second state.
A method for controlling a laser driver comprises receiving a bit stream; determining a set of timing parameters based upon contents of the bit stream; creating N sets of pulse defining parameters based upon the set of timing parameters, wherein N is an integer greater than one; generating N generic pulses using the sets of pulse defining parameters; combining the generic pulses into P enable signals, wherein P is an integer greater than one; and outputting the enable signals to the laser driver.
In other features, the set of timing parameters includes N edge time parameters, which each determine timing of an initial edge of a corresponding one of the generic pulses. Each of the edge time parameters represents a time delay of the initial edge of the corresponding one of the generic pulses from a previously occurring edge. The combining includes applying a logical XOR operation to selected ones of the generic pulses. The combining includes creating a plurality of intermediate pulses by combining selected ones of the generic pulses, and creating each of the enable signals by combining selected ones of the intermediate pulses.
In still other features, the method further comprises selectively inverting polarity of one of the enable signals before the one of the enable signals is output to the laser driver. The method further comprises selectively replacing one of the enable signals with an alternative signal before the one of the enable signals is output to the laser driver. The alternative signal is a derivative of the bit stream. The alternative signal is a clock signal. The generating includes making a first edge at a time specified by a respective set of the sets of pulse defining parameters.
In further features, the generating further comprises selectively generating additional edges based upon the respective set of the pulse defining parameters. The generating limits a total number of edges to a number contained within the respective set of the pulse defining parameters. The making includes making the edge at a time determined by a coarse signal and a fine signal. The method further comprises generating the fine signal based upon a fine parameter of a respective set of the sets of pulse defining parameters.
In other features, the method further comprises generating a plurality of phase-shifted clocks, and generating the coarse signal from one of the plurality of phase-shifted clocks based upon a coarse parameter of a respective set of the sets of pulse defining parameters. The making includes transmitting the fine signal when the coarse signal is asserted. The creating comprises creating N sets of preliminary pulse defining parameters from the set of timing parameters, creating N sets of intermediate pulse defining parameters from the sets of preliminary pulse defining parameters, and creating the sets of pulse defining parameters from the sets of intermediate pulse defining parameters.
In still other features, the method further comprises generating a bit clock at a first frequency and a base clock at a second frequency, wherein the second frequency is a multiple of the first frequency. Each of the sets of preliminary pulse defining parameters corresponds to one of the generic pulses and includes a coarse enable signal and a phase signal. The method further comprises asserting the coarse enable signal of one of the sets of preliminary pulse defining parameters during a period of the bit clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the phase signal of the one of the sets of preliminary pulse defining parameters indicates when within the period of the bit clock the edge is desired.
In further features, each of the sets of intermediate pulse defining parameters corresponds to one of the generic pulses and includes a fine enable signal and a fine timing control signal. The method further comprises asserting the fine enable signal of one of the sets of preliminary pulse defining parameters during a period of the base clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the fine timing control signal of the one of the sets of intermediate pulse defining parameters indicates when within the period of the base clock the edge is desired.
In other features, the method further comprises generating the sets of pulse defining parameters, each corresponding to one of the generic pulses and including a fine timing control signal and a coarse timing control signal, wherein the fine timing control signal indicates when within a time period described by the coarse timing control signal that an edge of the corresponding generic pulse is desired. The method further comprises performing the determining for each mark present in the bit stream.
In still other features, the determining is based upon at least one of a plurality of defining characteristics of the bit stream, wherein the defining characteristics include mark length, leading space length, and following space length. The determining includes selecting parameters from respective ones of a plurality of parameter tables based upon the defining characteristics. The determining includes selecting parameters from a table based upon mark length and following space length when a corresponding control value is in a first state, and selecting parameters from a table based upon mark length and leading space length when a corresponding control value is in a second state.
A driver comprises parameter generation means for receiving a bit stream and generating a set of timing parameters based upon contents of the bit stream; timing encoding means for receiving the set of timing parameters from the parameter generation means and creating N sets of pulse defining parameters, wherein N is an integer greater than one; and pulse generation means for creating N generic pulses using the sets of pulse defining parameters, combining the generic pulses into P enable signals, and outputting the enable signals to a laser driver, wherein P is an integer greater than one.
In further features, the set of timing parameters includes N edge time parameters, which each determine timing of an initial edge of a corresponding one of the generic pulses. Each of the edge time parameters represents a time delay of the initial edge of the corresponding one of the generic pulses from a previously occurring edge. The pulse generation means comprises N generic pulse means for creating a respective generic pulse of the generic pulses, and further comprises pulse combination means for creating each of the enable signals by programmably combining selected ones of the generic pulses.
In other features, the pulse combination means combines the selected ones of the generic pulses using a logical XOR operation. The pulse combination means includes first combination means for creating each of a plurality of intermediate pulses by combining at least one of the generic pulses, and the pulse combination means further includes second combination means for creating each of the enable signals by combining at least one of the intermediate pulses. The pulse generation means further comprises inversion means for selectively inverting polarity of one of the enable signals before the one of the enable signals is output to the laser driver.
In still other features, the pulse generation means further comprises output selector means for selectively replacing one of the enable signals with an alternative signal before the one of the enable signals is output to the laser driver. The alternative signal is a derivative of the bit stream. The alternative signal is a clock signal. Each of the generic pulse means create the respective generic pulse by generating a first edge at a time specified by a respective set of the pulse defining parameters. Each of the generic pulse means is one of a first type and a second type, and each of the generic pulse means of the first type holds the respective generic pulse constant after generating the first edge.
In further features, each of the generic pulse means of the second type is capable of generating further edges based upon the respective set of the pulse defining parameters. Each of the generic pulse means of the second type generates a total number of edges defined by a number contained within the respective set of the pulse defining parameters. Each of the N generic pulse means generates the first edge using a coarse signal and a fine signal. The control module further includes clock interpolating means for generating the fine signal based upon a fine parameter of a respective set of the sets of pulse defining parameters.
In other features, the control module further includes clock generating means for generating a plurality of phase-shifted clocks, and coarse timing generating means for generating the coarse signal from one of the plurality of phase-shifted clocks based upon a coarse parameter of a respective set of the sets of pulse defining parameters. The first edge is generated by transmitting the fine signal when the coarse signal is asserted. The timing encoding means includes first encoding means for receiving the set of timing parameters, second encoding means for communicating with the first encoding means, and third encoding means for communicating with the second encoding means.
In still other features, the control module further includes clock means for generating a bit clock at a first frequency and a base clock at a second frequency, wherein the second frequency is a multiple of the first frequency. The first encoding means communicates N sets of preliminary pulse defining parameters to the second encoding means, and each of the sets of preliminary pulse defining parameters corresponds to one of the generic pulses and includes a coarse enable signal and a phase signal. The first encoding means asserts the coarse enable signal of one of the sets of preliminary pulse defining parameters during a period of the bit clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the phase signal of the one of the sets of preliminary pulse defining parameters indicates when within the period of the bit clock the edge is desired.
In further features, the second encoding means communicates N sets of intermediate pulse defining parameters to the third encoding means, and each of the sets of intermediate pulse defining parameters corresponds to one of the generic pulses and includes a fine enable signal and a fine timing control signal. The second encoding means asserts the fine enable signal of one of the sets of preliminary pulse defining parameters during a period of the base clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the fine timing control signal of the one of the sets of intermediate pulse defining parameters indicates when within the period of the base clock the edge is desired.
In other features, the third encoding means generates the N sets of pulse defining parameters, each corresponding to one of the generic pulses and including a fine timing control signal and a coarse timing control signal, wherein the fine timing control signal indicates when within a time period described by the coarse timing control signal to generate an edge of the corresponding generic pulse. The parameter generation means generates the set of timing parameters for each mark present in the bit stream.
In still other features, the parameter generation means determines the set of timing parameters based upon at least one of a plurality of defining characteristics of the bit stream, wherein the defining characteristics include mark length, leading space length, and following space length. the parameter generation means includes a plurality of parameter tables and a table index register, wherein the set of timing parameters is generated by selecting parameters from respective ones of the plurality of parameter tables, and wherein the table index register determines which of the defining characteristics are used to select the parameters from the plurality of parameter tables.
In further features, the table index register includes a plurality of control values, each determining which of the defining characteristics are used to select parameters from a corresponding one of the plurality of parameter tables. For each table of the plurality of parameter tables, mark length and following space length are used to select the parameters from the table when the corresponding control value is in a first state, and mark length and leading space length are used to select the parameters from the table when the corresponding control value is in a second state.
A computer program executed by a processor for operating a laser driver comprising determining a set of timing parameters based upon contents of the bit stream; creating N sets of pulse defining parameters based upon the set of timing parameters, wherein N is an integer greater than one; generating N generic pulses using the sets of pulse defining parameters; combining the generic pulses into P enable signals, wherein P is an integer greater than one; and outputting the enable signals to a laser driver.
In other features, the set of timing parameters includes N edge time parameters, which each determine timing of an initial edge of a corresponding one of the generic pulses. Each of the edge time parameters represents a time delay of the initial edge of the corresponding one of the generic pulses from a previously occurring edge. The combining includes applying a logical XOR operation to selected ones of the generic pulses. The combining includes creating a plurality of intermediate pulses by combining selected ones of the generic pulses, and creating each of the enable signals by combining selected ones of the intermediate pulses.
In still other features, the computer program further comprises selectively inverting polarity of one of the enable signals before the one of the enable signals is output to the laser driver. The computer program further comprises selectively replacing one of the enable signals with an alternative signal before the one of the enable signals is output to the laser driver. The alternative signal is a derivative of the bit stream. The alternative signal is a clock signal. The generating includes making a first edge at a time specified by a respective set of the sets of pulse defining parameters.
In further features, the generating further comprises selectively generating additional edges based upon the respective set of the pulse defining parameters. The generating limits a total number of edges to a number contained within the respective set of the pulse defining parameters. The making includes making the edge at a time determined by a coarse signal and a fine signal. The computer program further comprises generating the fine signal based upon a fine parameter of a respective set of the sets of pulse defining parameters.
In other features, the computer program further comprises generating a plurality of phase-shifted clocks, and generating the coarse signal from one of the plurality of phase-shifted clocks based upon a coarse parameter of a respective set of the sets of pulse defining parameters. The making includes transmitting the fine signal when the coarse signal is asserted. The creating comprises creating N sets of preliminary pulse defining parameters from the set of timing parameters, creating N sets of intermediate pulse defining parameters from the sets of preliminary pulse defining parameters, and creating the sets of pulse defining parameters from the sets of intermediate pulse defining parameters.
In still other features, the computer program further comprises generating a bit clock at a first frequency and a base clock at a second frequency, wherein the second frequency is a multiple of the first frequency. Each of the sets of preliminary pulse defining parameters corresponds to one of the generic pulses and includes a coarse enable signal and a phase signal. The computer program further comprises asserting the coarse enable signal of one of the sets of preliminary pulse defining parameters during a period of the bit clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the phase signal of the one of the sets of preliminary pulse defining parameters indicates when within the period of the bit clock the edge is desired.
In further features, each of the sets of intermediate pulse defining parameters corresponds to one of the generic pulses and includes a fine enable signal and a fine timing control signal. The computer program further comprises asserting the fine enable signal of one of the sets of preliminary pulse defining parameters during a period of the base clock when an edge of the corresponding generic pulse is desired, as specified by the set of timing parameters; and wherein the fine timing control signal of the one of the sets of intermediate pulse defining parameters indicates when within the period of the base clock the edge is desired.
In other features, the computer program further comprises generating the sets of pulse defining parameters, each corresponding to one of the generic pulses and including a fine timing control signal and a coarse timing control signal, wherein the fine timing control signal indicates when within a time period described by the coarse timing control signal that an edge of the corresponding generic pulse is desired. The computer program further comprises performing the determining for each mark present in the bit stream.
In still other features, the determining is based upon at least one of a plurality of defining characteristics of the bit stream, wherein the defining characteristics include mark length, leading space length, and following space length. The determining includes selecting parameters from respective ones of a plurality of parameter tables based upon the defining characteristics. The determining includes selecting parameters from a table based upon mark length and following space length when a corresponding control value is in a first state, and selecting parameters from a table based upon mark length and leading space length when a corresponding control value is in a second state.
In still other features, the methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage and/or other suitable tangible storage mediums.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:
The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present invention.
Referring now to
An exemplary channel bit stream is represented as waveform 102. The waveform 102 contains one bit for every time period T. The portion of the waveform 102 shown in
Marks may be represented on the optical media as areas of low reflectivity (pits), amorphous domains, or any other type or form that can be sensed by the optical system, while spaces may be represented as areas of high reflectivity between marks. These reflectivities may be created by a laser beam that heats the optical media to different temperatures. Heating above a melting temperature disrupts the ordered structure of the optical media, leaving it in an amorphous, low-reflectivity state. Heating the media above a crystallization temperature, but below the melting temperature, allows the media to revert back to an orderly crystal structure that has high reflectivity. Reverting portions of the media back to high reflectivity is termed erasing.
Depending upon the parameters of the optical media, and the binary encoding scheme employed, the length of marks and spaces may be constrained. For example, marks may be no shorter than 2T and no longer than 14T, while spaces may be no shorter than 3T and no longer than 14T. The above-described 8-to-16 conversion produces at least two zeros after a one, and thus the minimum length of a certain state (either mark or space) is 3T. The mark depicted in waveform 102 is 9T long, and is preceded by a space greater than 1T in length and followed by a space greater than 2T in length.
A laser driver sends a waveform to the laser to write the 9T mark 106 to the optical media; an exemplary waveform is depicted at 110. Waveform 110 includes various power levels with respect to zero power level 112. Waveform 110 begins with a first power level Pe, the erase power. Waveform 110 then increases in power for a first pulse at power Pp1. At the end of the first pulse, waveform 110 drops to a base power, Pb. Waveform 110 then contains four 50%-duty-cycle middle pulses, each having a period equal to the bit time T and having a power equal to Pp2. The low times of the middle pulses have power Pb. After the four middle pulses, the waveform 102 contains a last pulse at power Pp3. Waveform 110 then decreases in power to Pcl, the cooling power, which may be greater than or equal to Pb. In this example, however, Pcl is less than Pb. Waveform 110 then returns to the erase power Pe. As further demonstrated below, many other waveforms are possible, and can vary in such features as number and duty cycle of middle pulses, power levels, and presence and number of first or cooling pulses.
Referring now to
The second enable signal EN2 122 corresponds to the first pulse, and is associated with power Pp1-Pb. The third enable EN3 124 corresponds to the four middle pulses, and is associated with power Pp2-Pb. The fourth enable EN4 126 corresponds to the last pulse and is associated with power Pp3-Pb. The fifth enable EN5 128 corresponds to the inverse of the cooling pulse and has an associated power level of Pb-Pcl. Lastly, the sixth enable EN6 130 corresponds to the erase portions of the waveform 110 and has an associated power level of Pe-Pb.
The waveform 110 depicted in
Referring now to
The laser driver 140 includes six switches 150, six multipliers 152, and a summing module 154. The first switch 150-1 receives a first voltage or current from the DACs 144, and also receives the read enable signal. When the read enable signal is high (alternately, the laser driver could work with active low logic), the first switch 150-1 passes the first voltage or current through to the first multiplier 152-1. The first multiplier 152-1 multiplies the incoming voltage or current by a constant K1. The first multiplier 152-1 then communicates that amplified voltage or current to the summing module 154.
The second switch 150-2 receives an enable signal from the write strategy pulse generation module 142 and a second voltage or current from the DACs 144. When the enable signal is high, the switch 150-2 communicates the incoming voltage or current to the second multiplier 152-2. The second multiplier 152-2 multiplies the incoming voltage or current by a constant K2 before passing the signal to the summing module 154. This functionality is repeated by the remaining switches 150-3, 150-4, 150-5, and 150-6, and multipliers 152-3, 152-4, 152-5, and 152-6.
The summing module 154 sums the six amplified inputs, and outputs the result to a laser 156. In this way, the enable signals shown in
The write strategy pulse generation module 142 and DACs 144 may be implemented to match the number of inputs of the laser driver 140. However, it is possible for more enable signals to be generated by the write strategy pulse generation module 142 than can be received by the laser driver 140. Alternately, the laser driver 140 may have more inputs than the write strategy pulse generation module 142 provides.
Referring now to
The second enable signal EN2 122, which defines the first pulse of the driver output waveform 110, is created by a logical XOR of two generic pulses, pulse1_r 160 and pulse1_f 162. The logical XOR operation means that the rising edge of pulse1_r 160 creates the rising edge of EN2, while the rising edge of pulse1_f 162 creates the falling edge of EN2. The time delay from the beginning of the mark, shown as the rising edge in the channel bit stream 102, to the rising edge of pulse1_r 160, is defined by a parameter named dtop. If dtop is negative, the rising edge of pulse1_r will occur prior to the beginning of the mark. The rising edge of pulse1_f 162 is defined to occur a specified period of time, ttop, after the rising edge of pulse1_r 160. The parameter ttop therefore defines the width of the first pulse.
The third enable signal EN3 124 is created from a logical XOR of two generic pulses, pulse2_r 164 and pulse2_f 166. The rising edge of pulse2_r 164 occurs a specified time, dtmp, after the rising edge of pulse1_f 162. Because four middle pulses are desired in EN3 124, pulse2_r and pulse2_f are programmed to have four edge transitions. If, for example, two middle pulses were instead desired, pulse2_r and pulse2_f would each have two edge transitions. After the initial rising edge of pulse2_r 164, a falling edge follows at a time equal to a multiple of T, the bit clock period. The third transition, which is now a rising edge, occurs at another increment of T, while the fourth transition, a falling edge, occurs at a further increment of T.
The first rising edge of pulse2_f occurs a specified time, ttmp, after the first rising edge of pulse2_r 164. The remaining edges of pulse2_f are also spaced in increments of T. The third enable will thus produce pulses with period T, while the duty cycle is determined by ttmp. When ttmp is greater than T/2, the duty cycle of the middle pulses will be greater than 50%. For other optical media, the pulses within pulse2_r164 and pulse2_f166 may have a period that is a multiple of T, such as 2T or 3T.
The fourth enable EN4 126, corresponding to the last pulse of waveform 110, is formed by a logical XOR of pulse3_r 168 and pulse3_f 170. The rising edge of pulse3_r 168 occurs a specified time, dlast, after the final transition of pulse2_f 166. The rising edge of pulse3_f 170 occurs a specified time, tlast, after the rising edge of pulse3_r 168. The fifth enable EN5 128, corresponding to erase power, is formed by the inverse of the logical XOR (XNOR) of erase_r 172 and erase_f 174.
The rising edge of erase_r 172 occurs a specified time, tcool, after the rising edge of pulse3_f 170. The rising edge of erase_f 174 occurs a specified time, derfl, relative to the beginning of the mark (shown as the rising edge in channel bit stream 102). If derfl is negative, the rising edge of erase_f 174 will occur before the beginning of the mark. The sixth enable EN6 130, corresponding to the cool pulse, is formed by the inverse of the logical XOR (XNOR) of pulse3_f 170 and erase_r 172. Finally, a reset pulse 176 occurs after the end of the mark. The falling edge of the reset pulse 176 synchronously resets all of the generic pulses 160, 162, 164, 166, 168, 170, 172, and 174.
Referring now to
The laser driver 196 also receives a read enable signal from the control module 190 and power level information in the form of voltage and/or current signals from the DACs 192. The laser driver 196 combines the power levels based upon the enable signals and transmits the result to a laser 198. The control module 190 performs a variety of functions, including determining when the laser driver 196 should be reading or writing to the optical media, and coordinating calibration of power level and timing information for the current optical media.
An optical sensor 202 gathers information from the laser 198 as reflected by the optical media. This information is communicated to a preamplifier 204, which communicates an amplified form of the information to the control module 190. The control module 190 may calibrate the power level information and/or the timing information. This can be done, for example, upon system power-on, at the time of manufacturing, at periodic intervals, when parameters of interest (such as temperature) change, and/or when a new type or instance of optical media is introduced. The control module 190 may write test patterns to a portion of the optical media and read them back to determine the efficacy of calibration parameters. The control module 190 may begin calibration using a default set of parameters stored for each type of optical media or from previously determined values.
Referring now to
The PLL and clock recovery module 212 generates a stable clock signal, as well as divided clocks to accommodate slower writing speeds. Clock information is communicated to the lookup table 210, the timing encoding module 214, and the pulse generation module 216. The timing encoding module 214 receives parameters from the lookup table 210 and encodes these parameters into precise timing instructions that are communicated to the pulse generation module 216. The lookup table 210 may be implemented as a table that looks up parameters based upon characteristics of the write data bit stream, a set of calculations performed on the characteristics, or a combination of both approaches. A combined approach may involve a set of base parameters stored in a table that are altered programmatically by mathematical operations. The pulse generation module 216 generates edges based on the commands from the timing encoding module 214 and combines these pulses to create the enable pulses, which are communicated to the laser driver 196.
Referring now to
Selections are made from the tables 220 and 222 based upon parameters such as mark length (in units of the channel bit clock T), leading space length (i.e., the length of the space prior to the current mark) and following space length (i.e., the length of the space following the current mark). The lookup table 210 includes a control module 234 that receives the write data bit stream. The control module 234 analyzes the incoming bit stream to determine when marks and spaces will need to be written.
Before the length of a mark can be determined and a table entry chosen, the control module 234 must receive the end of the mark. Further, if the table entry depends upon the length of the following space, the control module 234 must wait until the current mark ends, and the next begins (thus demarcating the end of the following space). The original incoming bit stream may be in raw 0s and 1s (NRZ), or may already have been converted to NRZI. If not converted to NRZI, the control module 234 may perform this function—conversion can entail ending the current mark or space (and thus starting the next space or mark, respectively) for each one value in the NRZ bit stream. Data is typically written to optical media in NRZI format, and thus the waveforms depicted are NRZI, though the write strategy according to the principles of the present invention is not limited to NRZI waveforms.
Referring now to
Likewise, table 240 can include table entries for leading space lengths of 3T through 6T, and the 6T entry is used if the leading space is longer than 6T. If, for instance, the leading space length is 4T and the mark length is 10T, table entry x12 is used. Table entry x12 corresponds to a specific set of values for parameters derfl, dtop, ttop, dtmp, and ttmp. Similarly, for a mark length of 3T and a leading space length of 5T, the values stored at table entry x14 will be used.
A second exemplary table 242 contains values for the mpcount parameter. Table 242 includes entries for mark lengths (depicted as columns) from 2T to 14T, and the 14T entry will be used if the mark length is greater than 14T. Table 242 includes entries for leading space lengths (depicted as rows) from 3T to 6T, and the 6T entry will be used if the leading space length is greater than 6T. For instance, with a mark length of 7T and a leading space length of 7T, the value of mpcount at table entry y45 will be used.
A third exemplary table 244 contains values for dlast, tlast, and tcool parameters. Table 244 includes entries for mark lengths from 2T to 14T, with mark lengths greater than 14T using the 14T entry. Table 244 includes entries for following space lengths from 3T to 6T, with space lengths greater than 6T using the 6T entry. For a mark length of 7T and a following space length of 5T, for example, the values of dlast, tlast, and tcool stored at table entry z32 will be used. If any of the tables within the group 238 is desired to have entries for space length of 2T instead of 3T, the table can be modified so that the space length entries are for 2T, 3T, 4T, and 5T+. Alternately, the table entries can be adapted for spaces of 2/3, 4, 5, and 6T+ where 2/3 means that the same entry is used whether the space length is 2T or 3T. Further, as described more fully below, whether the tables within the group 238 are indexed by following space length or by leading space length can be made programmable.
Referring now to
A table index register 260 can define how tables 250, 252, 254, 256, and 258 are indexed to select a parameter. For instance, each table 250, 252, 254, 256, and 258 may correspond to a bit within the table index register 260. Each bit in the table index register 260 can determine whether the corresponding table indexes based upon following space length or leading space length. This increases the flexibility of the write strategy by allowing the indexing of each parameter or group of parameters to be altered programmatically. Bits within the table index register 260 may also control which length values correspond to which table entries. For instance, a bit may specify whether the rows of the table correspond to space lengths of 2T, 3T, 4T, and 5T+, respectively, or to 3, 4, 5, and 6T+, respectively.
Referring now to
The analog PLL VCO 302 generates multi-phase clocks that are separated by 45 degrees: vclk0, vclk45, vclk90, vclk135, vclk180, vclk225, vclk270, and vclk315. The clock with zero-degree phase shift, vclk0, is communicated to an N divider module 304. The N divider module 304 divides vclk0 by an integer N, where N is often a power of two. Dividing a clock by N means dividing its frequency by N, while its period is multiplied by N. vclk0/N is the channel bit clock; in other words, the frequency of vclk0/N is the same frequency as the channel data rate.
The N divider module 304 is used so that the voltage-controlled oscillator 302 does not have to vary across a wide range. The frequency variation of the VCO 302 can be limited because large changes in frequency are accomplished through dividing the frequency produced by the VCO 302. An exemplary mapping between data rate and divisor N may be used as follows:
Data Rate
N
8 MHz to 16 MHz
32
16 MHz to 32 MHz
16
32 MHz to 64 MHz
8
64 MHz to 128 MHz
4
128 MHz to 256 MHz
2
256 MHz to 620 MHz
1
The N divider module 304 may provide one or more divided clocks to a retiming module 306. In the exemplary implementation of
The write pulse pattern lookup table 210 receives a bit stream of the data to be written to the optical media. The lookup table 210 also receives the channel bit clock vclk0/N. The appropriate pulse parameters, such as those depicted in the lookup table of
The edge generators 312 receive the multiple phases from the analog VCO 302 and the divided clocks 308. The edge generators 312 each generate a generic pulse. These pulses are all communicated in parallel to pulse combining logic 314, which combines the generic pulses into enable signals used to drive the laser driver shown in
Referring now to
Generators of type B produce generic pulses such as pulse2_r 164 and pulse2_f 166 in
Each edge generator 320 receives the multiple phases of the voltage-controlled oscillator and also receives a pulse reset signal (pulse_rst). Operation of the pulse reset signal is depicted in
Each edge generator 320 outputs its created generic pulse (denoted P1 through P8) to the pulse combining logic module 314. The pulse combining logic module 314 then combines the generic pulses from the edge generators 320 into enable signals that are communicated to the laser driver. In this implementation, six enable signals, EN2 through EN7, are depicted. The pulse combining logic 314 may include combinational and/or sequential circuitry. Greater or fewer number of enable signals may be created, and the pulse combining logic 314 may be programmable to allow creation of combinations of various numbers of generic pulses using various logic functions and/or transformations such as delays.
In one implementation, there are six intermediate values whose calculation can be programmed via six two-bit registers. These six intermediate values are named enable XORs, EN2_XOR, EN3_XOR, EN4_XOR, EN5_XOR, EN6_XOR, and EN7_XOR. Formation of each of the intermediate values is determined by the contents of a two-bit selection register. The following is an exemplary implementation, though more or less flexibility may be provided for. Generic pulses P1, P2, P3, P4, P5, P6, P7, and P8 may correspond to pulse1_r 160, pulse1_f 162, pulse2_r 164, pulse2_f 166, pulse3_r 168, pulse3_f 170, erase_r 172, and erase_f 174, respectively, of
EN2_XOR_SEL[1:0]
00
P1 XOR P2
01
P7 XOR P2
10
P1 XOR P5
11
P7 XOR P5
EN3_XOR_SEL[1:0]
00
P3 XOR P4
01
P1 XOR P4
10
P3 XOR P6
11
P1 XOR P6
EN4_XOR_SEL[1:0]
00
P5 XOR P6
01
P7 XOR P6
10
P5 XOR P2
11
P7 XOR P2
EN5_XOR_SEL[1:0]
00
P7 XOR P8
01
P6 XOR P8
10
P7 XOR P1
11
P6 XOR P1
EN6_XOR_SEL[1:0]
00
P6 XOR P7
01
P5 XOR P7
10
P6 XOR P2
11
P5 XOR P2
EN7_XOR_SEL[1:0]
00
(CK0_div2 XOR P8_div2 + NRZI * !P1) * !(P1 XOR P7) * !(P7 *
NRZI_DLY_1T)
01
(CK0_div2 XOR P8_div2 + NRZI * !P1 + P7 * NRZI_DLY_1T) *
!(P1 XOR P7)
10
(CK0_div2 XOR P8_div2) * !NRZI * !NRZI_DLY_1T
11
(CK0_div2 XOR P8_div2) * !NRZI * !NRZI_DLY_1T +P7 *
NRZI_DLY_1T
Based upon the above programming, EN2_XOR, for example, can be formed from one of four choices. If the selection bits are 00, EN2_XOR will be formed from the logical XOR of P1 and P2, which are the generic pulses arriving from edge generators 320-1 and 320-2, respectively. If the selection bits are 01, EN2_XOR will be formed from a logical XOR of P7 and P2. Likewise, selection bits 10 create the logical XOR of P1 and P5, while selection bits 11 select the XOR of P7 and P5. Intermediate values EN3_XOR through EN6_XOR operate similarly.
The last intermediate value, EN7_XOR, is formed from more complicated logical expressions, which allows for the creation of more complex waveforms, such as pulsed erase waveforms. CK0 is the channel bit clock, and CK0_Div2 is the bit clock divided by two; i.e., half the frequency of CK0. P8_Div2 is P8 divided in frequency by two. In various implementations, P8 can be generated as CK0 with a programmable phase shift. In this way, when a divided P8 is XOR'd with a divided CK0, a square wave can be created. The duty cycle of the square wave is controlled by the amount of phase shift between P8 and CK0. NRZI represents the incoming non-return-to-zero-inverted channel write bit stream. The exclamation point indicates a logical not, while _DLY—1T signifies a delay by a time of 1T (one channel bit period). A graphical depiction of these waveforms is presented in
Outputs of the pulse combining logic module 314 may be created from combinations of the intermediate values. In one implementation, there is a six-input summing module for each enable output. A crossbar switch can be placed between the intermediate values and the inputs of the six-input summing modules. Each six-input summing module is programmable to add any combination of its six inputs together. There may be an additional stage of logic that can invert the outputs prior to leaving the pulse combining logic module 314. For example, in
Referring now to
The complex combination logic module 327 receives pulse 1, pulse 7, and pulse 8, as indicated by the choices above for EN7_XOR_SEL[1:0]. The combination that the complex combination logic module 327 performs is determined by EN7_XOR_SEL. The output of the complex combination logic module 327 is communicated to the cross-bar switch 323. Each multiplexer 321 has two inputs and communicates its output to a corresponding XOR module 322. Outputs of the XOR modules 322 are communicated to inputs of the switch 323.
The inputs to the multiplexers 321 are derived from the generic pulses arriving at the pulse combining logic module 314. In this implementation, inputs of the multiplexers 321 match up with the enable select bits shown above. For example, EN2_XOR_SEL[1:0] selects whether P1 or P7 is XOR'd with P2 or P5. Therefore, one multiplexer 321 will have inputs of P1 and P7, while the other multiplexer corresponding to that XOR gate 322 will have inputs of P2 and P5. This pattern is repeated for the remaining multiplexers 321 and XOR gates 322. The cross-bar switch 323 has six inputs and 36 outputs, six for each selective addition module 324. The cross-bar switch 323 can route any input to any output.
Each selective addition module 324 can add any combination of its inputs, and the output is communicated to a polarity inversion module 325. With binary values, addition is the equivalent of a logical OR operation. The polarity inversion module selectively inverts the polarity of the signal (useful for such enable signals as EN5 128 in
Referring now to
The write strategy timing encoding module 214 contains three encoders, encoder 1 330, encoder 2 332, and encoder 3 334. Encoder 1 330 receives pulse parameters from the lookup table 210, and transmits eight sets of parameters to encoder 2 332, which transmits eight sets of parameters to encoder 3 334. Encoder 3 334 outputs eight sets of coarse and fine timing controls to the eight edge generators 312 of
The write strategy timing encoding module 214 converts the parameters from the lookup table 210 into coarse and fine timing parameters. For example, the time dtop (measured in units of T, the channel bit clock period) will be converted into coarse and fine timing parameters (such as P_CCTL1 and P_INT1) that define the rising edge of pulse1_r 160, depicted in
Encoder 1 330 operates in the channel bit clock domain and therefore receives vclk0/N. At each incoming clock cycle, encoder 1 will output a single enable bit, TD1, and a seven-bit phase group P_1[6:0]. These signals refer to the edge that will be generated for pulse1_r 160. If the rising edge of pulse1_r is to occur in the current clock cycle, TD1 will have the value one for the current clock cycle. If the rising edge of pulse1_r 160 is not to occur in this clock cycle, TD1 will be zero. The value of P_1 determines when within this clock cycle the rising edge of pulse1_r will occur.
Encoder 2 332 receives information from encoder 1 in the channel bit clock domain and receives vclk0/N. Encoder 2 outputs data in the vclk0 domain, which is at a frequency N times higher than the channel bit clock. Encoder 2 332 outputs a single enable bit TVCO_TD1 and a seven-bit phase value P_INT1[6:0]. TVCO denominates that this signal is in the VCO clock domain (vclk0), as opposed to the channel bit clock domain (vclk0/N). INT is an abbreviation for interpolator because the seven-bit P_INT1 value will be used by a phase interpolator to place the edge.
Because TVCO_TD1 is in the vclk0 domain, encoder 2 332 will output a one on TVCO_TD1 when an edge should occur during this vclk0 cycle, and a zero otherwise. The P_INT1 value determines where within the current vclk0 cycle the edge should occur. Because there are N vclk0 cycles within each bit clock cycle, the phase information P_1 from encoder 1 is multiplied by N. This is discussed in more detail with respect to
Encoder 3 operates in the vclk0 domain, and, therefore, receives vclk0. Encoder 3 334 transmits P_INT1 from encoder 2 332 unchanged. Encoder 3 334 also generates a coarse timing control value P_CCTL1 [3:0]. The coarse timing control value selects one of four phases of the vclk signal, specifically, vclk0, vclk90, vclk180, and vclk270. The coarse timing control signal serves to gate the output of the phase interpolator because the phase interpolator may experience glitches as the fine timing control information changes from one setting to the next (the fine timing control settings can change for each mark written). In various implementations, P_CCTL1[3:0] may be formed from the binary decoding of P_INT1[6:5].
Referring now to
Exemplary phase information output from Encoder 1 is depicted at 366. The fine timing information 366 is asserted in the cycle 367 in which the edge is desired to be generated. The fine information may be sent starting in the first bit period so that the phase interpolator can receive the fine timing information as soon as possible to stabilize. In this example, the fine timing information is seven bits long, with the most significant bits being 01.
The single enable bit, TVCO_TD, output from Encoder 2 is depicted at 368. TVCO_TD will be zero in all cycles except for the VCO clock cycle where the edge is desired. In VCO clock cycles when TD is zero, TVCO_TD must also be zero. Only in the channel bit clock cycle 360 where the edge is desired can TVCO_TD be one. Because there are four (22) TVCO cycles in one bit period, the two most significant bits of the fine pulse information P—[6:0] determine in which TVCO cycle the edge will occur within the chosen bit period. In this example, the two most significant bits are 01, the decimal value of one, which means that TVCO cycle number one 367 will contain the edge (with TVCO cycles 0, 1, 2 and 3).
The second encoder outputs fine phase interpolator information P_INT[6:0]. This phase information determines where within the TVCO clock cycle 360 the edge will fall. Because the two most significant bits were used in selecting the TVCO cycle, those digits are removed and the remaining bits are left-shifted by two. Therefore, the five least significant bits of P—[6:0] are now the five most significant bits of P_INT[6:0], and the two least significant bits are zero. The phase information P_INT[6:0] may be asserted as soon as the corresponding P—[6:0] phase information is received (the first TVCO cycle), as shown in
P_INT[6:0] is depicted in
The edge generator receiving P_CCTL[3:0] generates a coarse timing control signal CTCTL. This signal has a rising edge at the appropriate phase clock, as determined by P_CCTL. The CTCTL 374 generated by an edge generator of type A may have a falling edge after a time of at least TVCO. The CTCTL 376 generated by an edge generator of type B will have additional edges, as determined by mpcount. Mpcount determines the total number of edges, including the initial rising edge. The edges are spaced apart by the period of the middle pulses. In the example shown in
The phase interpolator information P_INT[6:0] determines where within the CTCTL pulse the rising edge will occur. The rising edge will occur at the same time whether a generated pulse 378 is created by Edge Generator A or a generated pulse 380 is created by Edge Generator B. However, if Edge Generator B is used, further edges may be created as dictated by the corresponding CTCTL signal 376. The rising edge generated in pulse 378 or 380 occurs at the next interpolated clock edge (as specified by P_INT[6:0]) after the corresponding CTCTL changes.
For a more detailed understanding of how Encoder 2 operates, a description is provided for each clock divider N selected from 1, 2, 4, 8, 16, and 32. If N is 1, then T=TVCO. Because T and TVCO are the same, TVCO_TD=TD and P_INT[6:0]=P—[6:0]. If N is greater than 1, there are N TVCO for each T, and T=N*TVCO. When an edge is desired within a bit clock period, TD=1 for that period. If N=2p, P—[6, 5, . . . , {6−(p−1)}] is binary decoded to determine to which TVCO cycle the edge belongs within the chosen bit clock period. The fine timing information is then P_INT[6:0]={P—[6−p], P—[6−(p+1)], . . . , P—[0], 0, . . . , 0]. In essence, the second encoder left-shifts the fine pulse timing information by log base 2 of the clock divider (filling shifted least significant bits with zeros), and outputs 1 (on TVCO_TD) during the appropriate TVCO cycle period.
If N=2, T=2TVCO. When an edge is desired within a particular clock cycle T, P—[6] is binary decoded to determine to which TVCO the edge belongs within that T. For example, if the sequence of TD in five T cycles is 00100, there is an edge in the third T cycle. If P—[6] is 1, the edge will be generated in the second of the two TVCO periods, and the TVCO_TD sequence for ten TVCO cycles (five T cycles) should be 0000010000. If P—[6] is 0, the TVCO_TD sequence for ten TVCO cycles should be 0000100000. The mapping from P—[6:0] to P_INT[6:0] is P_INT[6:0]={P—[5], P—[4], P—[3], P—[2], P—[1], 0}.
If N=4, T=4TVCO. When an edge is desired within a particular T, P—[6, 5] is binary decoded to determine to which TVCO the edge belongs within that T. The mapping is P_INT[6:0]={P—[4], P—[3], P—[2], P—[1], P—[0], 0, 0}. For example, if the sequence for TD in five T cycles is 00100, the twenty TVCO cycles of TVCO_TD are determined by the decoding of binary P—[6, 5] according to the following table:
P_[6,5]
TVCO_TD sequence
00
00000000100000000000
01
00000000010000000000
10
00000000001000000000
11
00000000000100000000
If N=8, T=8TVCO. When an edge is desired within a particular T, P—[6, 5, 4] is binary decoded to determine which TVCO the edge belongs to within that T. The mapping is P_INT[6:0]={P—[3], P—[2], P—[1], P—[0], 0, 0, 0}. If N=16, T=16TVCO. When an edge is desired within a particular T, P—[6, 5, 4, 3] is binary decoded to determine to which TVCO the edge belongs within that T. The mapping is P_INT[6:0]={P—[2], P—[1], P—[0], 0, 0, 0, 0}. If N=32, T=32TVCO and the mapping is P_INT[6:0]={P—[1], P—[0], 0, 0, 0, 0, 0}.
An exemplary implementation of Encoder 3 is explained in detail here. Assume that TVCO_TD has a sequence of 010 in three TVCO cycles. If these cycles are named TVCO(i−1), TVCO(i), and TVCO(i+1), the TVCO_TD of 1 in cycle TVCO(i) indicates an edge should be generated in cycle TVCO(i). The operation of Encoder 3 is then described by the following exemplary table, which gives P_CCTL[3:0] for the three TVCO cycles (P_CCTL[3:0] is zero for all other cycles) based upon the value of P_INT[6:0]:
TVCO(i − 1)
TVCO(i)
TVCO(i + 1)
1110000 < P_INT[6:0] ≦ 1111111
P_CCTL[3:0]:
0000
0100
0000
1010000 < P_INT[6:0] ≦ 1110000
P_CCTL[3:0]:
0000
0010
0000
0110000 < P_INT[6:0] ≦ 1010000
P_CCTL[3:0]:
0001
0000
0000
0010000 < P_INT[6:0] ≦ 0110000
P_CCTL[3:0]:
1000
0000
0000
0000000 < P_INT[6:0] ≦ 0010000
P_CCTL[3:0]:
0100
0000
0000
Referring now to
The OR gate 426 also receives an output of the D flip-flop 428. In this way, once the output of the D flip-flop 428 has gone high, the OR gate 426 will cause the input of the D flip-flop 428 to always remain high. In order to reset the D flip-flop 428, a pulse reset signal (pulse_rst) is provided and the D flip-flop 428 resets to zero upon the falling edge of the pulse_rst signal. The phase interpolator 424 receives the fine pulse timing information, P_INT[6:0], and the multiple phases of the VCO. The phase interpolator interpolates a clock, based upon P_INT[6:0], in between the multiple phases of the VCO, and outputs this fine clock signal to the clock input of the D flip-flop 428. In this way, once CTCTL is high, the incoming rising edge of the next fine clock from the phase interpolator 424 will cause the output of the D flip-flop 428 to go high.
Referring now to
Once CTCTL is asserted by the coarse timing generator 442, the next clock edge received by the D flip-flop 446 will cause the high CTCTL signal to be propagated to the output of the flip-flop 446. The clock is communicated to the flip-flop 446 by the phase interpolator 444. The phase interpolator 444 receives multiple phases of the VCO (such as the 45 degree separated phases described with respect to
Referring now to
The desired CTCTL is chosen based upon when the pulse edge is desired. Because the CTCTL signal serves as the input to the D flip-flop 428 in
For equal setup and hold times, if the generic pulse edge is desired within an interval A demarcated in
If an edge is desired during time interval B, the CTCTL corresponding to vclk90 can be selected using a P_CCTL of 0010. Likewise, a P_CCTL of 0100 will select the CTCTL corresponding to vclk180, beneficial for an edge in time period C2. If a P_CCTL of 0100 is asserted in the previous cycle, the CTCTL 492 is beneficial for an edge in time period C1. A P_CCTL of 1000 in the previous cycle will select the CTCTL 494 corresponding to vclk270, useful for an edge occurring in time period D. The CTCTLs depicted in
Referring now to
The outputs of the D flip-flops 524 are communicated to the OR gate 526. An output of the OR gate 526 is output from the coarse timing generator as the coarse timing control (CTCTL) signal. By definition, only one bit of P_CCTL[3:0] will be high at any one time, and therefore, only one output of the D flip-flops 524 will be high at a time. As soon as the output of one of the D flip-flops 524 goes high, the OR gate causes the output CTCTL to go high. Once the next value of P_CCTL[3:0] is clocked into the register 522, it will be all zeros (by definition, only one value of P_CCTL[3:0] will be nonzero for each generated edge) and, therefore, the D flip-flop 524 that was responsible for the high value output from the OR gate 526 will fall to zero once the new zero value is clocked into the D flip-flop by its corresponding vclk phase. Because the vclk phases operate at a period of TVCO, the initial rising edge and falling edge will be separated by TVCO as depicted in
Referring now to
The coarse timing generator 560 also includes an OR gate 570, an MTW counter 572, an MP counter 574, and three multiplexers, multiplexer A 576, multiplexer B 578, and multiplexer C 580. The OR gate 570 has four inputs, each receiving one of the bits of P_CCTL[3:0] from the write strategy timing encoding module 214. The output of the OR gate 570 is communicated to a selection input of multiplexer C 580, a start input of MTW counter 572, and a start input of MP counter 574. Vclk0 serves as the clock for the register 564, the write strategy timing encoding module 214, and the MTW counter 572.
The MTW counter 572 counts the number of VCO cycles in between each edge asserted on CTCTL. If there are N VCO clock cycles within each channel bit clock cycle, the value the MTW counter 572 would count to would be N, or starting from zero, would be N−1. For different write strategies, however, the CTCTL edges may be spaced at multiples of the channel bit period T, such as 2T or 3T.
This multiplier is called MTW, and the value the MTW counter must reach is N times MTW minus one (count starts from zero). Once two abstract pulses created from similar CTCTLs are XOR'd, the multiple of T spacing of pulse edges will translate into the same multiple of T period for the generated middle pulses. To create a middle pulse period of 1T, the waveform generated at CTCTL should have a period equal to 2T. Once the MTW counter 572 reaches MTW*N−1, an output of the MTW counter 572 is asserted and the MTW counter 572 returns to zero and resumes counting.
The output of the MTW counter 572 serves as the clock of the MP counter 574 and as a selection input of multiplexer A 576. MP counter 574 counts the number of edges in CTCTL which, once combined with a similar pulse, will create 2*mpcount edges (mpcount pulses). The value MP counter 574 counts to is therefore mpcount. The MTW counter 572 returns to zero in the clock cycle after the start signal is received, and begins counting from zero. MP counter 574 is a saturation counter, and once it reaches its target value, it remains at that value. An output of MP counter 574 is high once the target value has been reached. The output of MP counter 574 serves as a selection input of multiplexer B 578, and as a stop signal for the MTW counter 572.
The stop signal freezes the MTW counter 572 at the current count value, or alternately could return the count to zero. The stop signal is asserted once the number of pulses counted by MP counter 574 has reached the final value. Once this value is reached, power can be saved by preventing the MTW counter 572 from continuing to count and continuing to switch multiplexer A 576. Multiplexer A 576 alternates between passing the current value of the register 564 and an inverted value of the register 564. Input zero of multiplexer A 576 is received from the output of the register 564, and input one of multiplexer A 576 is the bitwise inverse of the output of the register 564. An output of multiplexer A 576 is received by multiplexer B 578 at input zero. Input one of multiplexer B 578 is the output of the register 564. Multiplexer C 580 receives an output of multiplexer B 578 at input zero. Input one of multiplexer C 580 is P_CCTL[3:0], received from the write strategy timing encoding module 214.
Multiplexer C 580 passes through the value selected by multiplexer B 578 unless one of the bits of P_CCTL[3:0] is asserted, in which case multiplexer C 580 passes the value of P_CCTL[3:0]. Multiplexer B 578 usually passes the output of multiplexer A 576. Once the target value of the MP counter 574 is reached (meaning that all edges have been produced and the value of CTCTL should remain steady), multiplexer B 578 then passes the current value of the register 564. This means that the value sorted in the register 564 will remain constant once the output of MP counter 574 has gone high; this will last until the next mark is generated, and a new non-zero P_CCTL[3:0] is received.
Multiplexer A 576 passes the current value of the register 564 unless the value of MTW counter 572 has reached its target count. MTW counter 572 reaches its target count after MTW*N clock cycles. This corresponds to the spacing desired for the edges of CTCTL. When the MTW counter 572 reaches its target count, and the output of the counter 572 selects the inverted input of multiplexer A 576, the value in the register 564 is inverted. The MTW counter 572 then resumes counting at zero and its output, now low, selects the non-inverted input of multiplexer A 576. In this way, the value in the register 564 is inverted each time MTW counter 572 reaches its target count. Because the multiplexer 566 only selects one flip flop, the inversion of the register 564 is seen as an edge on CTCTL.
Referring now to
The first two rows of the table 600, VCO cycles 1 and 2 show the coarse timing generator 560 at steady state. Column 610-3 contains the value of the register 564. Column 610-4 is a representation of the value of CTCTL. CTCTL may not have the same clock phase as the other values shown in table 600. Depending upon which bit of P_CCTL is set, the CTCTL may have a phase shift from vclk0. Column 610-4 depicts CTCTL, the output of the coarse timing generator 560. Because MP count is 3, there should be three edge transitions, shown here at VCO cycles 4, 8, and 12. Because MTW is 1 and N is 4, there should be 4×1 clock cycles at each value. This is the case as clock cycles 4 through 7 are one, and clock cycles 8 through 11 are zero. Column 610-5 lists the start signal. This signal is output by the OR gate 570 and communicated to the start inputs of the counters 572 and 574.
Column 610-6 includes two sub-columns, the internal count value of the MTW counter 572 and the output of the MTW counter 572. It can be seen that the output of the MTW counter 572 is one once the target value of three is reached (cycles 7, 11, 15, etc.), and zero otherwise. The count value begins at zero, continues to three and returns to zero until cycle 15, when the stop signal is received. The stop signal is received from the output of MP counter 574. At this point, the internal count value remains constant.
Column 610-6 includes two sub-columns, the internal count value of the MP counter 574 and the output of MP counter 574. The count value of MP counter 574 increases by one each time the output of the MTW counter 572 goes high. Once the MP counter reaches its target value (in this case 3, reached at cycle 15), the count value remains constant and the output goes high. Column 610-7 includes three sub-columns, the zero input, the one input, and the output of multiplexer A 576. Column 610-8 includes three sub-columns, the zero input, the one input, and the output of multiplexer B 578. Column 610-9 includes three sub-columns, the zero input, the one input, and the output of multiplexer C 580.
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EN2 923 can be formed from the logical sum of three generic pulses, and is associated with power Pp1-Pb. EN3 924 is associated with Pe1-Pb, EN4 925 with Pb-Pcl, and EN5 934 with Pe2-Pe1. Based upon register settings, one of four EN5s may be chosen: 934-1, 934-2, 934-3, and 934-4. Enable choices 934-1 and 934-2 each have a third pulse that creates the shaded portion 922-1 in the laser driver output 921. The second and fourth choices of EN5, 934-2 and 934-4, have a second to last pulse that is wider, corresponding to the shaded portion 922-2 of the laser driver output 921. The choice between EN5s 934 may be made based upon the type of optical media, and can be determined during calibration.
To visually demonstrate an exemplary calculation of EN5s 934 based on expressions given above, various waveforms are presented. CK0_div2 926 is the channel bit clock divided in frequency by 2. P8_div2 927 is the eighth generic pulse, P8, divided in frequency by 2. In various implementations, P8 is programmed to include a phase-shifted version of the channel bit clock. The logical XOR of CK0_div2 and 926 P8_div2 927 is represented at 928. The NRZI channel bit stream, delayed by one bit time period is depicted at 929. The inverse of the NRZI channel bit stream is depicted at 930. The first generic pulse, P1, is depicted at 931. P1 931 may correspond to pulse1_r 160 of
Referring now to
EN3 948 may be created from the logical addition of two generic pulses, and is associated with power Pp1-Pb. EN4 950 can be formed from the inversion of the logical sum of two generic pulses, and is associated with power Pb-Pc1. If the cooling power were greater than the base power, the waveform of EN4 950 would be inverted from that shown, and could be formed from the logical addition of two generic pulses. EN2 946 is associated with power dPw3. The pulse EN2 946 can be programmed so that it is only present when writing a mark of width 3T. When present, EN2 946 causes the shaded area 944 of the laser driver output to be asserted, and, therefore, the first pulse power will be Pp1+dPw3, not Pp1. Similar provision can be made for different power levels required by different mark widths, different space widths, or other suitable factors.
Referring now to
The read/write channel module 990 includes a write strategy implementation according to the principles of the present invention, and a series of DACs (Digital to Analog Converters) that communicate signals to a laser driver 991 within the optical media assembly 978. The read/write channel module 990 receives signals from a preamplifier 992 within the optical media assembly 978. The spindle/FM driver 989 controls a spindle motor 993 and a feed motor 994 within the optical media assembly 978. An optical read/write device 996 receives signals from the feed motor 994 and the laser driver 991, and communicates signals to the preamplifier 992.
The optical media assembly 978 also includes an optical media platter 998 that stores data optically. The platter 998 is rotated by the spindle motor, schematically shown at 993. The spindle motor 993 rotates the optical media platter 998 at a controlled and/or variable speed during read/write operations. The optical read/write device 996 moves relative to the optical media platter 998 to read and/or write data to/from the optical media platter 998. The optical read/write device 996 typically includes a laser and an optical sensor.
Volatile memory 981 functions as a buffer, and may employ SDRAM (Synchronous Dynamic Random Access Memory) or other types of low-latency memory. Non-volatile memory 982, such as flash memory, can be used for data relating to optical media write formats and/or other non-volatile control code. Additionally, the non-volatile memory 982 may include write pulse pattern constants that serve as a starting point when calibrating the look-up table used by the write strategy implementation. The processor 983 performs data and/or control processing related to the operation of the optical media system 970. The processor 983 may also perform decoding of copy protection and/or compression/decompression as needed.
During write operations, the read/write channel module 990 encodes the data to be written by the optical read/write device 996. The read/write channel module 990 processes the signals for reliability purposes and may apply, for example, ECC (Error-Correcting Code), RLL (Run Length Limited) encoding, and the like. During read operations, the read/write channel module 990 converts an analog output of the optical read/write device 996 to a digital signal. A converted signal is then detected and decoded by known techniques to recover the data that was written on the optical media.
The codec module 986 encodes and/or decodes video, such as MPEG formats. Audio and/or video DSPs 242 and 244 perform audio and video signal processing, respectively. The optical read/write device 996 is directed at grooves and/or lands containing marks and spaces. During write operations, the optical read/write device 996 may use a laser to heat a die layer on the optical media platter 998. If the die is heated to one temperature, the die is transparent and represents one binary digital value. If the die is heated to another temperature, the die is opaque and represents the other binary digital value. Other techniques for writing optical media may also be employed.
The spindle/FM driver 989 controls the spindle motor 993, which controllably rotates the optical media platter 998. The spindle/FM driver 989 also generates control signals that position the feed motor 994, for example, using a voice coil actuator, a separate motor, or any other suitable actuator. The feed motor 994 typically moves the optical read/write device 996 radially relative to the optical media platter 998. The preamplifier 992 amplifies analog read signals from the optical read/write device 996.
Portions of the optical media system 970 may be implemented by one or more integrated circuits (IC) or chips. For example, the processor 983 and control module 980 may be implemented by a single chip. The spindle/FM driver 989 and/or the read/write channel module 990 may also be implemented by the same chip as the processor 983 control module 980, and/or by additional chips. Most of the optical media system 970, other than the optical media assembly 978, may alternatively be implemented as a system-on-chip (SOC).
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The DVD drive 1000 may communicate with an output device (not shown) such as a computer, television, or other device via one or more wired or wireless communication links 1007. The DVD drive 1000 may communicate with mass data storage 1008 that stores data in a nonvolatile manner. The mass data storage 1008 may include a hard disk drive (HDD). The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The DVD drive 1000 may communicate with memory 1009 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.
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The HDTV 1020 may communicate with mass data storage 1027, which stores data in a nonvolatile manner such as optical and/or magnetic storage devices. The present invention may be implemented in an optical storage device of the mass data storage 1027. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The HDTV 1020 may be connected to memory 1028 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV 1020 also may support connections with a WLAN via a WLAN network interface 1029.
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The set top box 1040 may communicate with mass data storage 1048, which stores data in a nonvolatile manner. The mass data storage 1048 may include optical and/or magnetic storage devices; for example, hard disk drives HDD and/or DVDs. The present invention may be implemented in a DVD storage device. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The set top box 1040 may communicate with memory 1050 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The set top box 1040 also may support connections with a WLAN via a WLAN network interface 1052.
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The media player 1060 may communicate with mass data storage 1070 that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. The present invention may be implemented in an optical storage device. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The media player 1060 may be connected to memory 1074 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The media player 1060 also may support connections with a WLAN via a WLAN network interface 1076. Still other implementations in addition to those described above are contemplated.
Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.
Sutardja, Pantas, Li, Yingxuan, Mumford, Daniel
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