A receiver includes a digital phase locked loop (PLL) for performing carrier recovery. The digital PLL further includes a phase error estimator driven by hard decisions and an integrator, which accumulates a phase error signal provided by the phase error estimator. To reduce the acquisition time, the digital PLL is run in an open-loop mode during which an estimate of the carrier frequency offset is determined as a function of the phase error signal. After the estimate of the carrier frequency offset is determined, the integrator is pre-loaded with the determined estimate and the digital PLL is run in a closed-loop mode.
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5. A receiver comprising:
a carrier tracking loop (CTL) for processing a received signal; and
a processor for estimating a carrier frequency offset as a function of a phase error signal of the CTL;
wherein the processor detects a false lock condition as a function of comparing the estimate of the carrier frequency offset to a closed loop value of the CTL.
1. A method for use in a receiver, the method comprising:
using the receiver to perform the steps of
processing a received signal with a phase-locked loop (PLL);
generating a carrier frequency offset estimate as a function of a phase error signal of the PLL; and
detecting a false lock condition as a function of comparing the carrier frequency offset estimate to a closed loop value of the PLL.
2. The method of
3. The method of
determining a rollover count value for the phase error signal;
determining a symbol count value of the received signal; and
generating the carrier frequency offset estimate from the determined rollover count value and determined symbol count value.
4. The method of
6. The receiver of
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This application claims the benefit, under 35 U.S.C. §365 of International Application PCT/US2004/008743, filed Mar. 22, 2004, which was published in accordance with PCT Article 21(2) on Oct. 13, 2005 in English.
The present invention generally relates to communications systems and, more particularly, to carrier recovery in a communications system.
A carrier recovery loop, or carrier tracking loop, is a typical component of a communications system. The carrier recovery loop is a form of phase locked loop (PLL). In a digital carrier recovery loop, a decision-directed error estimator is often used to drive the PLL. In other words, the loop is driven by hard decisions, e.g., phase errors between respective received signal points and sliced symbols (nearest symbols) taken from the symbol constellation. When the carrier frequency offset, i.e., the frequency difference between the carrier of the received signal and the recovered carrier, is outside the “lock range” of the loop, the so-called “pull-in” process occurs, in which, under proper operating conditions, the loop operates to reduce the carrier frequency offset until the carrier frequency offset falls inside the lock range of the loop and phase lock follows.
For the correct pull-in process to take place, it is necessary that the output signal of the error estimator have a bias such that an integrator of the PLL drifts in the desired direction, i.e., a direction that reduces the carrier frequency offset. Unfortunately, there will be instances when the aforementioned bias will have an incorrect sign (because of excessive delay through the loop, errors associated with fixed point arithmetic, etc.), which, over time, will result in the loop either drifting without any predictable pattern or stabilizing at a false value (a “false-lock” condition). To combat this problem it is common to increase the precision of the arithmetic operations performed in the loop and/or to increase the loop gain. However, when the root cause of the problem lies in the pipeline delay through the loop and when such delay is necessitated by the system architecture and, thus, is unchangeable, the only option commonly available is to try and reduce the effective carrier frequency offset presented at an input to the loop such that the delay through the loop is no longer harmful. This can be done by sub-dividing the overall carrier frequency offset range into smaller ranges though which the loop can be “stepped”. However, the latter solution unavoidably increases the overall loop acquisition time and may not even be feasible if no reliable loop lock criterion exists to control the stepping algorithm.
As noted above, when a PLL of a receiver is operating outside the lock range, acquisition time may increase or may not be feasible. However, I have observed that it is possible to reduce the acquisition time in a way that adds little hardware and/or software overhead to the receiver. In particular, and in accordance with the principles of the invention, a receiver determines a carrier frequency offset estimate as a function of a phase error signal of the PLL.
In an embodiment of the invention, a receiver includes a digital phase locked loop (PLL) for performing carrier recovery. The digital PLL further includes a phase error estimator driven by hard decisions and an integrator, which accumulates a phase error signal provided by the phase error estimator. To reduce the acquisition time, or to make acquisition possible, the digital PLL is run in an open-loop mode during which an estimate of the carrier frequency offset is determined as a function of the phase error signal. After the estimate of the carrier frequency offset is determined, the integrator is pre-loaded with the determined estimate and the digital PLL is run in a closed-loop mode, whereby acquisition time is reduced.
Other than the inventive concept, the elements shown in the figures are well known and will not be described in detail. For example, other than the inventive concept, set-top box, and the components thereof, such as a front-end, Hilbert filter, carrier tracking loop, video processor, remote control, etc., are well known and not described in detail herein. In addition, the inventive concept may be implemented using conventional programming techniques, which, as such, will not be described herein. Finally, like-numbers on the figures represent similar elements.
Before describing the inventive concept, attention should be directed to
It should be noted that phase error detector 215 includes two elements phase error estimator 225 and slicer 220. As known in the art, the latter makes a hard decision as to the possible symbol (target symbol) represented by the in-phase and quadrature components of each received signal point of down-converted signal 211. In particular, for each received signal point of down-converted signal 211, slicer 220 selects the closest symbol (target symbol) from a predefined constellation of symbols. As such, the detector output signal 226 provided by phase error estimator 225 represents the phase difference between each received signal point and the corresponding target symbol. In particular, detector output signal 226 represents a sequence of phase error estimates, α, where each particular α is determined by calculating the imaginary part of the received signal point times the conjugate of the associated sliced symbol, i.e.,
α≅imag(z·z*sliced)=|z|·|zsliced|sin(∠z−∠zsliced). (1)
In the above equation, Z represents the complex vector of the received signal point, zsliced represents the complex vector of the associated sliced signal point and z*sliced represents the conjugate of the complex vector of the associated sliced signal point.
For example, consider a quadrature phase-shift keying (QPSK) symbol constellation 89 shown in
In the context of the illustrative symbol constellation 89, the phase error, α, is a monotonic function and varies between +/−45 degrees since the hard decision process always assumes that a received signal point is a phase-rotated version of a symbol from the same quadrant. However, it can be observed from
In view of the above noted phase error ambiguity, I have observed that if the received signal points are rotating (due to a carrier frequency offset) and the carrier recovery loop is “opened,” the phase error, α, will linearly increase (or decrease) and the detector output signal will “rollover” from a max positive (+) value to a max negative (−), and vice versa. Hence, in an open loop mode of operation, the detector output signal 226 will have a “saw tooth” shape as illustrated in
A high-level block diagram of a portion of an illustrative cable system 10 in accordance with the principles of the invention is shown in
Turning now to
Input signal 316 represents a QPSK modulated signal centered at a specific IF (Intermediate Frequency) of FIF Hertz. Input signal 316 is passed through CTL 320, which, in accordance with the principles of the invention, processes signal 316 to down convert the IF signal to baseband and correct for frequency offsets between the transmitter (not shown) and the receiver tuner Local Oscillator (not shown). CTL 320 is a second order loop, which, in theory, allows for frequency offsets to be tracked with no phase error. In practice, phase error is a function of the loop bandwidth, input phase noise, thermal noise and implementation constraints like bit size of the data, integrators and gain multipliers. CTL 320 provides a down-converted received signal 321. The latter is provided to other portions (not shown) of receiver 15 for recovery of the data conveyed therein.
In accordance with the principles of the invention, receiver 15 performs an open-loop carrier frequency offset estimate as a function of a phase error signal of CTL 320. Illustratively, and as described further below, processor 350 is coupled with CTL 320 via signals 326, 327, 351, 352 and 353 for determining the aforementioned carrier frequency offset estimate and, responsive thereto, loading CTL 320 with this estimate—thus reducing acquisition time of CTL 320.
Turning now to
At this time reference should also be made to
offsetvalue=rollovercounter÷(symbolcounter×4)×2N; (2)
where the term “rollovercounter” is equal to the value of rollover counter 455 and the term “symbolcounter” is equal to the value of symbol counter 460. The factor of “4” in equation (2) comes from the fact that the rollover counter in the QPSK case will rollover 4 times per single period of the offset frequency. It should be noted that if the value of symbolcounter is a power of two then, advantageously, the division operation of equation (2) can be replaced with an equivalent bit shift operation. In step 520, processor 350 loads (or initializes, or updates) phase integrator 435, via signal 353, with the offset value and sets CTL 320 to a closed loop mode of operation, via signal 352.
The closed loop mode of operation of CTL 320, other than the inventive concept, is similar to the earlier described carrier recovery circuit 200 of
As described above, and in accordance with the principles of the invention, a receiver performs an open-loop carrier frequency offset estimate as a function of a phase error signal of the carrier recovery loop. After the estimate of the carrier frequency offset is determined, the receiver initializes, or updates, the carrier recovery loop with the determined estimate and then runs the carrier recovery loop in a closed-loop mode, whereby acquisition time is reduced.
In addition to reduction of the acquisition time when a loop is operating outside the lock range, other applications of the inventive concept are possible. For example, the above-described determination of a carrier frequency offset estimate as a function of a phase error signal can also be used to decide whether a loop is in a true, or false, lock state. This is illustrated in the flow chart of
Another illustrative embodiment of the inventive concept is shown in
In view of the above, the foregoing merely illustrates the principles of the invention and it will thus be appreciated that those skilled in the art will be able to devise numerous alternative arrangements which, although not explicitly described herein, embody the principles of the invention and are within its spirit and scope. For example, although illustrated in the context of separate functional elements, these functional elements may be embodied on one or more integrated circuits (ICs). Similarly, although shown as separate elements, any or all of the elements may be implemented in a stored-program-controlled processor, e.g., a digital signal processor, which executes associated software, e.g., corresponding to one or more of the steps shown in
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