A liquid crystal display includes an insulating substrate, a plurality of parallel gate lines disposed on the insulating substrate, and a plurality of data lines disposed on the insulating substrate. The data lines insulatingly intercross the gate lines. An intersection between two of the plurality of gate lines and a corresponding two of the plurality of data lines defines a pixel region. Each pixel region includes a first thin film transistor (tft), a first pixel electrode, and a second pixel electrode. The first tft includes a first gate electrode connected with the gate line, a first source electrode connected with the first pixel electrode, and a first drain electrode connected with the first pixel electrode. A voltage of the first pixel electrode is different from a voltage of the second pixel electrode.
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19. A liquid crystal display comprising:
an insulating substrate;
a plurality of parallel gate lines disposed on the insulating substrate; and
a plurality of data lines disposed on the insulating substrate and insulatingly intercrossing the gate lines, thereby defining a plurality of pixel regions each between an intersection between two of the plurality of gate lines and a corresponding two of the plurality of data lines;
wherein each pixel region comprises two thin film transistors (tfts), a first pixel electrode, and a second pixel electrode, a gate electrode of each tft is connected with the gate line, a source electrode and a drain electrode of one of the tfts are connected with the data line and the first pixel electrode, respectively, a source electrode and a drain electrode of the other tft are connected with the first pixel electrode and the second pixel electrode, respectively, the first tft and the second tft share a same gate insulating layer and a passivation layer covering the gate insulating layer, the gate electrode of either one of the tfts is disposed below the gate insulating layer, and the gate electrode of the other tft covers the passivation layer.
11. A liquid crystal display comprising:
an insulating substrate; and
a plurality of pixel regions,
each pixel region comprising:
a gate line;
a data line;
a first pixel electrode;
a second pixel electrode; and
a first thin film transistor (tft);
wherein the first tft comprises a gate insulating layer, a first gate electrode connected with the gate line, a first source electrode connected with the data line, a first drain electrode connected with the first pixel electrode, and a passivation layer, the gate insulating layer covers the insulating substrate, the first source electrode and the first drain electrode cover the gate insulating layer, the passivation layer covers the first source electrode and the first drain electrode, and the first gate electrode covers the passivation layer; and
each pixel region further comprising:
a second gate electrode;
a second source electrode; and
a second drain electrode;
wherein the second gate electrode is disposed between the gate insulating layer and the insulating substrate, the second source electrode and the second drain electrode are disposed between the gate insulating layer and the passivation layer, and the second gate electrode, the gate insulating layer, the second source electrode, the second drain electrode and the passivation layer cooperate to define a second tft, the second gate electrode connected with the gate line, the second source electrode connected with the first pixel electrode, the second drain electrode connected with the second pixel electrode, and a voltage of the first pixel electrode being different from a voltage of the second pixel electrode.
1. A liquid crystal display comprising:
an insulating substrate;
a plurality of parallel gate lines disposed on the insulating substrate; and
a plurality of data lines disposed on the insulating substrate and insulatingly intercrossing the gate lines, thereby defining a plurality of pixel regions each between an intersection between two of the plurality of gate lines and a corresponding two of the plurality of data lines;
wherein each pixel region comprises a first thin film transistor (tft), a first pixel electrode, and a second pixel electrode, the first tft comprises a gate insulating layer, a first gate electrode connected with the gate line, a first source electrode connected with the data line, a first drain electrode connected with the first pixel electrode, and a passivation layer, the gate insulating layer covers the insulating substrate, the first source electrode and the first drain electrode cover the gate insulating layer, the passivation layer covers the first source electrode and the first drain electrode, and the first gate electrode covers the passivation layer; and
each pixel region further comprises a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode is disposed between the gate insulating layer and the insulating substrate, the second source electrode and the second drain electrode are disposed between the gate insulating layer and the passivation layer, and the second gate electrode, the gate insulating layer, the second source electrode, the second drain electrode and the passivation layer cooperate to define a second tft, the second gate electrode connected with the gate line, the second source electrode connected with the first pixel electrode, the second drain electrode connected with the second pixel electrode, and a voltage of the first pixel electrode being different from a voltage of the second pixel electrode.
2. The liquid crystal display of
3. The liquid crystal display of
4. The liquid crystal display of
5. The liquid crystal display of
6. The liquid crystal display of
7. The liquid crystal display of
8. The liquid crystal display of
9. The liquid crystal display of
10. The liquid crystal display of
12. The liquid crystal display of
13. The liquid crystal display of
14. The liquid crystal display of
15. The liquid crystal display of
16. The liquid crystal display of
17. The liquid crystal display of
18. The liquid crystal display of
20. The liquid crystal display of
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This application is related to, and claims the benefit of, a foreign priority application filed in China as Serial No. 200710123709.0 on Sep. 28, 2007. The related application is incorporated herein by reference.
The present disclosure relates to liquid crystal displays, and more particularly to multi-domain vertical alignment (MVA) liquid crystal displays.
LCDs have the advantages of portability, low power consumption, and low radiation, and have been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. A conventional LCD such as a twisted nematic (TN) LCD provides a limited viewing angle of the LCD. Thus, MVA LCDs were developed to improve the viewing angle of the LCD.
Referring to
The first substrate assembly includes a color filter (not shown), a common electrode (not shown), and a plurality of first protrusions 119, arranged in that order. The color filter includes a plurality of red filter units (not shown), a plurality of green filter units (not shown), and a plurality of blue filter units (not shown). The first protrusions 119 each are triangular in cross-section, and are arranged along a plurality of V-shaped paths.
The second substrate assembly includes a plurality of parallel gate lines 121 that each extend parallel to a first axis, a plurality of first parallel data lines 122 that each extend parallel to a second axis orthogonal to the first axis, a plurality of parallel second data lines 124 each extending parallel to the second axis, a plurality of first thin film transistors (TFTs) 161, a plurality of second TFTs 162, a plurality of first pixel electrodes 171, a plurality of second pixel electrodes 172, and a plurality of second protrusions 129.
The first data lines 122 and the second data lines 124 are arranged alternately. Every two adjacent first data lines 122, together with every two adjacent gate lines 121, form a rectangular area, defined as a pixel region 150. Each pixel region 150 corresponds to a filter unit of the color filter. Each second data line 124 is disposed across the middle of a corresponding pixel region 150, and divides the pixel region 150 into a first sub-pixel region 151 and a second sub-pixel region 152.
In each pixel region 150, the first TFT 161 is located in the vicinity of an intersection of the first data line 122 and the gate line 121. The second TFT 162 is located in the vicinity of an intersection of the second data line 124 and the gate line 121. Gate electrodes (not labeled) of the first TFT 161 and the second TFT 162 are connected to the same gate line 121. A source electrode (not labeled) of the first TFT 161 is connected to the first data line 122. A source electrode (not labeled) of the second TFT 162 is connected to the second data line 124. The first pixel electrode 171 is located in the first sub-pixel region 151, connected with a drain electrode (not labeled) of the first TFT 161. The second pixel electrode 172 is located in the second sub-pixel region 152, connected with a drain electrode (not labeled) of the second TFT 162. The first data line 122 provides a plurality of first gray-scale voltages to the corresponding first pixel electrode 171 via the first TFT 161. The second data line 124 provides a plurality of second gray-scale voltages to the corresponding second pixel electrode 172 via the second TFT 162. The first gray-scale voltages and the second gray-scale voltages are applied thereto independently.
The second protrusions 129 each are triangular in cross-section, arranged along a plurality of V-shaped paths. The second protrusions 129 and the first protrusions 119 are arranged alternately.
Referring also to
Similarly, in the same frame, when a second gray-scale voltage is applied to the second pixel electrode 172, and a common voltage is applied to the common electrode, an electric field is generated therebetween. The liquid crystal molecules 131 in the second sub-pixel region 152 re-orient according to the electric field. The liquid crystal molecules 131 are guided by the protrusions 119, 129 and thereby align along four different axes. Thus four domains are defined according to the protrusions 119, 129. Referring also to
However, each pixel region 150 requires a first data line 122 and a second data line 124 for the liquid crystal display 1 to perform the 8-domain vertical alignment. The layout of the first data line 122 and the second data line 124 is complicated, resulting in an increase of cost thereof.
It is desired to provide an improved liquid crystal display which can overcome the limitations described.
In one embodiment, a liquid crystal display includes an insulating substrate, a plurality of parallel gate lines on the insulating substrate, and a plurality of data lines on the insulating substrate. The data lines insulatingly intercross the gate lines. An intersection between two of the plurality of gate lines and a corresponding two of the plurality of data lines defines a pixel region. Each pixel region includes a first thin film transistor (TFT), a first pixel electrode, and a second pixel electrode. The first TFT includes a first gate electrode connected with the gate line, a first source electrode connected with the first pixel electrode, and a first drain electrode connected with the first pixel electrode. A voltage of the first pixel electrode is different from a voltage of the second pixel electrode.
Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, all the views are schematic.
Reference will now be made to the drawings to describe certain inventive embodiments of the present disclosure in detail.
Referring to
The first substrate assembly includes a color filter (not shown), a common electrode (not shown), and a plurality of first protrusions 419, arranged in that order from top to bottom. The color filter includes a plurality of red filter units (not shown), a plurality of green filter units (not shown), and a plurality of blue filter units (not shown). The first protrusions 419 are parallel, each having a triangular cross-section and arranged along a plurality of V-shaped paths.
The second substrate assembly includes a plurality of parallel gate lines 411, each extending along a first axis, a plurality of parallel data lines 412, each extending along a second axis orthogonal to the first axis, a plurality of first TFTs 461, a plurality of second TFTs 462, a plurality of first pixel electrodes 471, a plurality of second pixel electrodes 472, and a plurality of second protrusions 429.
Every two adjacent gate lines 411 and every two adjacent data lines 412 cooperatively form a rectangular area defined as a pixel region 450. Each pixel region 450 corresponds to a filter unit of the color filter. Each pixel region 450 includes a first sub-pixel region 451 and a second sub-pixel region 452. Each first sub-pixel region 451 includes one of the first TFTs 461 and one of the first pixel electrodes 462. The first TFT 461 is disposed in the vicinity of an intersection of the gate line 411 and the data line 412. Each second sub-pixel region 452 includes one second TFT 462, one second pixel electrode 472.
Referring also to
The first gate electrode 4613 is connected to a corresponding one of the gate lines 411. The first source electrode 4611 is connected to a corresponding one of the data lines 412. The first drain electrode 4612 is connected to a corresponding one of the pixel electrodes 471. The first gate electrode 4613, the first pixel electrode 471, and the second pixel electrode 472 can be made by a same photo-mask process, and can be made from a same material such as indium-zinc oxide (IZO) or indium tin oxide (ITO), for example. A thickness of the passivation layer 55 is less than a thickness of the gate insulating layer 52.
Referring to
The second gate electrode 4623 is connected to a corresponding gate line 411. The second source electrode 4621 is connected to the first pixel electrode 471. The second drain electrode 4622 is connected to the second pixel electrode 472.
Because the first TFT 461 is a top-gate TFT and the second TFT is a bottom-gate TFT and the thickness of the passsivation layer 55 is less than the thickness of the gate insulating layer 52, a switch-on voltage of the first TFT 461 is less than a switch-on voltage of the second TFT 462.
Scanning voltages of the gate lines 411 are substantially equal to the switch-on voltage of the first TFT 461. When the scanning voltage is applied to the first sub-pixel region 451, the first TFT 471 is completely switched on. Thus, a voltage of the first pixel electrode 471 is substantially equal to a voltage of the corresponding data line 412. The second TFT 472 is partly switched on. Thus, a voltage of the second pixel electrode 472 is lower than a voltage of the corresponding first pixel electrode 471.
When the corresponding voltages are applied to the first pixel electrode 471 and the common electrode, electric fields are generated. Referring to
Similarly, the liquid crystal molecules 431 in the second sub-pixel region 452 are guided by the first protrusions 419 and the second protrusions 429, thereby aligning along four different axes. Referring also to
Each pixel region 450 of the liquid crystal display 4 includes the top-gate first TFT 461 and the bottom-gate second TFT 462. The second TFT 462 is partly switched on when applied with a scanning voltage by the gate line 411. That is, a voltage difference generates between the first pixel electrode 471 and the second pixel electrode 472 to make the liquid crystal display 4 achieve 8-domain vertical alignment. No auxiliary data line is needed to apply a different voltage to the second pixel electrode 472. That is, each pixel region 450 of the liquid crystal display 4 needs only one data line 412 to achieve 8-domain vertical alignment. Layout of the data lines 412 is simplified, and the cost of the liquid crystal display 4 is reduced correspondingly.
Referring to
Because the switch-on voltage of the first TFT 661 is reduced, the liquid crystal display thereof has less power consuming and also achieves 8-domain vertical alignment.
Further or alternative embodiments may include, in a first example, the second source electrodes of the second TFTs 462 may be connected with the same data lines as the first source electrodes of the first TFTs 461. In a second example, the second source electrodes of the second TFTs 462 may be connected with the corresponding first drain electrodes of the first TFTs 461. In a third example, a capacitor may be placed to connect the first pixel electrodes and the second pixel electrodes to generate a voltage difference therebetween.
It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit or scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.
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