HBT/FET process integration

Abstract

A co-integrated HBT/FET apparatus and system, and methods for making the same, are disclosed. A co-integrated HBT/FET apparatus may include a first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a FET device, a separation layer formed over the first epitaxial structure, and a second epitaxial structure formed over the separation layer, the second epitaxial structure forming, at least in part, a heterojunction bipolar transistor (HBT) device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional application of, and claims priority to, provisional applications 60/859,190 filed on Nov. 15, 2006 and 60/893,412 filed on Mar. 7, 2007. The entire disclosures of said provisional applications are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments of the present invention relate generally to integrated heterojunction bipolar transistor (HBT)/field effect transistor (FET) processes, and their application to microwave circuits and apparatuses.

BACKGROUND

In the current state of integrated circuit technology, transistors are typically heavily incorporated into integrated circuits in order to perform a number of functions. In an effort to improve circuit functionality, particularly for power amplifier circuits, transistors, such as heterojunction bipolar transistors (HBT) and field effect transistors (FET), for example, have been co-integrated on single gallium arsenide substrates.

Co-integrating transistor devices sometimes involves compromising between manufacturability and device performance. For some co-integrated transistor devices, for example, metal-semiconductor field effect transistor (MESFET) specific layers are grown within an emitter layer of an HBT, which while featuring manufacturability and simplicity of process, may result in degraded device performance at least in part to incomplete decoupling of the transistors.

Another exemplary co-integrated device is a pseudo-morphic high-electron mobility transistor (pHEMT) epitaxial structure co-integrated into a subcollector layer of an HBT. Although device performance may be enhanced relative to the described MESFET/HBT device, manufacturability may suffer at least in that additional processing operations may be required and epitaxial crystal growth may be more complex.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 is a cross-sectional view of an apparatus formed using an integrated HBT/FET process in accordance with various embodiments of the present invention.

FIGS. 2-15 illustrate various stages of a method for forming the apparatus device of FIG. 1 in accordance with various embodiments of the present invention.

FIG. 16 is a block diagram of an apparatus including at least one apparatus formed using an integrated HBT/FET process in accordance with various embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments in accordance with the present invention is defined by the appended claims and their equivalents.

Various operations may be described as multiple discrete operations in turn, in a manner that may be helpful in understanding embodiments of the present invention; however, the order of description should not be construed to imply that these operations are order dependent. Moreover, some embodiments may include more or fewer operations than may be described.

The description may use the phrases “in an embodiment,” “in embodiments,” or “in various embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present invention, are synonymous.

For the purposes of the present invention, the phrase “A/B” means A or B. The phrase “A and/or B” means “(A), (B), or (A and B).” The phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).” The phrase “(A)B” means “(B) or (AB),” that is, A is an optional element.

Various embodiments of the present invention may include apparatuses including at least one heterojunction bipolar transistor (HBT) and at least one field effect transistor (FET) formed using an integrated process, in which no part of the HBT layers are used in the active FET device. The process of co-integrating the transistors is sometimes known in the art as a BiHEMT process. Separating the epitaxial layers of the HBT device from the epitaxial layers of the FET device may allow, in embodiments, optimization of the performance of both devices individually.

A cross-sectional view of an apparatus 100 formed using an exemplary integration process is illustrated in FIG. 1. As illustrated, the apparatus 100 may comprise field effect transistor (FET) devices 102a, 102b and a heterojunction bipolar transistor (HBT) device 104. FET devices 102a, 102b may be formed from portions of a first epitaxial structure 106 formed over a substrate 108. HBT device 104 may be formed from a portion of a second epitaxial structure 110 formed over a portion of first epitaxial structure 106.

As illustrated, no part of second epitaxial structure 110, used for forming HBT device 104, is used for forming FET devices 102a, 102b. In embodiments, this separation may be achieved, at least in part, by using a separation layer, such as, for example, an etch stop layer 126, between first epitaxial structure 106 and second epitaxial structure 110, as discussed more fully herein. Although HBT device 104 is technically over some portion of first epitaxial structure 106 (i.e., HBT device 104 is built from second epitaxial structure 110, which may be formed over first epitaxial structure 106), first epitaxial structure 106 may be configured to have minimal effect on HBT device 104. For example, first epitaxial structure 106 may be relatively thin as compared to second epitaxial structure 110, which may mean that the sheet conductivity of first epitaxial structure 106 is substantially negligible due at least in part to the thickness difference between the two.

FET devices 102a, 102b may comprise any type of FET devices suitable for the application. For example, in various embodiments, at least one of FET devices 102a, 102b may comprise a pseudo-morphic high electron mobility transistor (pHEMT) device or a metal-semiconductor field effect transistor (MESFET) device. At least one of FET devices 102a, 102b may comprise an enhancement mode FET or depletion mode FET, or in some embodiments, one of FET devices 102a, 102b may comprise an enhancement mode FET while the other one of FET devices 102a, 102b comprises a depletion mode FET. For example, an exemplary apparatus may include an enhancement mode pHEMT and a depletion mode pHEMT.

It is also noted that although the illustrated apparatus 100 includes two FET devices 102a, 102b, other apparatuses within the scope of the present disclosure may include any number of FET devices suitable for the application, and accordingly, may include more or less FET devices 102a, 102b.

Apparatus 100 may include various features for achieving functionality and depending at least in part on the particular application. For example, apparatus 100 may include various passive devices 112 such as, for example, capacitor, resistors, and the like. Interconnects 114, on the local and/or global level, may be included for electrical interconnection of apparatus 100 to external components (not illustrated). Dielectric material 116 may be included for separating interconnect layers as needed.

Various features of apparatus 100 may be more fully understood with reference to methods for making apparatuses such as, for example, apparatus 100 of FIG. 1. Various stages of an exemplary method are illustrated in FIGS. 2-15. For clarity, the same reference numerals used in FIG. 1 are used for describing the exemplary method of FIGS. 2-15.

Turning now to FIG. 2, first epitaxial structure 106 may be formed on substrate 108. A suitable substrate 108 may comprise, in various embodiments, gallium arsenide (GaAs). In other embodiments, however, substrate 108 may comprise GaN, indium phosphide (InP), or another material or combination of materials suitable for the application. For example, substrate 108 may comprise silicon carbide, silicon, sapphire, aluminum nitride, or some combination thereof or some combination with another suitable material. In various embodiments, one or more buffer layers (not illustrated) may be formed over substrate 108.

First epitaxial structure 106 may comprise one or more layers suitable for forming a FET device within the scope of this disclosure. In some embodiments wherein the FET device to be formed is a pHEMT device, first epitaxial structure 106 may comprise, for example, a first spacer layer 118 formed over substrate 108, a channel layer 120 formed over spacer layer 118, a second spacer layer 122 formed over channel layer 120, and a contact layer 124 formed over second spacer layer 122. In an exemplary embodiment, first spacer layer 118 comprises aluminum gallium arsenide (AlGaAs), channel layer 120 comprises indium gallium arsenide (InGaAs), second spacer layer 122 comprises AlGaAs, and contact layer 124 comprises GaAs. Other materials may be similarly suitable for forming the desired FET epitaxial structure. Further, various doping operations may be performed on the formed layers for achieving desired electrical properties. For example, in various embodiments, first spacer layer 118 may comprise a higher bandgap doped layer, channel layer 120 may comprise a lower bandgap layer, and second spacer layer 122 may comprise a higher bandgap doped Schottky layer.

Second epitaxial structure 110 may be formed over first epitaxial structure 106, as illustrated in FIG. 3. As discussed herein, HBT device 104 may be formed from a portion of second epitaxial structure 110. Accordingly, any material(s) suitable for forming HBT device 104 may be suitable for forming second epitaxial structure 110. For example, in various embodiments, second epitaxial structure 110 may comprise at least a subcollector layer 128, a collector layer 130, a base layer 132, an emitter layer 134, and a contact layer 136. Although various materials may be equally suitable, in exemplary embodiments one or more of subcollector layer 128, collector layer 130, and base layer 132 may comprise GaAs, or another suitable material. Emitter layer 134 may comprise indium gallium phosphide (InGaP), AlGaAs, or another suitable material, and contact layer 136 may comprise InGaAs contact layer or another suitable material.

As noted herein, no part of second epitaxial structure 110, used for forming HBT device 104, is used for forming FET devices 102a, 102b. To that end, a separation layer such as, for example, an etch stop layer 126, may be formed intermediate first 106 and second epitaxial structures 112. Etch stop layer 126 may help in protecting first epitaxial structure 106 from undesired etching and/or damage during formation of HBT device 104, as may become more evident in the discussion to follow. Any suitable material may be used for forming etch stop layer 126 including, for example, AlGaAs or InGaP, and the selected material may be doped or undoped. In various other embodiments, any material suitable for substantially electrically isolating first epitaxial structure 106 from second epitaxial structure 110 may be used for etch stop layer 126, even if not technically serving an “etch stop” function.

An emitter contact 138 may be formed over second epitaxial structure 110 as illustrated in FIG. 4, and portions of emitter layer 134 and contact layer 136 may be etched down to base layer 132 as illustrated in FIG. 5, resulting in the emitter mesa structure illustrated. In various embodiments, the operations illustrated in FIG. 4 and FIG. 5 may be reversed such that the emitter mesa is formed prior to forming emitter contact 138. Emitter contact 138 may comprise any material suitable for electrically interconnecting HBT device 104 including, for example, a suitable metal.

As illustrated in FIG. 6, a base contact 140 may then be formed over base layer 132, and then the base mesa may be formed by etching portions of base layer 132 down to subcollector layer 128 as illustrated in FIG. 7. In various embodiments, the operations illustrated in FIG. 6 and FIG. 7 may be reversed such that the base mesa is formed prior to forming base contact 140. Base contact 140 may comprise any material suitable for electrically interconnecting HBT device 104 including, for example, a suitable metal.

As illustrated in FIG. 8, portions of subcollector layer 128 may be etched down to etch stop layer 126, exposing portions of etch stop layer 126 and resulting in a subcollector mesa. The exposed portions of etch stop layer 126 may be etched away, revealing portions of first epitaxial structure 106, as illustrated in FIG. 9.

One or more recesses 142 may then be formed in contact layer 124 of revealed portions of first epitaxial structure 106, as illustrated in FIG. 10. The locations of recesses 142 may be selected based at least in part on desired locations of FET devices to be formed. More particularly, locations of recesses 142 may correspond to locations at which the gates for the FET devices are to be formed. In the illustrated embodiment, for example, two recesses 142 are formed, which may correspond to gates 158 of two FET devices 102a, 102b (refer to FIG. 1). The formation of recesses 142 may include one or more suitable operations including, for example, photolithographic patterning.

FET devices 102a, 102b and HBT device 104 may be electrically isolated using one or more isolation techniques. For example, first epitaxial structure 106 may be subjected to implant isolation at regions 144, as illustrated at FIG. 11. In various embodiments, a FET device 102a or 102b may be formed in a first portion of first epitaxial structure 106, and HBT device 104 may be formed over a second portion of first epitaxial structure 106, the first portion and the second portion electrically isolated by implanted isolation region 144.

One or more contacts may be formed using any suitable ohmic metallization operation. Contacts may include, for example, the collector contacts 146 of HBT device 104, and source contacts 150 and drain contacts 152 of FET devices 102a, 102b, as illustrated in FIG. 12.

As noted herein with reference to FIG. 10, recesses 142 may be formed at locations corresponding to locations at which the gates for the FET devices are to be formed. Recesses 142 may formed, for example, corresponding to locations of gates 158 of FET devices 102a, 102b (refer to FIG. 1). Accordingly, gates 158 may be formed in the previously formed recesses 142. In some embodiments, gates 158 may be recessed into contact layer 124. For these embodiments, narrow recesses 154 may be formed in second spacer layer 122 within previously-formed recesses 142 (i.e., recesses 142 are wider than recesses 154), as illustrated in FIG. 13. Gates 158 may then be formed by depositing material into narrow recesses 154, as illustrated in FIG. 14. In other embodiments, however, gates 158 need not be recessed as illustrated.

One or more passive devices may be formed, depending on the application. Passive device may include known passive devices including, for example, resistors, capacitors, and inductors. In the embodiment illustrated in FIG. 15, a resistor 160 and a capacitor 162 are formed.

Interconnects 114 may be formed for electrically interconnecting apparatus 100 to external components (refer also to FIG. 1). Further interconnects 114 (local and global interconnects, for example) may be formed as needed, and dielectric material 116 may be formed for separating interconnect layers as needed, as illustrated in FIG. 1.

Various embodiments of apparatuses disclosed herein may advantageously be incorporated into radio frequency systems. For example, FIG. 16 illustrates a block diagram of an embodiment of a system 1600 incorporating a microwave transceiver 1664 including at least apparatus 1666 including one or more FET devices and one or more HBT devices co-integrated on a substrate, such as, for example, apparatus 100 illustrated in FIG. 1.

System 1600 may be any system used for power amplification at microwave and/or millimeter wave frequencies. For example, system 1600 may be suitable for any one or more of terrestrial and satellite communications, radar systems, and possibly in various industrial and medical applications. Radar applications may include military-use radar, air traffic control, navigation, and the like.

In various embodiments, system 1600 may be a selected one of a radar device, a satellite communication device, a cellular telephone, or a cellular telephone base station. System 1600 may find applicability in other applications in which power amplification for microwave and/or millimeter wave frequency transmission and/or reception is required.

In various embodiments, transceiver 1664 may be configured to transmit and/or receive signals on microwave and/or millimeter wave frequencies. Microwave transceiver 1664 may, in various embodiments, include at least one apparatus including one or more FET devices and one or more HBT devices co-integrated on a substrate, such as, for example, apparatus 100 illustrated in FIG. 1.

System 1600 may include one or more antennas (not illustrated) coupled to microwave transceiver 1664. One or more of the antennas may be configured to transmit and receive electromagnetic radiation at frequencies suitable for the particular application.

A controller 1670 may be coupled to microwave transceiver 1664. Controller 1670 may be configured to control operation of the microwave transceiver 1664. In various embodiments, controller 1670 may be configured to produce and distribute a clock by which system 1600 is synchronized. In embodiments wherein system 1600 is configured to both transmit and receive microwave and/or millimeter wave frequencies, controller 1670 may be configured to control switching between transmit and receive modes, which may occur by way of a duplexer. Additionally or alternatively, controller 1670 may be configured to control various other aspects of system 1600.

Although certain embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present invention. Those with skill in the art will readily appreciate that embodiments in accordance with the present invention may be implemented in a very wide variety of ways. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments in accordance with the present invention be limited only by the claims and the equivalents thereof.

Claims

1. An apparatus comprising:

a first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a field effect transistor (FET) device, wherein the FET device includes a first layer, including a source contact and a drain contact, disposed in a first plane;

a separation layer formed over the first epitaxial structure; and

a second epitaxial structure formed over the separation layer, the second epitaxial structure forming, at least in part, a heterojunction bipolar transistor (HBT) device, wherein the HBT device includes a second layer, including collector contacts, that is separate from the first layer and disposed in a second plane, wherein the first plane and the second plane are non-coplanar to each other.

2. The apparatus of claim 1, wherein the separation layer comprises an etch stop layer comprising aluminum gallium arsenide (AlGaAs) or indium gallium phosphide (InGaP).

3. The apparatus of claim 1, wherein the FET device is a pseudo-morphic high electron mobility transistor (pHEMT) device or a metal-semiconductor field effect transistor (MESFET) device.

4. The apparatus of claim 1, wherein the FET device is an enhancement mode FET or a depletion mode FET device.

5. The apparatus of claim 4, wherein the FET device is an enhancement mode FET device and wherein the first epitaxial structure further forms, at least in part, another FET device, wherein the other FET device is a depletion mode FET device.

6. The apparatus of claim 1, wherein the substrate comprises a selected one of gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP).

7. The apparatus of claim 1, wherein the first epitaxial layer includes an implanted isolation region.

8. The apparatus of claim 7, wherein the FET device is formed in a first portion of the first epitaxial structure, and wherein the separation layer having the HBT device formed thereover is formed over a second portion of the first epitaxial structure, the first portion and the second portion electrically isolated by the implanted isolation region.

9. The apparatus of claim 1, wherein the collector contacts are disposed over the separation layer.