A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by electroless plating. Then, the backside metal layer, such as a gold layer or a copper layer, is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metal peeling after subsequent fabrication processes. This is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.
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1. A method of backside metal processes for a semiconductor wafer with electronic devices fabricated thereon comprising steps of:
fabricating backside via holes on a wafer backside using lithography techniques follows by etching process to etch through the wafer to a surface metal layer;
coating a thin metal layer or a thin metal alloy layer as a metal seed layer on a rear surface of the wafer and on an inner sidewalls of the backside via holes using an electroless plating method, wherein said electroless plating method for coating the thin metal layer or the thin metal alloy layer as the metal seed layer is performed by immersing the semiconductor wafer in a plating solution containing sources of metals, followed by reaction of an additive agent, which makes metallic ions in the plating solution metalized to a thin film on the backside of the semiconductor wafer, wherein said metal seed layer coated by the electroless plating method has a preferred thickness in a range of 20-500 nm; and
depositing a backside metal layer directly on the metal seed layer after the coating of the metal seed layer to make good electrical contact between the surface metal layer and the backside metal layer via the backside via holes.
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The present invention discloses a method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating process for coating a metal seed layer for the subsequent backside plated metal, which not only improves the adhesion between the surface metal and the backside metal layers through backside via holes, but also prevents metal peeling during the subsequent fabrication processes.
Heterojunction Bipolar Transistors (HBTs) as well as High-Electron Mobility Transistors and (HEMTs) are important semiconductor electronic devices for a variety of applications, such as microwave, millimeter wave, and optoelectronic applications. For advanced multifunction devices, which include more than one device type on a common substrate, it is important to consider not only the die size and cost reduction, but also the performance of the integrated circuits with additional functionality. To achieve this goal, much effort has been made on the development of reliable fabrication processes of monolithic integrated devices for volume productions.
Backside metal process is one of the key process steps for the fabrication of integrated semiconductor devices. Regardless of device types and functionalities, it is necessary to provide grounding for those transistors fabricated on the front surface of a semiconductor wafer. Therefore, ground pads were usually disposed either in the vicinity of, or at a distance from, those front-side devices, depending on the surface device layout. In general, for a space saving purpose, a common ground pad is usually shared by many transistors.
Conventionally, the backside metal processes for GaAs based integrated devices usually utilize sputter to coat a metal seed layer on the rear surface and the backside via holes. However, by using the conventional method, it is difficult to form a thin metal seed layer with good uniformity and free of defect, and thereby hard to provide good adhesion for backside metals (such as Au, Al or Cu, etc.) on the rear surface, and particularly on the inner sidewalls of via holes. This situation will become even worse for via holes with very large aspect ratio. As a consequence, the backside metal layer becomes easily peeled off the surface metal layer during the subsequent fabrication processes, leading to poor device grounding and hence degradations in device performance, reliability and overall yield.
The material of the backside metal itself is also an important consideration. For GaAs-based integrated devices, the most commonly used backside metal is gold. Recently, semiconductor manufacturers have begun using copper as backside metal, because of its lower resistivity and manufacture costs. However, a drawback of using copper as a backside metal is that Cu atoms can easily diffuse into the GaAs substrate, which may even reach the active area of front-side devices, leading to device damages.
Therefore, it is necessary to develop a method of backside metal process for semiconductor electronic devices, which not only improves the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metallic atoms of the backside metal diffusing into the active area of front surface devices.
It is an object of the present invention to provide a fabrication method of backside metal processes for fabricating integrated semiconductor devices, by which a good electrical contact between the backside metal layer and the front side metal layer can be achieved, the metal peeling during subsequent fabrication processes can be prevented, and the diffusion of metallic atoms from the backside metal into the active area of front side devices can be suppressed.
In order to achieve the previously mentioned objective, the present invention provide a method of backside metal processes using electroless plating to form a metal seed layer for the subsequent backside metal layer. The metal seed layer coated using the electroless plating method can achieve good thickness uniformity and free of defect, and thereby not only providing good adhesion for backside metals on either the rear surface or the inner sidewalls of via holes even with a very large aspect ratio, but also mitigating the diffusion of metallic atoms from the backside metal into the active area of front side devices.
The backside metal processes of the present invention, which can be applied to semiconductor wafers with devices fabricated thereon and after wafer thinning processes, comprise steps of:
Defining the sizes, shapes and positions of backside via holes on the wafer backside using conventional photolithography processes;
Fabricating the backside via holes using either dry or wet chemical etchings;
coating a thin metal layer or a thin metallic alloy layer as a backside metal seed layer on the wafer's rear surface and on the inner sidewalls of backside via holes using the electroless plating method; and
depositing a backside metal layer in the final to make good electrical contact to the surface metal layer via the backside via holes.
The advantages of coating the backside metal seed layer using the electroless plating method are threefold, including
1. Cost reduction;
2. Volume production;
3. High uniformity in the thickness;
4. Good adhesion to substrate;
5. Improve the performance of front side devices.
Suitable materials for the metal seed includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.
The following detailed description, given by way of examples or embodiments, will best be understood in conjunction with the accompanying drawings.
The method of backside metal processes of the present invention has been proven experimentally that the metal peeling effect can be effectively prevented, making good electrical contact between the surface metal and the backside metal layers.
In addition, the performances of devices on wafer with backside metal layer fabricated by the method of the present invention have also been examined thoroughly. It was found that the use of electrolessly plated seed layer for backside metal layer can retain very good device performance and reliability. Cu) layers. As shown in
As discussed above, coating the backside metal seed layer using the electroless plating method of the present invention has the following advantages:
1. Cost reduction;
2. Volume production;
3. High uniformity in the thickness;
4. Good adhesion to substrate;
5. Improved the performance of front side devices.
Although the embodiments of the present invention have been described in detail, many modifications and variations may be made by those skilled in the art from the teachings disclosed hereinabove. Therefore, it should be understood that any modification and variation equivalent to the spirit of the present invention be regarded to fall into the scope defined by the appended claims.
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