An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.
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1. An electrostatic discharge (ESD) device, comprising:
a substrate;
a high voltage terminal having a low-doped well formed in the substrate, and a first contact, coupled to the low doped well, that has a perimeter located within a perimeter of the low-doped well;
a punch-through terminal having a diffusion area formed in the substrate, and a second contact, coupled to the diffusion area, that touches the substrate,
wherein a concentration level of a dopant in the low-doped well has a peak level of 8×1016/cm3 and is less than a concentration level of the dopant in the diffusion area,
wherein the substrate and the low-doped well are configured to form a depletion region between the low-doped well and the substrate when a reverse bias voltage is applied to the low-doped well and the substrate, and
wherein the substrate, the low-doped well, and the diffusion area are configured to form a current discharging path between the first contact and the second contact when the depletion region comes into contact with the diffusion area.
13. A method for forming an electrostatic discharge (ESD) device, comprising:
forming a substrate;
forming a high voltage terminal having a low-doped well formed in the substrate,
wherein the low-doped well is coupled to a first contact and a perimeter of the first contact is located within a perimeter of the low-doped well; and
forming a punch-through terminal having a diffusion area formed in the substrate,
wherein the diffusion area is coupled to a second contact that touches the substrate,
wherein a concentration level of a dopant in the low-doped well has a peak level of 8×1016/cm3 and is less than a concentration level of the dopant in the diffusion area,
wherein the substrate and the low-doped well are configured to form a depletion region between the low-doped well and the substrate when a reverse bias voltage is applied to the low-doped well and the substrate, and
wherein the substrate, the low-doped well, and the diffusion area are configured to form a current discharging path between the first contact and the second contact when the depletion region comes into contact with the diffusion area.
2. The ESD device of
3. The ESD device of
4. The ESD device of
5. The ESD device of
6. The ESD device of
7. The ESD device of
10. The ESD device of
a second high voltage terminal having a second low-doped well formed in the substrate,
wherein the second low-doped well is coupled to a third contact and a perimeter of the third contact is located completely within a perimeter of the second low-doped well,
wherein the punch-through terminal is located between the first and second high voltage terminals.
11. The ESD device of
a second punch-through terminal having a second diffusion area formed in the substrate,
wherein the second diffusion area is coupled to a third contact that touches the substrate,
wherein a perimeter of the second diffusion area overlaps a perimeter of the third contact; and
wherein the high voltage terminal is located between the first and second punch-through terminals.
14. The method of
15. The method of
16. The method of
wherein the second low-doped well is coupled to a third contact and a perimeter of the third contact is located completely within a perimeter of the second low-doped well,
wherein the punch-through terminal is located between the first and second high voltage terminals.
17. The method of
wherein the second diffusion area is coupled to a third contact that touches the substrate,
wherein a perimeter of the second diffusion area overlaps a perimeter of the third contact; and
wherein the high voltage terminal is located between the first and second punch-through terminals.
19. The method of
20. The method of
21. The ESD device of
22. The ESD device of
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This application is a continuation of allowed U.S. patent application Ser. No. 11/198,277, filed on Aug. 8, 2005, now U.S. Pat. No. 7,439,592 titled “ESD Protection for High Voltage Applications”, which claims the benefit of U.S. Provisional Patent Application No. 60/635,180, filed Dec. 13, 2004, both of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD) protection. More specifically, the present invention provides ESD protection for high voltage integrated circuits (ICs).
2. Background Art
It is often difficult to provide ESD protection on a high voltage IC that requires devices with high voltage tolerances. High voltage devices must have breakdown voltages that are higher than the operating voltages of the high voltage IC. The ESD protection must provide an ESD trigger voltage that is higher than the operating voltages of the high voltage IC and yet lower than the breakdown voltages of the high voltage devices. The operating voltages of the high voltage IC often approach the breakdown voltages of the high voltage devices, thereby making an acceptable range of the ESD trigger voltage narrow and difficult to achieve.
Conventional IC devices, such as Metal-Oxide Semiconductor (MOS) Field Effect Transistors (MOSFETs) and Bipolar Junction Transistors (BJTs), fail to provide voltage tolerances required by high voltage ICs. High voltage devices are therefore typically constructed with alternative technologies. These alternative high voltage devices may include Lateral Diffused MOS (LDMOS) transistors, Lateral Insulated Gate Bipolar Transistors (LIGBTs) and other devices. Since these high voltage devices are designed to withstand high voltages, they are not optimized to work as ESD discharge devices. Conventional devices cannot be used to provide ESD protection because the operating voltages usually exceed the breakdown voltages of the conventional devices.
Silicon Controlled Rectifier (SCR) structures are commonly used to provide ESD protection for high voltage ICs. A drawback of the SCR device is its relatively slow turn-on time. Another drawback of the SCR device is its triggering mechanism. The triggering of the SCR device is initiated by a substrate current generated by a pn-junction breakdown. This pn-junction, however, is also designed to have a high breakdown voltage for use in high voltage applications. Therefore, it is difficult to design the SCR device with a pn-junction that can satisfy these conflicting design goals. The effectiveness of the SCR structure is further compromised when a low resistively substrate is used, a common practice for high voltage ICs.
Processing steps used to fabricate high voltage ICs also render other commonly used ESD protection techniques ineffective. For example, snapback MOS devices provide poor ESD protection because their desired parasitic bipolar characteristic is purposely subdued in many fabrication processes. MOS-based ESD protection devices suffer from the characteristic high threshold voltage and channel resistance of high voltage MOSs, which results in excessive layout overhead. Diode-based ESD protection devices suffer from the high parasitic series resistance inherent in high voltage processing techniques, which also results in excessive layout overhead. Another obstacle in the design of high voltage ESD protection includes building resistors and capacitors in the ESD protection circuits that can tolerate high voltages.
Accordingly, the invention provides ESD protection for use in high voltage ICs by substantially obviating one or more of the disadvantages of the related art.
In one aspect of the invention, there is provided an ESD device including a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area is connected to the second contact. The substrate has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the reverse bias voltage causes the depletion region to come into contact with the diffusion region.
In another aspect of the invention, there is provided an ESD device including a low doped well connected to a first contact, a first diffusion area connected to a second contact and a second diffusion area connected to a third contact. The ESD device includes a substrate between the low doped well and the first diffusion area. The substrate and the second diffusion area have dopant polarities that are opposite dopant polarities of the low doped well and the first diffusion area. A distance between the low doped well and the first diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the reverse bias voltage causes the depletion region to come into contact with the diffusion region. A pn-junction formed between the low doped well and the substrate is forward biased when a forward bias voltage is applied to the ESD device. The pn-junction is well biased by the forward bias voltage and provides a forward bias ESD discharge path.
In another aspect of the invention, there is a provided a method of forming an ESD device including a substrate, a low doped well positioned within the substrate and connected to a first contact and a diffusion area positioned within the substrate and connected to a second contact. The substrate is connected to the second contact and has a dopant polarity that is opposite a dopant polarity of the low doped well and a dopant polarity of the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device.
In another aspect of the invention, there is a provided a method of forming an ESD device including a substrate and a low doped well positioned within the substrate and connected to a first contact. The ESD device also includes a first diffusion area positioned within the substrate and connected to a second contact and a second diffusion area positioned within the substrate and connected to a third contact. The substrate and the second diffusion area have dopant polarities that are opposite dopant polarities of the low doped well and the first diffusion area. A distance between the low doped well and the first diffusion area determines a triggering voltage of the ESD device.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure and particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable one skilled in the pertinent art to make and use the invention.
As shown in
The circuit devices within a high voltage integrated circuit are required to have high voltage tolerances. The breakdown voltages of the circuit devices within a high voltage integrated circuit must be higher than the operating voltage of any internal circuit within the high voltage integrated circuit. The doped semiconductor device 200 is often used to build a high voltage device for use within a high voltage integrated circuit. The low doping profile of the conventional low doped well 202 increases the breakdown voltage of the doped semiconductor device 200, thereby ensuring the doped semiconductor device 200 has a high voltage tolerance.
A high voltage integrated circuit also requires suitable Electrostatic Discharge (ESD) protection. An ESD protection device within a high voltage integrated circuit must provide an ESD trigger voltage that is above the operating voltage of any internal circuit, yet below the breakdown voltage of any circuit device. The operating voltages of the internal circuits are often pushed up near the breakdown voltages of the constituent circuit devices. The ESD trigger voltage of an ESD protection device must therefore be set within the narrow range established by the maximum operating voltage and the minimum breakdown voltage. The doped semiconductor device 200 is often not suitable for application as an ESD protection device because it is principally designed to be a high voltage device. There is therefore a need to design a high voltage device incorporating the use of low doped wells that is suitable for providing ESD protection within a high voltage integrated circuit.
As shown in
As further shown in
The low doped well 302 has a deep junction depth, relative to the depth of the substrate 308. The contact 304 and the contact 312 are typically made of metal. The contact 304 and the low doped well 302 together form the high voltage terminal of the ESD protection device 300. The contact 312 and the diffusion area 310 together form the punch-through terminal of the ESD protection device 300.
As shown in
The contact 312 applies the same voltage potential to the substrate 308 and to the diffusion area 310 during normal operation. The pn-junction formed by the intimate contact of the substrate 308 and the diffusion area 310 is therefore not reverse biased during normal operation. Consequently, a depletion region is not formed between the substrate 308 and the diffusion area 310 when a reverse bias voltage is applied to the ESD protection device 300.
The triggering voltage of the ESD protection device 300 is determined by the distance separating the low doped well 302 from the diffusion area 310. The distance between the low doped well 302 and the diffusion area 310 prevents the contact 304 and the contact 312 from shorting out during normal operation. That is, the distance between the low doped well and the diffusion area 310 is large enough to prevent the depletion region 316 from reaching the diffusion area 310 under normal operating voltages.
The distance between the low doped well 302 and the diffusion area 310 also prevents the ESD protection device 300 from having a triggering voltage that is too high. That is, the distance between the low doped well 302 and the diffusion area 310 is small enough to enable the depletion region 316 to reach the diffusion area 310 without requiring a reverse bias voltage that exceeds a breakdown voltage of a circuit device within the high voltage integrated circuit.
Overall, the distance between the low doped well 302 and the diffusion area 310 provides an ESD triggering voltage that is above the normal operating voltages of the high voltage integrated circuit and below the breakdown voltage of the circuit devices within the high voltage integrated circuit.
The low doped well 302 has a high voltage tolerance required by high voltage integrated circuits that cannot be provided by a conventionally doped well. Additionally, the low doped well 302 provides a reduced diffusion capacitance in comparison to a conventionally doped well. A reduced diffusion capacitance is desirable in high frequency applications and low signal distortion applications.
The ESD protection device 300 can be formed by conventional semiconductor manufacturing processes. The substrate 308 forms a bottom layer of the ESD protection device 300. A middle layer of the ESD protection 300 device includes the low doped well 302, the substrate 308 and the diffusion area 310. The low doped well 302 is positioned within the substrate 308. The low doped well 302 has a deep junction depth relative to the depth of the substrate 308. Impurities added to the substrate 308 have a polarity opposite the polarity of the impurities added to the low doped well 302. The low doped well 302 has a low concentration of dopant, particularly at the periphery of the low doped well 302.
The diffusion area 310 is also positioned within the substrate 308. Impurities added to the diffusion area 310 have the same polarity as the polarity of the impurities added to the low doped well 302. The low doped well 302 and the diffusion area 312 are separated by the substrate 308.
A top layer of the ESD protection device 300 includes a contact 304 and a contact 312. The contact 304 is positioned over the low doped well 302. The contact 312 is positioned over the diffusion area 312 and the substrate 308. The low doped well 302 and the contact 304 form the high voltage terminal of the ESD protection device 300. The diffusion area 310 and the substrate 308 form the punch-through terminal of the ESD protection device 300.
The distance between the low doped well 302 and the diffusion area 310 determines the ESD triggering voltage of the ESD protection device. The ESD protection device 300 can be formed using either type of dopant in the low doped well 302 and the diffusion area 310 depending on the dopant type used within the substrate 308. For example, the low doped well 302 and the diffusion area 310 can be p-type materials if the substrate 308 is an n-type material. Alternatively, the low doped well 302 and the diffusion area 310 can be n-type materials if the substrate 308 is an p-type material.
To protect a circuit element or circuit within an integrated circuit, the ESD protection device 300 is configured to route a high-voltage ESD event from a signal input or voltage supply input of the circuit element or circuit to an appropriate or suitable discharge node or device. Specifically, the high voltage terminal of the ESD protection device 300 is connected to the signal input or supply input of the circuit element or circuit that could experience an ESD event. The punch-through terminal of the ESD protection device 300 is then connected to a discharge node or device to prevent exposure of the ESD event to the signal input or voltage supply input of the circuit element or circuit.
As shown in
The contact 604-1 and the low doped well 606-1 form a high voltage terminal. The contact 604-2 and the low doped well 606-2 also form a high voltage terminal. The contacts 608-1, 608-2 and 608-3, in conjunction with their respective diffusion areas 610-1, 610-2 and 610-3, each form a punch-through terminal. ESD current discharge paths are created between the high voltage terminals and the punch-through terminals of the ESD protection device 600 during an ESD event.
ESD protection efficiency is improved by forming the high voltage terminals and punch-through terminals depicted in
The ends of the low doped wells 606-1 and 606-2 extend beyond the vertical boundaries of the contacts 604-1 and 604-2, respectively. The ends of the diffusion areas 610-1, 610-2 and 610-3 also extend beyond the vertical boundaries of the contacts 608-1, 608-2 and 608-3, respectively. This layout minimizes conduction at the ends of the low doped wells 606-1 and 606-2 and the diffusion areas 610-1, 610-2 and 610-3. In turn, the current discharge paths formed between the high voltage terminals and punch-through terminals of the ESD protection device 600 are less affected by edge effects that can result in non-uniform current flow.
The successively decreasing concentrations of dopant within the doped regions 702, 708 and 710 form a doping gradient. The high concentration of dopant within dopant region 702 provides a low resistive contact between the low doped well and the contact 704.
The periphery of the low doped well (i.e., the doped region 710) has a low doping concentration regardless of the doping concentration of the interior of the low doped well (i.e., the doped regions 702 and 708). Doping profiles other than the exemplary profile shown in
In one aspect of the present invention, the doped region 702 is a conventional doped diffusion area having a concentration level that is greater than 7×1017/cm3, the doped region 708 is a conventional doped well having a concentration level on the order of 1017/cm3 and the doped region 710 is a low doped well having a concentration level on the order of 1016/cm3. In another aspect of the present invention, the concentration level of the doped region 702 is less than or equal to 1×1020/cm3, the concentration level of the doped region 708 is between 5×1017/cm3 and 7×1017/cm3 and the concentration level of the doped region 710 is less than or equal to 8×1016/cm3.
As shown in
As shown in
As further shown in
The diffusion area 1008 and the contact 1010 together form the punch-through terminal of the ESD protection device 1000. The high concentration of dopant within the diffusion area 1016 provides a low resistive connection to the substrate 1006. The diffusion area 1016 therefore provides an improved conduction path from the punch-through terminal of the ESD protection device 1000 into the substrate 1006 for biasing.
The ESD protection device 1000 is reverse biased during normal operation. The ESD protection device 1000 will provide a discharge path between the contact 1004 and the contact 1010 when the reverse bias voltage exceeds an ESD triggering voltage of the ESD protection device 1000. This behavior of the ESD protection device 1000 provides reverse bias ESD discharge protection.
The ESD protection device 1000 also provides forward bias discharge protection. A forward biased pn-junction diode is formed between the low doped well 1002 and the substrate 1006 when the voltage applied to the high-voltage terminal and punch-through terminal is forward biased. The forward biasing of the pn-junction formed by the low doped well 1002 and the substrate 1006 is improved by the high concentration of dopant in the diffusion area 1016. A discharge path is formed between the contact 1004 and the contact 1014 when the ESD protection device 1000 is forward biased. In this way, the ESD protection device 1000 provides improved forward biased ESD discharge protection.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example and not limitation. It will be apparent to one skilled in the pertinent art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Therefore, the present invention should only be defined in accordance with the following claims and their equivalents.
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