A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material.
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1. A semiconductor device configured to be electrically connected to another device by through silicon interconnect technology, the semiconductor device comprising:
a semiconductor substrate with at least one through hole extending from a first surface to a second surface of the semiconductor substrate;
a through silicon conductor extending inside the through hole from the first surface to the second surface of the semiconductor substrate, wherein the through silicon conductor is electrically isolated from the semiconductor substrate;
a conductor bump electrically connected to an end of the through silicon conductor adjacent the first surface; and
a gap between the semiconductor substrate and the through silicon conductor, the gap surrounding the through silicon conductor adjacent the first surface of the semiconductor substrate, the gap extending from the first surface into the semiconductor substrate and a flexible dielectric material at least partially filling the gap,
wherein a length of the gap into the semiconductor substrate is smaller than a thickness of the semiconductor substrate.
2. The semiconductor device of
3. The semiconductor device of
4. The semiconductor device of
5. The semiconductor device of
6. The semiconductor device of
7. The semiconductor device according to
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The present method relates generally to the field of semiconductor fabrication and, more specifically, to preparing through silicon interconnects in semiconductor substrates.
To increase the functionality and density of semiconductor devices multiple semiconductor chips are stacked on a substrate or on each other. For instance, chips with the same functions, e.g., memory chips are stacked to increase the memory density or chips with different functions, e.g., processor chip and memory chip are stacked to minimize the processing time. Usually a first chip is mounted on a substrate. A second chip is then mounted onto the upper side of the first chip.
In the so called Through Silicon Interconnect Technology (TSV—Through Silicon Via), electric connections between chips, or between substrate and chip are led directly through the chip. At this, via holes are formed directly into the semiconductor substrate. The inner surface of the via holes is passivated and the via hole are filled with conductive material.
For stacking at chip level or at wafer level, the chips or the wafers each having a plurality of semiconductor chips are stacked on each other. Chips and wafers are prepared using any conventional semiconductor manufacturing process. Each semiconductor chip is provided with a plurality of interconnect elements mostly comprising a through electrode and a bump wherein a bump is formed on at least one end surface of the through electrodes.
A plurality of such chips or wafers are then sequentially stacked so that the corresponding through electrodes or bumps of adjacent chips are aligned and brought into contact so as to provide electric connection between vertical adjacent chips. In stacking at wafer level, the stacked wafers are then divided into individual chip stack packages.
A semiconductor device is configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole extending from an upper side to a bottom side of the semiconductor substrate. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrically isolated from the semiconductor substrate and comprises a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material.
To manufacture a device as above described, a dielectric layer is formed on the inner surface of a through hole extending in a semiconductor substrate from its upper side to its bottom side. Inside the through hole a through silicon conductor is formed. Furthermore a gap is formed into the semiconductor substrate, wherein the gap surrounds the through silicon conductor and extends from one side of the semiconductor substrate into the semiconductor substrate. The gap is filled with a flexible dielectric material.
The present device and method will be more completely understood through the following detailed description, which should be read in conjunction with the attached drawings. In this description, like numbers refer to similar elements within various embodiments of the present invention. Within this detailed description, the claimed invention will be explained with respect to preferred embodiments. However, the skilled person will readily appreciate that the methods and systems described herein are merely exemplary and that variations can be made.
The semiconductor device according to
Semiconductor substrates are referred to as diverse substrates that can be integrated into a stack of semiconductor devices, e.g., silicon chips or semiconductor interposer, which can serve the connecting and holding of components in a stack. The sides of the semiconductor substrate will be referred to as upper and bottom side of the semiconductor substrate in the following also identified as upper and bottom according to its illustration in
The part of the through silicon conductor 6 extending beyond the bottom side 3 of the semiconductor substrate 1 forms a conductor bump 8, that can be used to connect the semiconductor device to another device (not shown). The conductor bump can be also covered by a contact pad (not shown), which may have a larger size than the contact bump. This connection of the semiconductor device according to
The through silicon conductor 6 inside the semiconductor substrate 1 is completely surrounded by dielectrical material and is in this way electrically insulated from the semiconductor substrate 1. The insulation is realized by a dielectric layer 10 surrounding the through silicon conductor 6 at an upper part of the through hole 4 adjacent to the upper side 2 of the semiconductor substrate 1. At a lower part of the through hole 4 adjacent to the bottom side 3 of the semiconductor substrate 1, the insulation is carried out by a dielectric flexible material 14 filling a gap 12.
The dielectric layer 10 can include diverse materials provided that these materials with respect to their thickness provide the required electrical isolation and capacitive signal decoupling between the through silicon conductor 6 and the semiconductor bulk 7. For instance, the dielectric layer 10 can be an oxide of the semiconductor deposited by passivation of the semiconductor. Further, nitride of the semiconductor, polymers or the like can be used.
Adjacent to the dielectric layer 10 is the dielectric flexible material 14 embedding the through silicon conductor 6 at its lower part. The shape and thickness of the dielectric flexible material 14 is determined by the gap 12. Taking the perspective from the bottom side 3 inside the semiconductor substrate 1, the gap 12 has a tapered form in the present embodiment. Different forms of the gap 12 are possible depending on the process of manufacturing of the gap and on the thickness of the dielectric flexible material 14 to be manufactured. The thickness of the dielectric flexible material 14 can be manufactured in a larger manner through the filling of the gap 12 compared to the thickness of the dielectric layer 10. The mean width of the gap 12 in an embodiment is bigger than the thickness of the dielectric layer. The increased thickness enables a decrease/decline of the capacitive signal coupled between the through silicon conductor 6 and the semiconductor substrate 1. This effect can be selectively adjusted to the point by the choice of the dielectric material and the shape of the gap 12. Diverse low-k dielectric can be used as the dielectric flexible material 14. For instance, polymers with permittivity within a range of 2.5 can be used and can bring an additional decoupling effect in comparison to a thin oxide layer.
By means of a thicker flexible dielectric embedding the through silicon conductor 6, a compliant and flexible interconnect element is provided. This interconnect element can be attached to a PCB or a laminate substrate, whose coefficient of thermal expansion (CTE) deviates from the CTE of the semiconductor substrate, and thus, can compensate any possible thermo-mechanical stress. By using polymer with a high elasticity, i.e., with a low Young's modulus, there is a certain compliance of this end of the through silicon conductor 6 which enables the interconnection in a stack. The compliance is referred to as an external shear force affecting the connection between the through silicon conductor 6 and a further component (not shown). In the case of assembling the interconnect of the described semiconductor device to a non-CTE adapted material, the through silicon conductor 6 can be elastically deformed thereby preventing a fatigue and mechanical failure.
In one embodiment, at least the bottom side 3 of the semiconductor substrate 1 is covered by a layer of a dielectric, e.g., a layer of the dielectric flexible material. Alternatively, other suitable dielectric can be used.
In
In contrast to
The upper semiconductor substrate 15 comprises a redistribution layer 22 on its upper side 2 connected electrically to a through silicon conductor 6. The through silicon conductor 6 extends in a through hole 4 in the upper semiconductor substrate 15 from the redistribution layer 22 through the upper semiconductor substrate 15 to its bottom side 3 and beyond it. The through silicon conductor 6 inside the through hole 4 is surrounded by a dielectric layer described above.
The part of the through silicon conductor 6 extending beyond the bottom side 3 of the semiconductor substrate 1 forms a conductor bump 8 serving to connect the through silicon conductor 6 of the upper semiconductor substrate 15 with a through silicon conductor 6 of the lower semiconductor substrate 16, e.g., via a solder ball 20. The solder ball 20 connects the conductor bump of the upper semiconductor substrate 15 with a contact pad 18 formed on a side of a interconnect element which faces the upper semiconductor substrate 15 inside the lower semiconductor substrate 16. The upper semiconductor substrate 15 is electrically connected with a contact pad 18 of the supporting substrate 17 through this interconnect element.
The interconnect element of the lower semiconductor substrate 16 comprises a through silicon conductor 6 formed inside a through hole 4 that is electrically insulated from the bulk 7 of the lower semiconductor substrate 16. The lower semiconductor substrate 16 is surrounded by a gap 12 on its bottom side 3 facing the supporting substrate 17. The gap 12 is filled with a dielectric flexible material 14. Further, the bottom side 3 of the lower semiconductor substrate 16 is covered by the dielectric flexible material 14. The embodiment of the interconnect element of the lower semiconductor substrate 16 accords in the present embodiment of the semiconductor device with the one in
In the presented embodiment, the upper semiconductor substrate 15 has no compliant interconnect element because both stacked semiconductor substrates 1 have a comparable thermal expansion behavior. As a matter of course, both semiconductor substrates 1 can have compliant interconnect elements which are formed either comparable or differing from each other irrespective of the substrates' thermal expansion behavior. Likewise, more than two semiconductor substrates 1 can be stacked.
Even though in
Forming the gap 12 into the semiconductor substrate 1 can be done e.g. by an isotropic or anisotropic etch process. Diverse wet etching processes (e.g.,
In a subsequent step, the gap 12 is filled with a dielectric flexible material 14, e.g., a suitable polymer so that the dielectric flexible material 14 embeds the uncovered end of the through silicon conductor 6 (
Another way could be filling the gap 12 after stripping the mask. The filling process of the dielectric flexible material 14 can be executed with or without a structure definition for the filling by, e.g., lithography or the like. Furthermore, it can comprise a deposition of a layer of the dielectric flexible material 14 covering the bottom side 3 of the semiconductor substrate 1 (
For forming a conductor bump 8, the upper side and the dielectric flexible material 14 and the dielectric layer 10 are planar etched so that a part of the through silicon conductor 6 extends out of the etched surface and which forms the conductor bump 8 (
A starting point for another embodiment of the method for manufacturing a semiconductor device with an interconnect element is again a semiconductor substrate 1 with a through hole 4 (
By use of RIE (Reactive Ion Etching), a planar etching back of the bottom side 3 of the semiconductor substrate 1, and simultaneously an isotropic etching of the semiconductor substrate 1 and the dielectric layer 10 occurs along the through silicon conductor 6 for forming the gap 12. Subsequently to the etch process, a planar bottom side 3 of the semiconductor substrate 1 and a tapered gap 12 are formed running along the through silicon conductor 6 into the semiconductor substrate 1 (
With then depositing a dielectric flexible material 14 by, e.g., spin coating, the gap 12 is completely filled and at the same time the bottom side 3 of the semiconductor substrate 1 as well as the through silicon conductor 6 is evenly covered with a layer (
In further embodiments, the method for manufacturing the gap 12 is modified in a way that the width of the gap 12 can be selectively adjusted to the point in a self aligned etch process. And it is for this purpose that the through silicon conductor 6 inside the semiconductor substrate 1 is embedded by two layers, a dielectric layer 10 as described above (hereinafter referred to as first dielectric layer 10) and a second dielectric layer 11. The second dielectric layer 11 just like the first dielectric layer 10 can be used for capacitive signal decoupling between the through silicon conductor 6 and the semiconductor bulk 7, because of its dielectric characteristics. At the same time, the second dielectric layer serves as a sacrificial layer for adjusting the width of the gap 12. Hereinafter, the layer covering the inner surface 5 of the semiconductor through hole 4 should be referred to as first dielectric layer 11. And the layer arranged between the first dielectric layer 10 and the through silicon conductor 6 should be referred to as second dielectric layer 11.
With this, a planar etch back process as described above occurs. Subsequent to the etch process, the base area 13 of the gap 12 adjoins the second dielectric layer 11 according to this embodiment. Because of the above described selective etching behavior, the width of the base area 13 is as big as the thickness of the second dielectric layer 11, so that the width of the gap 12 can be adjusted through the thickness of the second dielectric layer 11. The first dielectric layer 10 within the area of the gap 12 is removed through a suitable choice of materials of the first dielectric layer 10 as, e.g., a passivation layer of the semiconductor substrate 1. Therefore, only the through silicon conductor 6 projects into the gap 12 (
Following, as per
For manufacturing a gap 12 having a suitable form, the first dielectric layer 10 consists of such a material whose etching rate is higher than the etching rate of the semiconductor. Furthermore, the second dielectric layer 11 is made of a material which is in comparison to the first dielectric layer 10 etched only a little while the gap 12 is formed. Thus, the second dielectric layer 11 almost entirely embeds the through silicon conductor 6 after the etching process. Solely, a small part of the through silicon conductor 6 is laid open. This forms the conductor bump 8. As already described further above, in this process the width of the gap 12 is adjusted through the thickness of the sacrificial layer, though in this case, it is through the thickness of the first dielectric layer 10. For filling the gap 12 and depositing the planar layer for insulating the semiconductor substrate 1 (
Hedler, Harry, Irsigler, Roland, Wolter, Andreas
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