A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
|
1. A method for operating a non-volatile storage system, comprising:
setting a first group of non-volatile storage elements into an active state, said setting a first group of non-volatile storage elements into said active state includes biasing a plurality of first control lines to one or more unselected voltages, each first control line is coupled to a subset of said first group of non-volatile storage elements;
setting a second group of non-volatile storage elements into an inactive state, each non-volatile storage element of a subset of said second group of non-volatile storage elements is coupled to one of a plurality of second control lines; and
transitioning said second group of non-volatile storage elements from said inactive state to said active state, said transitioning includes sharing charge between said plurality of first control lines and said plurality of second control lines.
13. A method for operating a non-volatile storage system, comprising:
biasing a plurality of first control lines, each first control line is coupled to a respective subset of a first plurality of non-volatile storage elements, said first plurality of non-volatile storage elements are part of a first memory block;
floating a plurality of second control lines, each second control line is coupled to a respective subset of a second plurality of non-volatile storage elements, said second plurality of non-volatile storage elements are part of a second memory block; and
setting up read conditions for said second plurality of non-volatile storage elements, said setting up read conditions includes sharing charge between said plurality of first control lines and said plurality of second control lines, said plurality of first control lines comprise a plurality of unselected bit lines, each unselected bit line is biased to one or more unselected bit line voltages prior to said setting up read conditions.
19. A non-volatile storage system, comprising:
a first memory block comprising a plurality of first control lines, said first memory block set into a read state;
a second memory block comprising a plurality of second control lines, said second memory block set into an inactive state;
a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit controls charge sharing between said plurality of first control lines and said plurality of second control lines during a transitioning of said second memory block from said inactive state into said read state; and
a latch, said latch latches a first block enable signal associated with said first memory block during said transitioning, said first block enable signal controls the electrical coupling of said plurality of first control lines to said plurality of second control lines, said plurality of second control lines comprise a plurality of unselected bit lines.
11. A method for operating a non-volatile storage system, comprising:
decoding a read command from a host;
identifying a set of memory blocks that contain requested data to be read;
setting a first memory block into a read state, said first memory block comprises a first plurality of bit lines, said first plurality of bit lines are biased to one or more unselected bit line voltages when said first memory block is in said read state;
setting a second memory block into an inactive state, said second memory block comprises a second plurality of bit lines, said second plurality of bit lines are floated when said second memory block is in said inactive state;
reading data from said first memory block;
transitioning said first memory block into said inactive state and said second memory block into said read state, said transitioning includes sharing charge between said first memory block and said second memory block;
reading data from said second memory block; and
outputting the data read to said host.
16. A non-volatile storage system, comprising:
non-volatile storage elements including a first set of said non-volatile storage elements and a second set of said non-volatile storage elements;
a plurality of first control lines, each first control line is coupled to a respective subset of said first set of non-volatile storage elements;
a plurality of second control lines, each second control line is coupled to a respective subset of said second set of non-volatile storage elements; and
a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a first switch, said first switch controls charge sharing between said plurality of first control lines and said plurality of second control lines while setting up read conditions for said second set of non-volatile storage elements, said plurality of first control lines comprise a plurality of unselected bit lines, said plurality of unselected bit lines are biased to one or more unselected bit line voltages prior to said setting up read conditions.
20. A non-volatile storage system, comprising:
a first memory block comprising a plurality of first control lines, said first memory block set into a read state;
a second memory block comprising a plurality of second control lines, said second memory block set into an inactive state;
a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit controls charge sharing between said plurality of first control lines and said plurality of second control lines during a transitioning of said second memory block from said inactive state into said read state;
a latch, said latch latches a first block enable signal during said transitioning, said first block enable signal controls a first switch, said first switch controls the electrical coupling of said plurality of first control lines to an intermediate node; and
a second block enable signal, said second block enable signal controls a second switch, said second switch controls the electrical coupling of said plurality of second control lines to said intermediate node, said first block enable signal turns on said first switch at the same time said second block enable signal turns on said second switch.
12. A method for operating a non-volatile storage system, comprising:
decoding a read command from a host;
identifying a set of memory blocks that contain requested data to be read;
setting a first memory block into a read state, said first memory block comprises a plurality of first control lines;
setting a second memory block into an inactive state;
reading data from said first memory block;
transitioning said first memory block into said inactive state and said second memory block into said read state, said transitioning includes sharing charge between said first memory block and said second memory block, said transitioning includes controlling a charge transfer circuit, said charge transfer circuit is coupled to both said first memory block and said second memory block, said charge transfer circuit comprises a switch, said transitioning includes turning off said switch during charge sharing to prevent the electrical coupling of one or more unselected voltages to said plurality of first control lines, said transitioning includes latching a first block enable signal, said first block enable signal is an input to said charge transfer circuit and controls charge sharing between said first memory block and said second memory block during said transitioning;
reading data from said second memory block; and
outputting the data read to said host.
15. A method for operating a non-volatile storage system, comprising:
biasing a plurality of first control lines, each first control line is coupled to a respective subset of a first plurality of non-volatile storage elements, said non-volatile storage elements comprise two-terminal non-volatile memory cells;
floating a plurality of second control lines, each second control line is coupled to a respective subset of a second plurality of non-volatile storage elements; and
setting up read conditions for said second plurality of non-volatile storage elements, said setting up read conditions includes sharing charge between said plurality of first control lines and said plurality of second control lines, said setting up read conditions includes latching a first block enable signal, said first block enable signal controls a first switch, said first switch controls the electrical coupling of said plurality of first control lines to an intermediate node, said setting up read conditions includes generating a second block enable signal, said second block enable signal controls a second switch, said second switch controls the electrical coupling of said plurality of second control lines to said intermediate node, said setting up read conditions includes said first block enable signal turning on said first switch at the same time said second block enable signal turns on said second switch.
18. A non-volatile storage system, comprising;
non-volatile storage elements including a first set of said non-volatile storage elements and a second set of said non-volatile storage elements;
a plurality of first control lines, each first control line is coupled to a respective subset of said first set of non-volatile storage elements, said plurality of first control lines comprise a plurality of unselected word lines;
a plurality of second control lines, each second control line is coupled to a respective subset of said second set of non-volatile storage elements; and
a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a first switch, said first switch controls charge sharing between said plurality of first control lines and said plurality of second control lines while setting up read conditions for said second set of non-volatile storage elements, said plurality of second control lines are not biased to any voltage prior to said setting up read conditions, said setting up read conditions includes latching a first block enable signal, said first block enable signal controls said first switch, said first switch controls coupling of said plurality of first control lines to an intermediate node, said setting up read conditions includes generating a second block enable signal, said second block enable signal controls a second switch, said second switch controls coupling of said plurality of second control lines to said intermediate node, said setting up read conditions includes said first block enable signal turning on said first switch at the same time said second block enable signal turns on said second switch.
2. A method according to
floating said plurality of second control lines when said second group of non-volatile storage elements is in said inactive state;
reading data from said second group of non-volatile storage elements when said second group of non-volatile storage elements is in said active state; and
outputting said data read to a host.
4. A method according to
said transitioning includes controlling a charge transfer circuit, said charge transfer circuit is coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a switch, said transitioning includes turning off said switch during charge sharing to prevent the electrical coupling of said one or more unselected voltages to said plurality of first control lines.
5. A method according to
said first group of non-volatile storage elements is part of a first memory block;
said second group of non-volatile storage elements is part of a second memory block, said first memory block and said second memory block are in a common memory bay;
said plurality of first control lines comprise a plurality of bit lines; and
said non-volatile storage elements comprise two-terminal non-volatile memory cells.
6. A method according to
said transitioning includes latching a first block enable signal, said first block enable signal is an input to a charge transfer circuit, said charge transfer circuit is coupled to said plurality of first control lines and to said plurality of second control lines, said first block enable signal controls the electrical coupling of said plurality of first control lines to said plurality of second control lines during said transitioning; and
said transitioning includes changing said first group of non-volatile storage elements from said active state to said inactive state.
7. A method according to
said transitioning includes latching a first block enable signal, said first block enable signal controls a first switch, said first switch controls the electrical coupling of said plurality of first control lines to an intermediate node; and
said transitioning includes generating a second block enable signal, said second block enable signal controls a second switch, said second switch controls the electrical coupling of said plurality of second control lines to said intermediate node, said transitioning includes said first block enable signal turning on said first switch at the same time said second block enable signal turns on said second switch.
9. A method according to
said plurality of first control lines are biased to one or more unselected voltages in a set mode.
10. A method according to
said plurality of first control lines are biased to one or more unselected voltages in a RESET mode.
14. A method according to
said setting up read conditions includes controlling a charge transfer circuit, said charge transfer circuit includes a first switch and a second switch, said first switch electrically couples said plurality of first control lines to an intermediate node, said second switch electrically couples said intermediate node to said one or more unselected bit line voltages, said controlling the charge transfer circuit includes turning off said second switch during charge sharing to prevent the electrical coupling of said one or more unselected bit line voltages to said intermediate node, said controlling the charge transfer circuit includes latching a first enable signal, said first enable signal controls said first switch during said setting up read conditions.
17. The non-volatile storage system of
a latch, said first set of non-volatile storage elements is part of a first memory block, said latch latches a first block enable signal associated with said first memory block during said setting up read conditions, said first block enable signal controls said first switch.
|
1. Field
The present invention relates to technology for data storage.
2. Description of the Related Art
Non-volatile memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, mobile computing devices, and non-mobile computing devices. Non-volatile memory allows information to be stored and retained even when an electronic device is not connected to a source of power (e.g., a battery). Three characteristics of a non-volatile memory device include its cost, energy consumption, and performance. The performance characteristic of a non-volatile memory device includes the time necessary to write information to the memory device and the time necessary to read information from the memory device.
Many commercially available non-volatile memory devices (e.g., NAND flash memory cards) contain two-dimensional arrays of non-volatile memory cells. The memory cells within a two-dimensional array form a single layer of memory cells and are selected via control lines in the X and Y directions. Two-dimensional arrays are typically formed on top of a silicon substrate. In contrast, the memory cells within a monolithic three-dimensional array form multiple “vertically aligned” layers of memory cells and are selected via control lines in the X, Y, and Z directions. A monolithic three-dimensional array is one in which multiple layers of memory cells are formed above a single substrate with no intervening substrates. Three-dimensional arrays of memory cells may be cheaper to fabricate than two-dimensional arrays of memory cells if the additional cost of forming multiple “vertically aligned” layers of memory cells is less than the cost of forming either wider or a greater number of two-dimensional arrays (i.e., if the cost of building memory layers vertically is less than the cost of building memory layers horizontally).
Three-dimensional memory arrays having more than one layer of memory cells have been formed by vertically aligning two-dimensional cross-point memory arrays. A cross-point memory array is one in which memory cells are placed at the intersection of a first set of control lines and a perpendicular second set of control lines. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” and in U.S. Pat. No. 5,835,396 to Zhang, entitled “Three-Dimensional Read-Only Memory Array.”
One example of a non-volatile memory device comprises one or more memory bays (or other groupings). Each memory bay (or other grouping) comprises one or more memory blocks that include a grouping of non-volatile storage elements. Structures other than blocks can also be used. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
Referring to
Referring again to
In some embodiments, row decoder 304 and/or column decoder 302 can be split or shared between memory arrays. One embodiment of a memory bay 332, depicted in
A simplified schematic diagram including word lines and bit lines and corresponding to memory bay 332 is depicted in
The memory block 310 depicted in
Memory array 201 includes a plurality of memory cells 200. The memory cells 200 can be write-once memory cells or re-writeable memory cells. With respect to first memory level 218, memory cells 200 are between and connect to a set of bit lines 206 and a set of word lines 208. With respect to second memory level 220, memory cells 200 are between and connect to a set of bit lines 210 and word lines 208. In one embodiment, each memory cell includes a steering element (e.g., a diode) and a state change element. In one embodiment, the diodes of the first memory level 218 may be upward pointing diodes as indicated by arrow A1 (e.g., with p regions at the bottom of the diodes), while the diodes of the second memory level 220 may be downward pointing diodes as indicated by arrow A2 (e.g., with n regions at the bottom of the diodes), or vice versa. In another embodiment, each memory cell includes only a state change element. Many different types of memory cells can be used.
In one embodiment, the memory cells 200 are re-writable. For example, U.S. Patent Application Publication No. 2006/0250836, which is incorporated herein by reference in its entirety, describes a rewriteable non-volatile memory cell that includes a diode coupled in series with a reversible resistance-switching element. A reversible resistance-switching element includes reversible resistivity-switching material having a resistivity that may be reversibly switched between two or more states. In some embodiments, the reversible resistance-switching material may be formed from a metal oxide. Various different metal oxides can be used. In one example, nickel oxide is used. Examples of various memory cells can be found in U.S. Pat. No. 6,034,882; U.S. Pat. No. 6,525,953; U.S. Pat. No. 6,952,043; U.S. Pat. No. 6,420,215; U.S. Pat. No. 6,951,780; and U.S. Pat. No. 7,081,377. No particular type of memory cell is required to implement the memory block switching technique disclosed herein.
In one embodiment of a read operation, the data stored in one of the plurality of memory cells 200 is read by biasing one of the set of word lines (i.e., the selected word line) to the selected word line voltage in read mode (e.g., 0V). A read circuit is used to bias the bit line connected to the selected memory cell to the selected bit line voltage in read mode (e.g., 2V). For purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via another part). To avoid sensing leakage current from the selected bit line to many unselected word lines, the unselected word lines are biased to the same voltage as the selected bit lines (e.g., 2V). To avoid leakage current from the unselected bit lines to the selected word line, the unselected bit lines can be biased to the same voltage as the selected word line (e.g., 0V). The read circuit then senses the amount of current through the selected memory cell (e.g., by comparing, over time, the voltage of a precharged node connected to the selected memory cell with a reference voltage).
In another embodiment of a read operation, the selected word line is biased to −1.6V, the selected bit lines are biased to 0V, the unselected word lines are biased to 0V, and the unselected bit lines are biased to −1.6V. The read circuit then senses the amount of current conducted by the selected memory cell.
In one embodiment of a write operation, the process of switching the resistance of a memory cell element from a high-resistivity state to a low-resistivity state is referred to as SETTING the reversible resistance-switching element. The process of switching the resistance from the low-resistivity state to the high-resistivity state is referred to as RESETTING the reversible resistance-switching element. The high-resistivity state is associated with binary data “0” and the low-resistivity state is associated with binary data “1.” In other embodiments, SETTING and RESETTING and/or the data encoding can be reversed. In some embodiments, the first time a resistance-switching element is SET requires a higher than normal voltage and is referred to as a FORMING operation.
In one embodiment of a write operation, the reversible resistance-switching material may be in an initial high-resistivity state upon fabrication that is switchable to a low-resistivity state upon application of a first voltage and/or current. Application of a second voltage and/or current may return the reversible resistance-switching material back to the high-resistivity state. Alternatively, the reversible resistance-switching material may be in an initial low-resistance state upon fabrication that is reversibly switchable to a high-resistance state upon application of the appropriate voltage(s) and/or current(s). When used in a memory cell, one resistance state may represent a binary data “0” while another resistance state may represent a binary data “1.” However, more than two data/resistance states may be used.
In one embodiment of a write operation, the resistance-switching element of one of a plurality of memory cells 200 is SET by biasing the selected word line to the selected word line voltage in SET mode (e.g., −0.6V). A write circuit is used to bias the bit line connected to the selected memory cell to the selected bit line voltage in SET mode (e.g., 7.4V). Therefore, the selected memory cell in SET mode is forward biased, similar to a read operation except with a larger voltage range. The unselected word lines are biased to 6.8V and the unselected bit lines are biased to 0V. Placing a voltage of 6.8V across the unselected memory cells associated with the intersection of unselected word lines and unselected bit lines reduces the amount of leakage current through the unselected memory cells, as compared to placing the 8V found across the selected memory cell. Other SET biasing schemes can also be used (e.g., placing a voltage of 5V across the selected memory cell, rather than 8V).
In one embodiment of a write operation, the resistance-switching element of one of a plurality of memory cells 200 is SET by biasing the selected word line to −8V, the selected bit lines to 0V, the unselected word lines to 0V, and the unselected bit lines to −8V.
In one embodiment of a write operation, the resistance-switching element of one of a plurality of memory cells 200 is RESET by biasing the selected word line to the selected word line voltage in RESET mode (e.g., 7V). A write circuit is used to bias the bit line connected to the selected memory cell to the selected bit line voltage in RESET mode (e.g., −7V). Therefore, the selected memory cell in RESET mode is reverse biased. The unselected word lines are biased to 0V and the unselected bit lines are biased to 0V. Biasing the unselected word lines and the unselected bit lines to the same voltage during a RESET operation reduces the amount of leakage current through the unselected memory cells, as compared to the SET operation described above.
In one embodiment, a memory core 103, as depicted in
Vias can be used to make connections between adjacent routing layers. Multi-layer vias can be used to make connections between more than 2 layers. Information regarding multi-layer vias using less than one masking step per layer can be found in U.S. Pat. No. 6,034,882.
Though larger memory arrays are more area efficient, their size may be limited for a variety of reasons. For example, the signal delays traversing down word lines and bit lines which arise from the resistance and the capacitance of such lines (i.e., the RC delays) may be very significant in a large array. These RC delays may be reduced by subdividing the larger array into a group of smaller sub-arrays so that the length of each word line and/or each bit line is reduced. As another example, the power associated with accessing a group of memory cells may dictate an upper limit to the number of memory cells which may be accessed simultaneously during a given memory operation. Consequently, a large memory array may be subdivided into smaller sub-arrays to decrease the number of memory cells which are simultaneously accessed.
Referring to the read/write circuit depicted in
During the read operation, read/write circuit 502 biases the selected bit line to 2V (i.e., the selected bit line voltage in read mode). Prior to sensing data, read/write circuit 502 will precharge the Vsense node to 4V. When sensing data, read/write circuit 502 attempts to regulate the SELB node to 2V via clamp control circuit 564 and transistor 562 in a source-follower configuration. If the current through the selected memory cell 550 is greater than the read current limit, Iref, then, over time, the Vsense node will fall below Vref-read (e.g., set to 3V) and the sense amplifier 566 will read out a data “0.” Outputting a data “0” represents that the selected memory cell 550 is in a low resistance state (e.g., a SET state). If the current through the selected memory cell 550 is less than Iref, then the Vsense node will stay above Vref-read and the sense amplifier 566 will read out a data “1.” Outputting a data “1” represents that the selected memory cell 550 is in a high resistance state (e.g., a RESET state). Data latch 568 will latch the output of sense amplifier 566 after a time period of sensing the current through the selected memory cell (e.g., 400 ns).
In one embodiment, during a write operation, if the data in terminal requests a data “0” to be written to a selected memory cell, then read/write circuit 502 biases SELB to the selected bit line voltage in write mode (e.g., 7.4V for a SET operation) via write circuit 560. The duration of programming the memory cell can be a fixed time period (e.g., using a fixed-width programming pulse) or variable (e.g., using a write circuit 560 that senses whether a memory cell has been programmed while programming). Information regarding write circuits that can sense while programming data can be found in U.S. Pat. No. 6,574,145. If the data in terminal requests a data “1” to be written, then write circuit 560 biases SELB to the unselected bit line voltage in write mode (e.g., 0V for a SET operation).
In one embodiment, when memory array 602 is in an active state, row decoder 608 selects a single word line and column decoder 604 selects a single bit line (i.e., XCS[2] is low, while XCS[1] and XCS[3] are high). When memory array 602 is active, column decoder 604 electrically couples the selected bit line 692 to the SELB[1] node, which is connected to read/write circuits 606. Column decoder 604 also biases the unselected bit lines 691 and 693 to VUB, the unselected voltage for bit lines. Though the depicted portion of column decoder 604 only selects one bit line per memory block 601, more than one bit line per memory block 601 may be selected. In one embodiment, column decoder 604 selects 32 bit lines per memory block. For example, column decoder 604 controls 32 subsets of bit lines and electrically couples one bit line from each of the 32 subsets of bit lines to a SELB node (i.e., to one of SELB[31:0]). In one embodiment, unselected bit lines may be biased to one or more unselected bit line voltages (e.g., in a read operation, the one or more unselected bit line voltages may include −1.6V, −1.5V, and −1.7V). In another embodiment, unselected word lines may be biased to one or more unselected word line voltages (e.g., in a SET operation, the one or more unselected word line voltages may include 6.8V, 6.7V, and 6.9V).
In one embodiment, when memory array 602 is in an inactive state, row decoder 608 biases all word lines (i.e., there is no selected word line) to an unselected word line voltage. Column decoder 604 biases all bit lines (i.e., there is no selected bit line) to an unselected bit line voltage. In another embodiment, row decoder 608 floats all word lines and column decoder 604 floats all bit lines. In one embodiment, memory bay 600 includes 16 memory blocks, one of the 16 memory blocks is in an active state and the other 15 memory blocks are in an inactive state.
Portion of a second block 882 includes a portion of second memory array 804 and a portion of a second column decoder 808. The second memory array 804 includes word lines 896-898, a bit line 895, and memory cells 820 which can either be one-time or many-time programmable memory cells. As depicted in
In one embodiment, first memory array 802 and second memory array 804 include a plurality of word lines and a plurality of bit lines. In another embodiment, portion of a first column decoder 806 and portion of a second column decoder 808 comprise a plurality of bit line decoders. The word lines 896-898 of second memory array 804 may be biased to an unselected word line voltage or floated. The bit line 895 of second memory array 804 may be biased to an inactive unselected voltage (e.g., 0V) or floated. Referring to
Charge transfer circuit 840 includes NMOS transistors 866, 862, and 864. NMOS transistor 866 couples node VUB, biased to the unselected bit line voltage, to node VUB_TRI, which is a node that can either be biased to a particular voltage or floated. NMOS transistor 862 couples node NVUB[1] to VUB_TRI and is controlled by BLKEN[1]. NMOS transistor 864 couples node NVUB[2] to VUB_TRI and is controlled by BLKEN[2]. NMOS transistor 866 couples node VUB to VUB_TRI and is controlled by XBLKSW.
During a memory operation, first memory array 802 is initially in an active state with its unselected bit lines biased to an unselected bit line voltage. Second memory array 804 is initially in an inactive state with its bit lines floating. The process of transitioning the second memory array 804 into the active state includes turning off transistor 866 and turning on transistors 862 and 864 at the same time. Turning on transistors 862 and 864 at the same time creates a conductive path between nodes NVUB[1] and NVUB[2]. Along with portion of column decoder 806 selecting NVUB[1] for its unselected bit lines and portion of column decoder 808 selecting NVUB[2] for its unselected bit lines, a conductive path between the unselected bit lines in first memory array 802 and the unselected bit lines in second memory array 804 is formed and charge sharing occurs. After charge sharing occurs, first memory array 802 is placed into the inactive state and second memory array 804 is placed into the active state.
The timing diagram shown in
In one embodiment, the capacitance between unselected bit lines and unselected word lines in a first memory block in an active state is several nanofarads. Referring to
During a memory operation, first memory array 802, corresponding to portion of first block 880, is initially in an active state (e.g., in a read state or a write state) and its unselected bit lines are biased to the unselected voltage for bit lines. Second memory array 804, corresponding to portion of second block 882, is initially in an inactive state. As depicted in
Referring to
Portion of a second block 1082 includes a second memory array 1004 and a portion of a second row decoder 1008. The second memory array 1004 includes bit lines 1096-1098, a word line 1095, and memory cells 1020 which can either be one-time or many-time programmable memory cells. Word line 1095 is floated when second memory array 1004 is in an inactive state. Portion of a second row decoder 1008 includes a word line decoder formed by transistors 1052 and 1054 and controlled by node RSEL[17]. The NMOS transistor 1054 couples node XSELW[2] to word line 1095 in second memory array 1004. The PMOS transistor 1052 couples node NVUW[2] to word line 1095 in second memory array 1004. In one embodiment, first memory array 1002 and second memory array 1004 include a plurality of word lines and a plurality of bit lines. In another embodiment, portion of a first row decoder 1006 and portion of a second row decoder 1008 comprise a plurality of word line decoders. The bit lines 1096-1098 of second memory array 1004 may be biased to an unselected bit line voltage or floated. The word line 1095 of second memory array 1004 may be biased to an inactive unselected voltage or floated. Referring to
Charge transfer circuit 1040 includes PMOS transistors 1066, 1062, and 1064. PMOS transistor 1066 couples node VUW, biased to the unselected word line voltage, to node VUW_TRI, which is a node that can either be biased to a particular voltage or floated. PMOS transistor 1062 couples node NVUW[1] to VUW_TRI and is controlled by XBLKEN[1]. PMOS transistor 1064 couples node NVUW[2] to VUW_TRI and is controlled by XBLKEN[2]. PMOS transistor 1066 couples node VUW to VUW_TRI and is controlled by BLKSW.
During a memory operation, first memory array 1002, corresponding to portion of a first block 1080, is initially in an active state (e.g., in a read state or a write state) and its unselected word lines are biased to the unselected voltage for word lines. Second memory array 1004, corresponding to portion of a second block 1082, is initially in an inactive state. Charge transfer circuit 1040 can be operated in a fashion similar to that of charge transfer circuit 840 in
In one embodiment, memory arrays 1002 and 1004 depicted in
One embodiment includes setting a first group of non-volatile storage elements into an active state, setting a second group of non-volatile storage elements into an inactive state, each non-volatile storage element of a subset of the second group of non-volatile storage elements is coupled to one of a plurality of second control lines and transitioning the second group of non-volatile storage elements from the inactive state to the active state. The setting a first group of non-volatile storage elements into the active state includes biasing a plurality of first control lines to one or more unselected voltages. Each first control line is coupled to a subset of the first group of non-volatile storage elements. The transitioning includes sharing charge between the plurality of first control lines and the plurality of second control lines.
One embodiment includes decoding a read command from a host, identifying a set of memory blocks that contain the requested data to be read, setting a first memory block into a read state, setting a second memory block into an inactive state, and reading data from the first memory block. The embodiment further includes transitioning the first memory block into the inactive state and the second memory block into the read state, reading data from the second memory block, and outputting the data read to the host. The transitioning includes sharing charge between the first memory block and the second memory block.
One embodiment includes biasing a plurality of first control lines, each first control line is coupled to a respective subset of a first plurality of non-volatile storage elements, floating a plurality of second control lines, each second control line is coupled to a respective subset of a second plurality of non-volatile storage elements, and setting up read conditions for the second plurality of non-volatile storage elements. The setting up read conditions includes sharing charge between the plurality of first control lines and the plurality of second control lines.
One embodiment includes non-volatile storage elements including a first set of the non-volatile storage elements and a second set of the non-volatile storage elements, a plurality of first control lines, each first control line is coupled to a respective subset of the first set of non-volatile storage elements, a plurality of second control lines, each second control line is coupled to a respective subset of the second set of non-volatile storage elements, and a charge transfer circuit. The charge transfer circuit is coupled to both the plurality of first control lines and the plurality of second control lines. The charge transfer circuit comprises a first switch, the first switch controls charge sharing between the plurality of first control lines and the plurality of second control lines while setting up read conditions for the second set of non-volatile storage elements.
One embodiment includes a first memory block comprising a plurality of first control lines, the first memory block set into a read state, a second memory block comprising a plurality of second control lines, the second memory block set into an inactive state, and a charge transfer circuit coupled to both the plurality of first control lines and the plurality of second control lines. The charge transfer circuit controls charge sharing between the plurality of first control lines and the plurality of second control lines during a transitioning of the second memory block from the inactive state into the read state.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
Fasoli, Luca, Scheuerlein, Roy E, Yan, Thomas
Patent | Priority | Assignee | Title |
10304528, | Apr 27 2015 | Sony Semiconductor Solutions Corporation | Memory device, memory system, and memory control method |
11145363, | Sep 16 2019 | SK Hynix Inc. | Memory device including discharge circuit |
8223525, | Dec 15 2009 | SanDisk Technologies LLC | Page register outside array and sense amplifier interface |
8320196, | Aug 10 2009 | SanDisk Technologies LLC | Semiconductor memory with improved block switching |
8677216, | Mar 18 2010 | Samsung Electronics Co., Ltd. | Stacked semiconductor memory device and related error-correction method |
Patent | Priority | Assignee | Title |
5337273, | Jul 30 1993 | SGS-Thomson Microelectronics, Inc.; SGS-Thomson Microelectronics, Inc | Charge sharing flash clear for memory arrays |
6618295, | Mar 21 2001 | SanDisk Technologies LLC | Method and apparatus for biasing selected and unselected array lines when writing a memory array |
6711067, | May 08 2002 | Synopsys, Inc | System and method for bit line sharing |
6785179, | Jun 19 2003 | ARM Limited | Charge sharing between bit lines within a memory circuit to increase recharge speed |
6859392, | Aug 26 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Preconditioning global bitlines |
6879505, | Mar 31 2003 | SanDisk Technologies LLC | Word line arrangement having multi-layer word line segments for three-dimensional memory array |
7511986, | Jul 31 2006 | SAMSUNG ELECTRONICS CO , LTD | Semiconductor memory device |
20040141393, | |||
20040264281, | |||
20080159032, | |||
20090116271, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 07 2009 | YAN, THOMAS | SanDisk 3D LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023073 | /0533 | |
Aug 07 2009 | FASOLI, LUCA | SanDisk 3D LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023073 | /0533 | |
Aug 07 2009 | SCHEUERLEIN, ROY E | SanDisk 3D LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023073 | /0533 | |
Aug 10 2009 | SanDisk 3D LLC | (assignment on the face of the patent) | / | |||
Mar 24 2016 | SanDisk 3D LLC | SanDisk Technologies Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 038300 | /0665 | |
Mar 24 2016 | SanDisk 3D LLC | SanDisk Technologies Inc | CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 038520 | /0552 | |
May 16 2016 | SanDisk Technologies Inc | SanDisk Technologies LLC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 038807 | /0850 |
Date | Maintenance Fee Events |
Apr 15 2015 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Apr 18 2019 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Apr 19 2023 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Nov 01 2014 | 4 years fee payment window open |
May 01 2015 | 6 months grace period start (w surcharge) |
Nov 01 2015 | patent expiry (for year 4) |
Nov 01 2017 | 2 years to revive unintentionally abandoned end. (for year 4) |
Nov 01 2018 | 8 years fee payment window open |
May 01 2019 | 6 months grace period start (w surcharge) |
Nov 01 2019 | patent expiry (for year 8) |
Nov 01 2021 | 2 years to revive unintentionally abandoned end. (for year 8) |
Nov 01 2022 | 12 years fee payment window open |
May 01 2023 | 6 months grace period start (w surcharge) |
Nov 01 2023 | patent expiry (for year 12) |
Nov 01 2025 | 2 years to revive unintentionally abandoned end. (for year 12) |