A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.
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1. A semiconductor structure comprising:
a first semiconductor region coupled to a first terminal of the structure;
a second semiconductor region coupled to a second terminal of the structure;
a third semiconductor region disposed between the first and second semiconductor regions; and
at least first and second dielectric regions extending a first distance along a depth of the third semiconductor region, wherein said first and second semiconductor regions are of opposite conductivity types, and wherein the at least first and second dielectric regions or an interface region between each of said at least first and second dielectric regions and said third semiconductor regions includes intentionally introduced charges.
25. A semiconductor structure comprising:
a first semiconductor region coupled to a first terminal of the structure;
a second semiconductor region coupled to a second terminal of the structure;
a third semiconductor region disposed between the first and second regions;
a fourth semiconductor region extending a first distance along a depth of the third semiconductor region and having a conductivity type opposite a conductivity type of the third semiconductor region, said fourth semiconductor region being adjacent the first and second; and
at least first and second dielectric regions extending a second distance along a depth of the third semiconductor region, wherein said first and second semiconductor regions are of opposite conductivity types, wherein said fourth semiconductor region surrounds a portion of the at least first and second dielectric regions, and wherein said at least first and second dielectric regions or an interface region between each of said at least first and second dielectric regions and said fourth semiconductor regions includes intentionally introduced charges which are immobile at typical device operating temperatures.
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The present application claims benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 60/879,434, filed Jan. 9, 2007, entitled “Power MOS Transistor”, the content of which is incorporated herein by reference in its entirety.
The present invention relates to electronic devices, and more particularly to a semiconductor device adapted to sustain high voltages.
In electronic systems, there is often a need to sustain a relatively high voltage across a pair of nodes. Semiconductor p-n junction diodes are widely used in a reverse-bias mode to sustain high voltages. To sustain a high breakdown voltage across a p-n junction, a lightly doped region is required that is relatively thick and that forms a voltage sustaining layer. Such p-n junctions provide relatively higher breakdown voltage in many semiconductor devices such as MOSFETs, IGBTs and JFETs. Moreover, such semiconductor devices are typically required to have a relatively low on-resistance (Ron) in the on-state and a relatively high breakdown voltage VB under reverse bias conditions. As is well known, achieving both a high breakdown VB and a low Ron poses a number of challenging tasks. In conventional devices, design parameters such as the doping density or layer thickness that can be used to increase the breakdown voltage causes the on-resistance to increase, and vice versa.
One known device used to achieve both a low on-resistance as well as a high breakdown voltage is commonly referred to as the SuperJunction (SJ) device. As is shown in
In a SJ structure, the widths of the n-type and p-type pillars set a limit on the cell pitch and the scaling down of the structure. There are also a number of drawbacks associated with the manufacturing of a SJ structure, such as the requirement to grow multiple epitaxial layers and to perform a number of implant and diffusion steps. A need continues to exist for a semiconductor device that has a high breakdown voltage, a low Rsp, low capacitances and low reverse recovery charge (Qrr), is easily scaled down and is easier to manufacture.
A semiconductor structure, in accordance with one embodiment of the present invention, includes, in part, a number of semiconductor regions, at least a pair of dielectric regions and a pair of terminals. The first and second regions of the semiconductor structure are respectively coupled to the first and second terminals. The third region of the semiconductor structure is of a single conductivity type and is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the semiconductor structure. The electrical characteristic of the semiconductor structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types.
In one embodiment, the dielectric regions extend into the first and second regions. In one embodiment, the integrated density of doping impurities in the third region along a line parallel to a surface of the dielectric regions ranges from about 1×1012/cm2 to about 5×1012/cm2. In one embodiment, each dielectric region further includes a second material. In one embodiment, the second material in each dielectric region includes, in part, aluminum fluoride. In one embodiment, each dielectric region further includes, in part, a third material that is a dielectric material. In one embodiment, the second and third materials in each dielectric region are the same material.
In one embodiment, the first and second regions are respectively p+ type and n+ type regions, and the first and second terminals are respectively anode and cathode terminals. In one embodiment, the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and said first region is formed above the third region. In one embodiment, the dielectric regions are isolated from one another.
In one embodiment, the semiconductor structure further includes, in part, a fourth region disposed between the second and the third regions. The second and fourth regions are of the same conductivity type.
In one embodiment, the first and second regions are respectively n+ type and p+ type regions, and the first and second terminals are respectively cathode and anode terminals. In one embodiment, the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and the first region is formed above the third region. In one embodiment, the third region is formed above the second region and the first region is formed above the third region. In one embodiment, each of the dielectric region is tapered so as to have a larger width near one end of the dielectric region than another end of the dielectric region.
In one embodiment, the first, second and third regions are formed along the same surface of a semiconductor substrate in which the semiconductor structure is formed. In one such embodiment, the semiconductor structure includes a fourth region in which the second region is formed. In one such embodiment, the third region is adjacent the first and fourth regions. In one such embodiment, the first region is a p+ type region, the second region is an n+ type region, the third region is a p-type region and the fourth region is an n-type region. In another such embodiment, the first region is a p+-type region, the second region is an n+-type region, the third region is an n-type region and the fourth region is a p-type region.
A semiconductor structure, in accordance with another embodiment of the present invention, includes, in part, a number of semiconductor regions, at least a pair of dielectric regions and a pair of terminals. The first and second regions of the semiconductor structure are respectively coupled to the first and second terminals. The third and fourth regions are disposed between and adjacent the first and second regions. The dielectric regions extend into the third region. The fourth region extends into the third region, has a conductivity type opposite a conductivity type of the third region, and surrounds a portion of the at least first and second dielectric regions. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the semiconductor structure. The electrical characteristic of the semiconductor structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The interface region between the dielectric regions and the fourth region includes intentionally induced charges.
In one embodiment, the dielectric regions extend into the first and second regions. In one embodiment, the integrated density of doping impurities in the third region along a line parallel to a surface of the dielectric regions ranges from about 1×1012/cm2 to about 5×1012/cm2. In one embodiment, each dielectric region further includes a second material. In one embodiment, the second material in each dielectric region includes, in part, aluminum fluoride. In one embodiment, each dielectric region further includes, in part, a third material that is a dielectric material. In one embodiment, the second and third materials in each dielectric region are the same material.
In one embodiment, the first and second regions are respectively p+ type and n+ type regions, and the first and second terminals are respectively anode and cathode terminals. In one embodiment, the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and said first region is formed above the third region. In one embodiment, the dielectric regions are isolated from one another.
In one embodiment, the semiconductor structure further includes, in part, a fourth region disposed between the second and the third regions. The second and fourth regions are of the same conductivity type.
In one embodiment, the first and second regions are respectively n+ type and p+ type regions, and the first and second terminals are respectively cathode and anode terminals. In one embodiment, the third region is a p-type region. In one embodiment, the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and the first region is formed above the third region. In one embodiment, the third region is formed above the second region and the first region is formed above the third region. In one embodiment, each of the dielectric region is tapered so as to have a larger width near one end of the dielectric region than another end of the dielectric region.
In one embodiment, the first, second and third regions are formed along the same surface of a semiconductor substrate in which the semiconductor structure is formed. In one such embodiment, the semiconductor structure includes a fourth region in which the second region is formed. In one such embodiment, the third region is adjacent the first and fourth regions. In one such embodiment, the first region is a p+ type region, the second region is an n+ type region, the third region is a p-type region and the fourth region is an n-type region. In another such embodiment, the first region is a p+-type region, the second region is an n+-type region, the third region is an n-type region and the fourth region is a p-type region.
A semiconductor structure, in accordance with one exemplary embodiment of the present invention, is characterized, in part, by a relatively high breakdown voltage VB. The semiconductor structure includes dielectric layers that have intentionally introduced charge (Qf). By alternating dielectric and silicon layers that are charge balanced, the structure sustains a higher breakdown voltage for a given voltage sustaining region doping concentration and/or thickness than conventional devices. In some embodiments, the silicon layers disposed between the dielectric layers are formed using epitaxial growth, implantation or lightly doped epitaxial growth followed by implantation, or the like. The device performance provided by embodiments of the present invention exceeds the one dimensional silicon breakdown voltage limit for the same doping and thickness of the epitaxial layer or voltage sustaining layer.
In the following description, fixed charge(s) refers to the charge intentionally introduced using processes such as ion implantation, diffusion, deposition and the like in addition to the charge that results as a by-product of fabrication processes. Furthermore, while reference is made below generally with respect to interfacial charges, i.e., charges in the interface region between the dielectric and the semiconductor region, it is understood that such charges may also be present both in the dielectric as well as in the semiconductor region in which the dielectric regions are formed.
At reverse bias, dielectric layer's charge is balanced by charges in the depletion region. At zero bias, the dielectric layer's charge is balanced, in part, by the charges present in an inversion layer that forms at the semiconductor-dielectric layer interface. The charge in the dielectric layer, in one embodiment, is located at or close to the semiconductor-dielectric interface for maximum effectiveness. In one embodiment, the charge is immobile at typical device operating temperatures. Both negative or positive charges can be used to provide the required charge to balance the depletion charge of the ionized impurities of the semiconductor layer. This results in a more uniform electric field along the voltage sustaining region and therefore a higher breakdown voltage.
The present invention provides a number of advantages over conventional semiconductor structures that depend primarily on the permittivity and width of a dielectric layer adjacent the semiconductor region. In accordance with the present invention, the fixed charge provided for charge balance is not a function of the trench width. Therefore, to achieve a higher breakdown voltage, the width of the dielectric layer is only limited by the steps needed to introduce the fixed charge and refill the trench, which enables smaller cell pitches than that which can be obtained by conventional SJ or non-SJ type structures. Furthermore, by implementing charge balance by using charges in dielectric layers and not p-n junctions or field plates, lower capacitances are achieved. The structures of the present invention as described herein are easier and more cost effective to fabricate.
Both negative or positive charges may be used to provide the required charge balance. The charge balance achieved using charges in dielectric layers, in accordance with the present invention, provides lower capacitance values than other charge balance techniques. A structure, in accordance with the present invention, is easier and more cost effective to fabricate.
In some embodiments, negative charges near the semiconductor-dielectric interface of trenches balance the positive depletion charges in the n-type semiconductor layers to sustain higher voltages. The negative dielectric charges may be generated using compound insulating layer, for example, silicon dioxide and aluminum fluoride (AlF3 or AlFx) or by implanting ions such as iodine, bromine, chlorine, chromium, aluminum, or other suitable ions. The negative charge generation effect using a compound insulating layer of silicon dioxide and aluminum fluoride (AlF3 or AlFx) has been experimentally verified where the negative interface charge was found to be a strong function of the fraction x. In yet other embodiments, positive charges near the semiconductor-dielectric interface of trenches balance the negative depletion charges in p-type semiconductor layers to sustain higher voltages. The positive charges may be generated, for example, by implanting positive ions such as cesium or potassium into the dielectric layer that is formed along the walls and the bottom of trenches. Alternatively, another dielectric layer that contains positive charges, such as silicon-nitride or silicon-oxynitride, is deposited on the dielectric layer that is formed along the walls and the bottom of trenches. Another approach of generating positive or negative charges in dielectric layers, for example oxide, is diffusion of impurities into the oxide using techniques such as vapor deposition of impurities on the oxide layer followed by a drive-in or annealing step.
In one embodiment, each trench 206 includes one or more dielectric layers 210. In accordance with the present invention, the interface region disposed between each dielectric filled trench 206 and p-region 204 includes positive charges. It is understood that the positive charges may reside inside trenches 206, in a transition region (not shown) between the trench and p-type region 204, in the P-region 204, or a combination thereof. In accordance with the present invention, the positive interface charges present across the opposing surfaces 2121 and 2122 of trenches 2061 2062 are sufficient to cause p region 2042 disposed between these two trenches to partially or fully deplete under reverse bias. The partial or full depletion of p-region 2042 causes the electric field along line xx′ shown in
At reverse bias, the positive charges are balanced by the charges in the depleted semiconductor voltage sustaining region. As described above, the positive charges are, in one embodiment, immobile at typical device operating temperatures. A semiconductor structure, in accordance with the present invention achieves cell pitches that are smaller and with thinner voltage sustaining layer than many conventional SJ structures. Furthermore, by using charges in dielectric layers in contrast to conventional p-n junctions lower capacitances are achieved and less charge stored under reverse recovery conditions. The structures of the present invention are also easier and more cost effective to fabricate.
Referring to
In accordance with some embodiments of the present invention, the trenches include materials that include negative charges adapted to deplete the N regions in which the trenches are partly formed.
In the exemplary embodiment shown in
In one embodiment, n-type region 1004 is an epitaxial layer grown over a heavily doped n+substrate 202. In one embodiment, the n-type epitaxial layer 1004 is uniformly doped. In another embodiment, the n-type epitaxial layer 1004 is non-uniformly doped. For example, the doping profile can be graded to have higher doping at the substrate relative to the surface or vice versa.
In the embodiment illustrated in
In device 1100, each trench 1006 includes a first layer 1020 that is a dielectric layer, a second layer 1022, and a third layer 1024 that is a dielectric layer. First layer 1020 is formed on the walls and bottom of the trenches. Second layer 1022—which may include more than one material—is formed so as to be enclosed within the first layer 1020. Third layer 1024 is formed so as to be enclosed within second layer 1022. In one embodiment, third layer 1024 is formed from the same material as the first layer 1020. In another embodiment, the first and second dielectric layers are formed using different materials. Disposing layer 1022 which may include, for example, aluminum fluoride, between the two dielectric layers 1020 and 1024 provides negative charges at the interfaces between the dielectric layers 1020, 1024 and layer 1022. The various n+, p+, n and p-type layers of device 1100 are formed using conventional fabrication processes such as implantation, diffusion, annealing, and the like.
In one embodiment, each trench 206 includes one or more dielectric layers 210. In accordance with the present invention, positive charges are intentionally introduced into trenches 206. Such charges may reside in the trenches, in a transition region between the trench and p-type region 204, in the P-region 204, or a combination thereof, and are collectively and alternatively referred to herein as interface charges. Such positive interface charges present across the opposing surfaces of the trenches is sufficient to cause the p region 204 disposed between such two trenches to partially or fully deplete at a reverse bias. For example, the charges present near opposing surfaces 2121 and 2122 of trenches 2061, 2062 are sufficient to cause p-type region 2042 disposed between these two trenches to partially or fully deplete at a reverse bias. Similarly, the charges present near opposing surfaces 2123 and 2124 of trenches 2062, 2063 are sufficient to cause p-type region 204 disposed between these two trenches to partially or fully deplete at a reverse bias. The partial or full depletion of p-type regions 204 at a reverse bias causes the electric field along, for example, a plane perpendicular to line AA′ positioned at the midpoint of opposing surfaces 2121 and 2122 to remain relatively uniform under an externally applied reverse bias between the cathode and anode terminals. At a reverse bias, the positive interface charges are balanced by the charges in the depleted charge of the P-type regions 204. As described above, the positive charges are, in one embodiment, immobile at typical device operating temperatures.
In device 1300 and as described above, each trench 1006 includes a first layer 1020 that is a dielectric layer, a second layer 1022, and a third layer 1024 that is a dielectric layer. First layer 1020 is formed on the walls and bottom of the trenches. Second layer 1022—which may include more than one material—is formed so as to be enclosed within the first layer 1020. Third layer 1024 is formed so as to be enclosed within second layer 1022. In one embodiment, third layer 1024 is formed from the same material as the first layer 1020. In another embodiment, the first and second dielectric layers are formed using different materials. Disposing layer 1022 which may include, for example, aluminum fluoride, between the two dielectric layers 1020 and 1024 provides negative charges at the interfaces between the dielectric layers 1020, 1024 and layer 1022. The various layers of device 1300 are formed using conventional fabrication processes such as implantation, diffusion, annealing, and the like.
The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the type of device or integrated circuit in which the present disclosure may be disposed. Nor is the disclosure limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
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