A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal.
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14. A semiconductor device, comprising:
a periodic signal generation circuit configured to generate first and second periodic signal which comprise information about a change in a refresh period depending on a change in internal temperature of the semiconductor device; and
a flag signal generation circuit configured to generate a pre-flag signal which is enabled when at least one of a level of the first periodic signal and a level of the second periodic signal changes, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal comprising the information about the change in the internal temperature.
1. A flag signal generation circuit in a semiconductor device comprising:
a first periodic signal detection unit configured to detect a change in a level of a first periodic signal and generate a first detection signal indicative of a internal temperature change in the semiconductor device;
a second periodic signal detection unit configured to detect a change in a level of a second periodic signal and generate a second detection signal also indicative of an internal temperature change in the semiconductor device; and
a flag signal output unit configured to generate a pre-flag signal based on the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal.
2. The flag signal generation circuit of
3. The flag signal generation circuit of
4. The flag signal generation circuit of
5. The flag signal generation circuit of
6. The flag signal generation circuit of
a first latch section configured to latch the first periodic signal;
a buffer section configured to buffer an output signal of the first latch section in response to the mode register read signal; and
a logic section configured to compare the first periodic signal with an output signal of the buffer section, and generate the first detection signal.
7. The flag signal generation circuit of
a second latch section configured to latch the output signal of the buffer section; and
a buffer section configured to buffer and output the first periodic signal in response to the mode register read signal.
8. The flag signal generation circuit of
9. The flag signal generation circuit of
a first latch section configured to latch the second periodic signal;
a first buffer section configured to buffer an output signal of the first latch unit in response to the mode register read signal; and
a logic section configured to compare the second periodic signal with an output signal of the buffer section, and generate the second detection signal.
10. The flag signal generation circuit of
a second latch section configured to latch the output signal of the first buffer section; and
a second buffer section configured to buffer and output the second periodic signal in response to the mode register read signal.
11. The flag signal generation circuit of
a logic section configured to receive the first and second detection signals and generate the pre-flag signal; and
a buffer section configured to buffer the pre-flag signal and output the buffered pre-flag signal as the flag signal in response to the mode register read signal.
12. The flag signal generation circuit of
13. The flag signal generation circuit of
a reset section configured to reset an output node of the logic section in response to a power-up signal; and
a latch section configured to latch a signal of the output node of the logic section.
15. The semiconductor device of
16. The semiconductor device of
a first periodic signal detection unit configured to detect a change in a level of the first periodic signal and generate a first detection signal;
a second periodic signal detection unit configured to detect a change in a level of the second periodic signal and generate a second detection signal; and
a flag signal output unit configured to generate a pre-flag signal based on the first and second detection signals, buffer the pre-flag signal in response to the mode register read signal, and output the buffered pre-flag signal as the flag signal.
17. The semiconductor device of
18. The semiconductor device of
a first latch section configured to latch the first periodic signal;
a buffer section configured to buffer an output signal of the first latch unit in response to the mode register read signal; and
a logic section configured to compare the first periodic signal with an output signal of the buffer and generate the first detection signal.
19. The semiconductor device of
a second latch section configured to latch the output signal of the buffer; and
a buffer section configured to buffer and output the first periodic signal in response to the mode register read signal.
20. The semiconductor device of
21. The semiconductor device of
a first latch section configured to latch the second periodic signal;
a first buffer section configured to buffer an output signal of the first latch unit in response to the mode register read signal; and
a logic section configured to compare the second periodic signal with an output signal of the buffer and generate the second detection signal.
22. The semiconductor device of
a second latch section configured to latch the output signal of the first buffer section; and
a second buffer section configured to buffer and output the second periodic signal in response to the mode register read signal.
23. The semiconductor device of
a logic section configured to receive the first and second detection signals and generate the pre-flag signal; and
a buffer section configured to buffer the pre-flag signal and output the buffered flag signal in response to the mode register read signal, wherein the buffered flag signal is outputted as the flag signal to an output pad.
24. The semiconductor device of
25. The semiconductor device of
a reset section configured to reset an output node of the logic section in response to a power-up signal; and
a latch section configured to latch a signal of the output node of the logic section.
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The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2009-0080737, filed on Aug. 28, 2009, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety set forth in full.
In general, a register set is used to define the operation modes of a semiconductor device, and it is provided with a mode register set (MRS) and an extended mode register set (EMRS). The MRS and the EMRS set the operation modes of a semiconductor device based on the values applied to the address pins with a mode register set command. Information about the set operation modes is substantially maintained until a semiconductor device is reprogrammed or its power is interrupted. The MRS is necessary for synchronous dynamic random access memories (SDRAM) or static random access memories (SRAM). Before a semiconductor device is in use, the MRS sets the operation modes of the semiconductor device such as burst length (BL), column address strobe (CAS), signal latency (CL), and read latency (RL).
Meanwhile, the semiconductor devices used in mobile devices, such as portable computers, PDAs, hand-held phones, and so on (hereinafter, referred to as “mobile memory chips”) are required to reduce power consumption to improve the portability of the mobile devices having such mobile memory chips therein. The mobile memory chips are also required to improve the data transfer rate to increase the operating speeds of mobile devices having such memory chips therein. To meet these demands, a low power DDR2 (LPDDR2) technology was developed to dramatically improve both the power consumption and the data transfer rate. The LPDDR2 technology can implement the data transfer rate of 800 Mbps, which is currently the highest in the industry, at an operating voltage of 1.2 V. Furthermore, since an ultra-fine 66-nano process is applied to the LPDDR2 technology, a mobile memory chip can be packaged to a size of 9 mm×12 mm.
According to the LPDDR2 technology specification, the specification defines an MRS to set a signal for the information on the internal temperature change of a semiconductor device and to store the information in a register.
An embodiment of the present invention relates to a flag signal generation circuit capable of extracting a flag signal, which includes information about a change in the internal temperature of a semiconductor device, from information about a self-refresh period differently set depending on the change in the internal temperature, and a semiconductor device including the same.
In one embodiment, a flag signal generation circuit includes: a first periodic signal detection unit configured to detect a change in a level of a first periodic signal and generate a first detection signal; a second periodic signal detection unit configured to detect a change in a level of a second periodic signal and generate a second detection signal; and a flag signal output unit configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal.
In another embodiment, a semiconductor device includes: a periodic signal generation circuit configured to generate a periodic signal which comprises information about a change in a refresh period depending on a change in internal temperature; and a flag signal generation circuit configured to extract a flag signal, which comprises the information about the change in the internal temperature, from the periodic signal in response to a mode register read signal, and output the extracted flag signal to an output pad.
The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.
As shown in
The periodic signal generation circuit 1 may be implemented with, for example, a temperature-compensated self-refresh (TCSR) circuit. A TCSR circuit generally includes a temperature sensor and the circuits such as a counter, and such a TCSR circuit controls the refresh period adjusting it based on the internal temperature of the semiconductor device. For example, the data retention characteristics of memory cells depend on the internal temperature of the semiconductor device. Therefore, as the internal temperature rises, the self-refresh operations may need to be executed in shorter intervals (that is, more frequently) to prevent data loss. On the other hand, when the internal temperature is low, data could be retained even if the self-refresh operations are performed in longer intervals (i.e., less frequently). In an embodiment of the present invention, the periodic signal generation circuit 1 generates the first to third periodic signals OP<1:3>, and the levels of which are counted and controlled depending on the internal temperature of the semiconductor device. For example, the periodic signal generation circuit 1 down-counts the first to third periodic signals OP<1:3> in order to reduce the refresh period when the internal temperature rises, and up-counts the first to third periodic signals OP<1:3> in order to increase the refresh period when the internal temperature drops. The counting of the first to third periodic signals OP<1:3> can be variously set according to embodiments of the present invention.
As illustrated in
As illustrated in
The first buffer section 210 includes PMOS transistors P21 and P22 coupled between a power supply voltage (VDD) terminal and a node nd25, and NMOS transistors N21 and N22 coupled between the node nd25 and the ground voltage (VSS) terminal and configured to buffer the first periodic signal OP<1> and output a first output periodic signal OP<1>_OUT in response to a mode register read signal MRR. The mode register read signal MRR is a signal which, when enabled to a low level, causes the output of the first to third periodic signals OP<1:3> or is an operation mode set by an MRS and stored in the registers.
The first periodic signal detection unit 20 configured as above outputs the first detection signal DET1 which is enabled to a high level when a self-refresh period changes due to a change in the internal temperature of the semiconductor device or, in other words, due to a change in the level of the first periodic signal OP<1>. In addition, the first periodic signal detection unit 20 buffers the first periodic signal OP<1> and outputs the first output periodic signal OP<1>_OUT in response to the mode register read signal MRR.
The second periodic signal detection unit 21 and the third periodic signal detection unit 22 would have the same configurations of the first periodic signal detection unit 20 as discussed above, except that the second periodic signal detection unit 21 would receive the second periodic signal OP<2> and output a second output periodic signal OP<2>_OUT and the second detection signal DET2. Similarly, the third periodic signal detection unit 22 would receive the third periodic signal OP<3> and output a third output periodic signal OP<3>_OUT and the third detection signal DET3. Accordingly, the detailed descriptions of the configuration and operation of the second periodic signal detection unit 21 and the third periodic signal detection unit 22 are not repeated herein as the repeated discussions are not considered as necessary to understand.
As illustrated in
The flag signal output unit 23 configured as above buffers the pre-flag signal PRE_TUF, which is enabled to a high level when at least one of the first to third detection signals DET1, DET2, DET3 is enabled to a high level, in response to the mode register read signal MRR, and generates the flag signal TUFB which is enabled to a low level.
Hereinafter, the operations of the semiconductor device configured as above will be described with reference to
First, when the internal temperature of the semiconductor device changes, the level of at least one of the first to third periodic signals OP<1:3> generated by the periodic signal generation circuit 1 also changes.
Next, when the level of at least one of the first to third periodic signals OP<1:3> changes, the flag signal generation circuit 2 generates the flag signal TUFB which is enabled to a low level. More specifically, the following description will be made about the case in which the level of the first periodic signal OP<1> among the first to third periodic signals OP<1:3> changes depending on a change in the internal temperature of the semiconductor device.
When the level of the first periodic signal OP<1> changes, the levels of the nodes nd20 and nd22 which are detected by the first periodic signal detection unit 20 of
As described above, the semiconductor device according to an embodiment of the present invention extracts the flag signal including information about a change in the internal temperature from a change in the levels of the first to third periodic signals OP<1:3> related to the information about a change in the refresh period due to changes in the internal temperature of the semiconductor device.
The embodiments of the present invention have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jul 27 2010 | Hynix Semiconductor Inc. | (assignment on the face of the patent) | / |
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