A printed circuit board (200) includes at least one via (280) defined therein, the via has an upper cap (220) formed on a top surface of the PCB, and a lower cap (240) formed on a bottom surface of the PCB. A conductive hole (290) is defined in the PCB having a plated sidewall (230) plated on its inner surface, and a first clearance hole (271) is defined in a first inner layer (260) of the PCB around the sidewall. A first transmission line (210) defined on the top surface of the PCB is coupled to the upper cap, a first void (273) extending from a boundary of the first clearance hole being disposed along the layout direction of the first transmission line.
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1. A printed circuit board (PCB) comprising:
a via with a conductive hole defined in the PCB, the conductive hole having a plated sidewall;
a top layer with a first transmission line coupled to an upper cap of the via;
a bottom layer;
a first inner layer defined between the top layer and the bottom layer; and
a first clearance hole defined in the first inner layer around the sidewall, a first extended void extending from the first clearance hole and defined in a layout direction and right under the first transmission line,
wherein the first clearance hole is circular shaped, the first clearance hole has a diameter greater than that of the upper cap, and the first extended void has a width greater than that of the first transmission line.
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1. Field of the Invention
The present invention relates to printed circuit boards, and particularly to the structure of a via of a printed circuit board.
2. Description of Related Art
As well known to those skilled in the art, a conventional printed circuit board (PCB) functions to connect various electronic components to each other on the PCB along a predetermined pattern, and is applied to various electronic goods such as home appliances including digital televisions and advanced telecommunication equipment. A conventional PCB comprises a copper plate on which a circuit pattern is formed, and at least an inner layer.
The capacitance of the via 180 which depends on the area of the clearance holes 170 is one of the most important parameters for PCB designers, because the capacitance of the via 180 may reduce the quality of a signal transmitted through the via 180.
What is needed, therefore, is a printed circuit board which can solve the above problem.
An exemplary printed circuit board includes at least one via defined therein, the via has an upper cap formed on a top surface of the PCB, and a lower cap formed on a bottom surface of the PCB. A conductive hole is defined in the PCB having a plated sidewall, and a first clearance hole is defined in a first inner layer of the PCB around the sidewall. A first transmission line defined on the top surface of the PCB is coupled to the upper cap, a first void extending from a boundary of the first clearance hole being disposed along the layout direction of the first transmission line.
Other objects, advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiments when taken in conjunction with the accompanying drawings, in which:
Referring to
The conductive hole 290 has a plated sidewall 230. A first transmission line 210 disposed on the exposed surface of the top layer of the PCB 200 is coupled to the upper cap 220, and a second transmission line 250 disposed on the bottom surface of the bottom layer of the PCB 200 is coupled to the lower cap 240. The first and second transmission lines 210, 250 communicate with each other through the via 280. The first clearance hole 271 is formed around the sidewall 230 in the inner layer 260 adjacent the top layer. The second clearance hole 272 is formed around the sidewall 230 in the inner layer 260 adjacent the bottom layer. The first clearance hole 271 has a first void 273 defined along the layout direction of the first transmission line 210, and the second clearance hole 272 has a second void 274 defined along the layout direction of the second transmission line 250. The other inner layers 260 also have clearance holes 275.
In this embodiment, the clearance holes 271, 272 are circular shaped, and the diameter of the clearance holes 271, 272 is greater than the diameter of the caps 220, 240. The first void 273 and the second void 274 are rectangular shaped or oval shaped. The first void 273 is defined at a side of the first clearance hole 271 right under the first transmission line 210, the second void 274 is defined at a side of the second clearance hole 272 right above the second transmission line 250. The first void 273 and the second void 274 increases the area of the clearance holes 271, 275, so that the capacitance of the via 280 is reduced and the impedance of the via 280 is increased. In this embodiment, the via 280 is a through hole, the via 280 can also be a blind via or a buried via.
The foregoing description of the exemplary embodiment of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to explain the principles of the invention and its practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description and the exemplary embodiment described therein.
Liu, Chien-Hung, Hsu, Shou-Kuo, Pai, Yu-Chang
Patent | Priority | Assignee | Title |
9860985, | Dec 17 2012 | Lockheed Martin Corporation | System and method for improving isolation in high-density laminated printed circuit boards |
Patent | Priority | Assignee | Title |
6329603, | Apr 07 1999 | GLOBALFOUNDRIES Inc | Low CTE power and ground planes |
6388206, | Oct 29 1998 | Agilent Technologies Inc | Microcircuit shielded, controlled impedance "Gatling gun"via |
6767252, | Oct 10 2001 | Molex Incorporated | High speed differential signal edge card connector and circuit board layouts therefor |
6787710, | May 29 2001 | Mitsubishi Denki Kabushiki Kaisha | Wiring board and a method for manufacturing the wiring board |
7317166, | May 10 2004 | Fujitsu Limited | Wiring base board, method of producing thereof, and electronic device |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Oct 25 2007 | PAI, YU-CHANG | HON HAI PRECISION INDUSTRY CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020032 | /0538 | |
Oct 25 2007 | HSU, SHOU-KUO | HON HAI PRECISION INDUSTRY CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020032 | /0538 | |
Oct 25 2007 | LIU, CHIEN-HUNG | HON HAI PRECISION INDUSTRY CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020032 | /0538 | |
Oct 30 2007 | Hon Hai Precision Industry Co., Ltd. | (assignment on the face of the patent) | / |
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