A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Patent
   8071451
Priority
Jul 29 2009
Filed
Jul 29 2009
Issued
Dec 06 2011
Expiry
Oct 09 2029
Extension
72 days
Assg.orig
Entity
Large
427
14
EXPIRED<2yrs
1. A method of doping a semiconductor body, comprising:
exposing the semiconductor body to an activated hydrogen gas for a predetermined time, wherein the activated hydrogen gas reacts with one or more surfaces of the semiconductor body to form a reactive layer comprised within the one or more surfaces, and wherein the semiconductor body comprises a silicon, germanium, or silicon-germanium substrate, wherein the reactive layer comprises dangling bonds comprising one or more of: dangling silicon bonds, silicon hydrogen (Si—H) bonds, silanol (Si—OH) bonds, germanium hydrogen (Ge—H) bonds, and germanol (Ge—OH) bonds;
exposing the semiconductor body to an ultraviolet illumination source or a plasma after exposing the semiconductor body to the activated hydrogen gas, wherein the ultraviolet illumination source or the plasma are configured to change a density of one or more of Si—H, Si—OH, Ge—H, and Ge—OH bonds; and
exposing the semiconductor body to a reactant comprising an n-type or p-type dopant species, wherein the reactant is configured to chemically react with the dangling bonds within the reactive layer to form a doped layer.
10. A method of forming a multi-gate semiconductor device, comprising:
selectively masking a silicon, germanium or silicon-germanium substrate to expose a doping region of the multi-gate semiconductor device;
exposing the exposed doping region of the substrate to an activated hydrogen gas for a predetermined time, wherein the activated hydrogen gas reacts with one or more surfaces of the substrate to form a reactive layer comprising dangling silicon bonds, dangling germanium bonds, silicon hydrogen (Si—H) bonds, silanol (Si—OH) bonds, germanium hydrogen (Ge—H) bonds, or germanol (Ge—OH) bonds, the reactive layer comprised within the one or more surfaces;
exposing the substrate to an ultraviolet illumination source or a plasma after exposing the substrate to the activated hydrogen gas, wherein the ultraviolet illumination source or the plasma are configured to change a density of Si—H, Si—OH, Ge—H or Ge—OH bonds;
exposing the exposed doping region of the substrate to a reactant, wherein the reactant is configured to chemically react with the reactive layer to form a doped layer comprising one or more elements of the reactant;
forming a gate layer extending above the one or more surfaces of the substrate; and
forming a gate oxide layer configured between the gate layer and the reactive layer.
2. The method of claim 1, wherein the doped layer comprises a doping concentration that is substantially independent of a physical orientation of the one or more surfaces.
3. The method of claim 1, wherein a thickness of the doped layer is a function of a concentration of the activated hydrogen gas, a species of the activated hydrogen gas, a temperature of the activated hydrogen gas, a substrate temperature, or the predetermined time.
4. The method of claim 1, further comprising:
depositing a masking layer onto the one or more surfaces of the semiconductor body;
selectively patterning the deposited masking layer to define a region for formation of the doped layer prior to exposing the semiconductor body to the activated hydrogen gas and the reactant; and
removing the masking layer from the one or more surfaces of the semiconductor body after exposing the region to the reactant.
5. The method of claim 1, further comprising performing an anneal to activate the n-type or p-type dopant species in the doped layer.
6. The method of claim 1, the activated hydrogen gas comprising an additive gas configured to control hydrogen etching or active site formation, wherein the additive gas comprises one or more of: Nitrogen gas (n2), Nitrous oxide (n2O), Ammonia (NH3), Helium (He), Neon (Ne), Argon (Ar), Carbon Dioxide (CO2), Carbon Monoxide (CO), Nitrous oxide (n2O), or Oxygen gas (O2).
7. The method of claim 1, wherein the reactant is introduced as a gas phase comprising one of: B2H6, BF3, BCl3, PH3, AsCl3, AsF3, AsF5, P2F4, PH4Cl, PCl2F, PClF2, PF3, PCl3, As(OC2H5)3, or AsH3.
8. The method of claim 1, wherein the reactant is introduced as a liquid phase comprising one of: H3BO3, H3PO4, POCL, AsCl3, AsF3, or H3AsO4.
9. A method of claim 1, wherein the activated hydrogen gas is formed by a plasma reaction of a hydrogen containing gas comprising one of more of: H2, NH3, CH4, C2H6, H2S, HF, HCl, n2H4, HBr.
11. The method of claim 10, further comprising performing an anneal to activate the reactant comprised within the doped layer.
12. The method of claim 10, comprising including an additive gas to the activated hydrogen gas to control hydrogen etching or active site formation.
13. The method of claim 10, wherein the substrate comprises a three-dimensional substrate comprising respective surfaces having normal vectors that are configured to have substantially different angles, and wherein the doped layer is formed to provide a substantially uniform concentration profile within the one or more surfaces that is substantially independent of an angle of respective normal vectors.

The present invention relates generally to semiconductor doping, and more specifically to methods for providing a conformal doping to one or more surfaces of a semiconductor body that is substantially independent of physical orientation of the surfaces.

Modern day semiconductor devices are typically formed by changing the electrical characteristics of a semiconductor material (e.g., a silicon substrate) through implanting dopants into the bulk of the material. By changing the type and/or concentration of implanted dopants (e.g., n-type dopants, p-type dopants) the current conduction characteristics of a device can be changed. Current conduction occurs by forming free charge carriers (e.g., electrons, holes) in the bulk of the semiconductor material. Through doping the material with impurity dopant atoms (e.g., phosphorus or boron) the number of free charge carriers can be greatly increased resulting in different current conduction characteristics. Semiconductors containing an excess of holes are called p-type devices and semiconductors containing an excess of electrons are called n-type devices.

For example, the simplest semiconductor device is a p-n junction diode comprising a semiconductor surface having two regions, with different dopant types, abutted together (e.g., a p-type material in contact with an n-type material) at a junction. When an electric potential is applied across the junction of the device (i.e., an electric field is present in the bulk of the device) charge carriers (e.g., electrons) freely flow from one region (e.g., the n-type region) to the other region (e.g., the p-type region), where they recombine with opposite charge carriers (e.g., holes) and form a depletion region in the vicinity of the junction.

More complex device topologies, having more sophisticated geometries, may also be formed based upon the basic idea of semiconductor doping. These more complex devices may be formed to provide devices that meet the needs of the modern computing industry.

The present invention is directed to a method of conformal doping which can provide a doped layer having a thickness and doping concentration that are substantially independent of the physical orientation of an underlying surface (e.g., that can provide the same doping level at the top of a structure as on the sidewalls). In one particular embodiment, a semiconductor body (e.g., a silicon wafer) is exposed to an activated hydrogen gas (H2 gas) for a predetermined time period and temperature. The activated hydrogen gas will react with the surface of the semiconducting body, breaking bonds in the substrate (e.g., silicon-silicon bonds), and forming a reactive layer comprising weakened and/or dangling bonds (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds, and/or dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, result in reactive sites that extend into the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant, metal hydride, metal-organic, etc.) may then be introduced (e.g., as a gas phase or as a liquid phase) to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer. Therefore, a doped layer is formed within a semiconductor body that may be substantially independent of the physical orientation of respective surfaces of the semiconductor body.

To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

FIG. 1 illustrates a flow diagram of a method for providing a conformal doping to one or more surfaces of a semiconductor body that is substantially independent of the physical orientation of the surfaces;

FIG. 2 illustrates a flow diagram of a method for providing a conformal doping to one or more surfaces of a semiconductor body that is substantially independent of the physical orientation of the surfaces;

FIG. 3 illustrates a flow diagram of a more detailed method for providing a conformal doping to one or more surfaces of a semiconductor body that is substantially independent of the physical orientation of the surfaces;

FIGS. 4-6 illustrate cross-sectional views of a semiconductor body according to the method of FIG. 3, wherein an exemplary conformal doping of one or more surfaces of the semiconductor body is performed substantially independent of the physical orientation of the surfaces;

FIG. 7 illustrates a graph showing hydrogen concentration in a semiconductor body as a function of distance from the surface;

FIG. 8 illustrates a graph showing the depth of the doped layer as a function of the activated hydrogen concentration;

FIG. 9 illustrates a graph showing the effect of introducing a gas additive to an activated hydrogen gas to reduce hydrogen etching of a silicon substrate;

FIGS. 10-12 illustrate cross-sectional views of a semiconductor body according to the method of FIG. 3, wherein an exemplary conformal doping of one or more surfaces of the semiconductor body is performed substantially independent of the physical orientation of the surfaces;

FIG. 13 illustrates a flow diagram of a method for providing a conformal doping to one or more surfaces of a multi-gate semiconductor device that is substantially independent of the physical orientation of the surfaces;

FIG. 14-16 illustrates a top view of a gate-all-around semiconductor device according to the method of FIG. 13, comprising a doped silicon layer extending over all surfaces of the device's conducting silicon channel; and

FIG. 17 illustrates a tri-gate semiconductor device comprising a doped silicon layer extending over three surfaces of the device's conducting silicon channel.

The present invention will now be described with reference to the drawings wherein like reference numerals are used to refer to like elements throughout.

Performance enhancement of metal-oxide-semiconductor field-effect transistors (MOSFET) devices have traditionally been driven by scaling the physical size of the devices. However, since physical limitations have began to increase the difficulty of traditional scaling of semiconductor circuits, three dimensional devices are emerging as viable alternatives to the commonly used two dimensional devices to optimize surface area and extend device scaling to emerging technology nodes. In particular, three dimensional, multi-gate devices (e.g., tri-gate devices, gate-all-around devices, etc.) are being developed for implementation in the 32 nm technology node, the 22 nm technology node, etc.

Presently in the manufacture of semiconductor devices, ion implantation is the most utilized method to dope semiconductor workpieces (e.g., silicon wafers) with impurities. For example, ion implanters or ion implantation systems may treat a workpiece with an ion beam, to produce n-type or p-type doped regions or to form passivation layers on the workpiece. When used for doping semiconductors, an ion implantation system will usually operate by accelerating dopant species ions provided by an ion source, to a high energy (e.g., between 0.5 to 500 keV). The high energy beam of dopant ions is collided into the surface of a semiconducting substrate resulting in implantation of the energized ions that provides a doped substrate.

Due to the high energy of accelerated ions, dopants implanted by ion implantation are limited to a substantially line-of-sight direction. Therefore, implantation in multiple directions (e.g., of multiple, substantially perpendicular surfaces) can be performed by providing an initial dopant either through implantation or through deposition from a gaseous source, followed by a high temperature thermal diffusion of the dopants. However, such methods result in a number of setbacks including limited dopant concentration (e.g., limited by the concentration of solid solubility), mask thermal stability, and limited control of the dopant concentration. Therefore, to achieve widespread fabrication of high quality multi-gate devices methods of conformal doping of three dimensional devices will have to be improved.

Accordingly, a method of doping a semiconductor body is provided herein. FIG. 1 illustrates a flow diagram of a method 100 for doping of a semiconductor body as provided herein. The method 100 is performed by forming a reactive layer at 102. The reactive layer is configured within about 30 nm of the semiconductor body surface and comprises chemically reactive sites (e.g., dangling bonds). At 104, the reactive layer may be exposed to a reactive element (e.g., dopants) configured to chemically react with (e.g., attach to) reactive sites of the reactive layer, thereby forming a doped semiconductor layer comprising the reactive element.

In a more detailed embodiment, a semiconductor body (e.g., a silicon wafer, a germanium substrate, a silicon-germanium substrate) is exposed to an activated hydrogen gas (H2 gas) for a predetermined time period. The activated hydrogen gas will react with the surface of the semiconducting body, breaking bonds in the substrate (e.g., silicon-silicon bonds, germanium-germanium bonds), and forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds, germanium-hydrogen bonds (Ge—H), germanol bonds (Ge—OH), etc.) and/or dangling bonds (e.g., dangling silicon or germanium bonds). The concentration of the weakened or dangling bonds and the depth to which the bonds penetrate into the surface of the semiconductor body is a function of activated hydrogen concentration, substrate temperature, and the exposure time. The dangling bonds, in addition to the easily broken weakened bonds, result in reactive sites that extend into the semiconductor body. A reactant (e.g., n-type dopant, or p-type dopant, metal hydride, metal-organic, etc.) may then be introduced (e.g., as a gas phase or as a liquid phase) to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer.

In one embodiment, the method provided herein may comprise forming a conformal doped layer comprising a thickness and doping concentration that are substantially independent of the physical orientation of an underlying surface (e.g., that provides the same doping level at the top of a structure as on the sidewalls).

It will be appreciated that the term “conformal doping” is defined herein as a doping, alloying, or other materials modification of a planar and non-planar surface in a way that is substantially independent of the angle of the surface normal and provides the planar and non-planar features with a surface normal angle independent concentration profile (e.g., uniform thickness, etc.) over both the planar and non-planar features. Furthermore, it will be appreciated that the terms “dopant” and “doping layer” may refer to a wide range of doping elements including but not limited to n-type dopants (e.g., boron), p-type dopants (e.g., phosphorus, arsenic), metals (e.g. tungsten, tantalum, titanium, nickel, ruthenium), carbon, etc.

FIG. 2 illustrates a first exemplary embodiment of a method 200 of doping which can provide a doped layer that extends along one or more surfaces of a semiconductor body. In one embodiment, the doped layer comprises a conformal doped layer which has a thickness and doping concentration that are substantially independent of the physical orientation of the surfaces (e.g., that provides the same doping level at the top of a structure as on the sidewalls). It should be noted that while exemplary methods are illustrated and described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events, as some steps may occur in different orders and/or concurrently with other steps apart from that shown and described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Moreover, it will be appreciated that the methods may be implemented in association with the systems illustrated and described herein as well as in association with other systems not illustrated.

The method 200 of FIG. 2 begins at 202, wherein a semiconductor body or substrate (e.g., a silicon wafer, germanium substrate) is exposed to an activated hydrogen gas for a predetermined time period at a set temperature or temperature ramp. The activated hydrogen gas may comprise hydrogen ions, atoms and/or molecules in an excited state (e.g., exited atoms from a plasma that are allowed to recombine with electrons, thereby avoiding ionic species), which are configured to react with the semiconductor body and form a reactive layer having chemically reactive sites comprising weakened and/or dangling bonds. For example, in one embodiment, the activated hydrogen gas reacts with a silicon substrate, breaking existing silicon-silicon bonds and forming a reactive layer having chemically reactive sites comprising silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds, and/or dangling silicon bonds. It will be appreciated that the semiconductor body, as referred to herein, may comprise any type of semiconductor body (e.g., silicon, germanium, SiGe, SOI) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith.

The weakened bonds formed by the activated hydrogen gas can be easily depleted (i.e., broken), thereby providing reactive sites. In one embodiment, the weakened bonds (e.g., silicon-hydrogen bonds, silanol bonds, germanium-hydrogen bonds, germinol bonds, etc.) can subsequently be depleted by a thermal anneal and/or an ultraviolet exposure and/or a plasma exposure. For example, in one embodiment a thermal anneal can be used to break weakened Si—H, Si—OH, Ge—H, or Ge—OH bonds, thereby resulting in additional dangling silicon or germanium bonds (i.e., reactive sites) within the reactive layer.

At 204 a reactant is introduced to the surface of the semiconducting body or substrate. The reactant may be distributed to contact exposed (e.g., unmasked) surfaces of the semiconductor body and to react with the reactive sites comprised within the reactive layer of the semiconductor body. The reaction results in the reactant bonding to the substrate of the semiconductor body (e.g., by chemically bonding to the dangling bonds formed) and thereby results in a doped semiconductor body. Since such a hydrogen-substrate reaction occurs without a highly direction ion bombardment (e.g., from high energy ion implantation), the process provides an inherently isotropic doping that is substantially independent of the orientation of the surface.

In various embodiments, the reactant may be introduced to the surface of the semiconductor body in a gas phase. For example, a boron dopant reactant (e.g., B2H6, BCl3, or BF3) can be introduced into the atmosphere surrounding in the hydrogen exposed substrate. As stated above, the hydrogen activated substrate presents chemically reactive sites for boron dopant reactant to be incorporated into the substrate. In alternative embodiments, the reactant may be introduced to the surface of the semiconductor body in the liquid phase (e.g., a solution of boric acid and water). In either embodiment, the introduced reactant will be evenly distributed to the reactive sites on unmasked surfaces of the semiconductor body substantially independent of the physical orientation of the surface (e.g., allowing the same doping level to be achieved at a top surface and sidewall surfaces of a structure).

It will be appreciated that the depth and the density of the chemical reactions (e.g., bond breaking) achieved by the activated hydrogen gas can be varied by changing operational parameters of the exposure. For example, the depth and density of the chemical reaction may be a function of the concentration of the activated hydrogen gas (e.g., 50% hydrogen gas, 60% hydrogen gas, etc.), the species of the activated hydrogen gas (e.g., hydrogen ions, atoms, molecules, etc.), the temperature of the activated hydrogen gas, the substrate temperature, and/or the exposure time of a semiconductor body to the activated hydrogen gas. For example, the greater the time a semiconductor body is exposed to an activated hydrogen gas and/or the higher the temperature of the exposure and/or the higher the active hydrogen concentration, the deeper the chemical reaction will extend into the semiconductor body. In general, under typical processing conditions an activated hydrogen gas can be configured to form weakened and/or dangling bonds that extend into a top 10-300 Å of a surface of a semiconductor body.

Furthermore, it will be appreciated that the reactant may comprise various elements or compounds that can be used to satisfy a wide range of applications. For example, in one embodiment, the reactant may comprise an organic gas configured to result in carbon being incorporated to the hydrogen activated reactive sites on the semiconductor body. In alternative embodiments, the dopant element may comprise a dopant species (e.g., boron, phosphorus), thereby allowing the method may be used to dope semiconductor bodies. As will be more fully appreciated below, such embodiments may be useful in the fabrication of multi-gate device (e.g., tri-gate devices, gate-all-around devices, etc.) for evenly doping the various surfaces of the semiconductor body.

In other embodiments, the reactant may comprise a metal (e.g., tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), palladium (Pd), nickel (Ni), Platinum (Pt), etc.), wherein the metal is incorporated into the substrate. In such embodiments, when the substrate is annealed it may produce a conformal metal silicide, thereby promoting improved contact resistance. In yet another embodiment, the dopant element may be an oxygen or nitrogen containing gas (e.g., O2, N2O, NH3, N2), thereby resulting in the formation of a conformal oxide, nitride, or oxy-nitride structure.

FIG. 3 illustrates a flow diagram of a more detailed method 300 for providing a doping to one or more surfaces of a semiconductor body (e.g., a silicon substrate). In one embodiment, the method may provide a conformal doping that is substantially independent of the physical orientation of the surfaces. Furthermore, it will be appreciated that this method 300 may be used for a wide range of applications. For example, in one embodiment, the method 300 may be used to form a conformal doped semiconductor device. The method subjects a semiconductor body to an activated hydrogen gas which reacts with exposed surfaces of the substrate, breaking existing bonds (e.g., Si—Si bond), and forming chemically reactive sites which can subsequently be used to graft a dopant element to exposed surfaces of the semiconductor body.

FIG. 3 begins at 302, wherein a semiconductor body is selectively masked. A masking layer is deposited onto a cleaned semiconductor body. The masking layer can be selectively patterned to define one or more regions that are to be exposed to an activated hydrogen gas (e.g., doped). In one embodiment, the masking layer may comprise a photoresist layer. The photoresist layer may be formed on the substrate by depositing the photoresist onto the substrate and spinning the substrate at a high speed (e.g., 500-3000 RPM) or a sequence of high speeds resulting in an even distribution of photoresist over the surface of the substrate, for example. Photoresist comes in two tones, positive and negative. Positive photoresist will be structurally weakened when it is exposed and negative photoresist will be structurally strengthened when it is exposed.

In an alternative embodiment, the masking layer may comprise a hard mask. The hard mask can be formed above the semiconductor body and may be, for example, around 50 to 500 nm thick. The hard mask may comprise TiAlN, TiN, Ti, TiO2, Al, AlOx, AlN, TiAl, TiAlOx, Ta, TaOx, TaN, Cr, CrN, CrOx, Zr, ZrOx, ZrN, Hf, HfN, HfOx, silicon-rich nitride (SRN), silicon-rich oxynitride (SRON), silicon oxide, low-k dielectric, high-k dielectric, or any stack or combination thereof. An example of a hard mask stack is 300 nm of PECVD deposited SiO2 on 50 nm of sputter deposited TiAlN or TiN.

FIG. 4 illustrates a cross sectional view of a semiconductor body prior to processing provided by method 300. As shown in FIG. 4, silicon molecules comprise silicon-silicon bonds 404 that extend along the surface of the semiconductor body. It will be appreciated that the FIGS. 4 to 6 and 10 to 12 are intended only to convey ideas associated with method 300 and are not intended to be physically descriptive of the bonds existing in an actual silicon semiconductor body.

FIG. 5 illustrates a cross sectional view of a semiconductor body 402 comprising a masking layer 502 configured to mask part of the surface of the semiconductor body 402. As shown in FIG. 5 a three dimensional section, comprising a top surface and two sidewall surfaces is left unmasked, so that it can be acted upon by the subsequent method of doping.

At 304 the semiconductor body is exposed to an activated hydrogen gas. The activated hydrogen gas may comprise hydrogen ions, hydrogen atoms, hydrogen radicals, and/or hydrogen molecules in an excited state and/or hydrogen radicals. The activated hydrogen gas is configured to react with the semiconductor body, breaking existing bonds (e.g., silicon-silicon or germanium-germanium bonds), and forming a reactive layer comprising weakened and/or dangling bonds (e.g., Si—H, Si—OH, Ge—H, Ge—OH and Si or Ge dangling bonds).

The activated hydrogen gas may be formed by passing the hydrogen containing gas over a hot filament or by exciting atoms from a plasma and allowing them to recombine with electrons. This results in exited state hydrogen molecules while avoiding ionic species. For deeper reactions, hydrogen ions and excited-state hydrogen atoms may be used as generated by electron-impact dissociation for example. In one particular embodiment, the activated hydrogen gas may be formed from a plasma reaction of a hydrogen containing gas comprising one of more of H2, NH3, CH4, C2H6, H2S, HF, HCl, N2H4, HBr. Parameters of the activated hydrogen gas exposure can be adjusted to vary the depth and concentration of the reactive sites comprised within the reactive layer. For example, the depth and density of the bond breaking are a function of the length of time the semiconductor body is exposed to the active hydrogen as well as the concentration and temperature of the activated hydrogen gas. Therefore, while a semiconductor body exposed to active hydrogen for 80 seconds may result in a relatively thin reactive layer thickness (e.g., 5 nm), a semiconductor body exposed to active hydrogen for 300 seconds may result in a substantially thicker reactive layer thickness (e.g., 27.5 nm). In one embodiment, the hydrogen exposure is performed in a gas phase that is at a temperature of 0-600° C. and a pressure between 1 mtorr-760 torr.

As illustrated in FIG. 6, the activated hydrogen gas 602 interacts with exposed silicon-silicon bonds 404, but does not interact with silicon-silicon bonds 404 that are covered by the masking layer 502. The activated hydrogen gas 602 interacts with the silicon-silicon bonds 404 comprised within the reactive layer 604 of the semiconductor body 402 to generate reactive sites. The reactive layer 604 may extend many monolayers into the semiconductor surface and may be substantially independent of a surfaces orientation.

The reactive hydrogen layer is distinct from oxides typically formed on the surface of the semiconductor body due to physical characteristics such as weight and hydrogen concentration. These physical characteristics are shown in FIGS. 7 and 8 for an exemplary semiconductor body as provided herein.

For example, FIG. 7 illustrates a graph 700 showing hydrogen concentration in a semiconductor body as a function of distance from the surface. More particularly, the graph 700 illustrates three different secondary ion mass spectroscopy (SIMS) profiles. The x-axis of FIG. 7 illustrates the concentration of hydrogen in atoms/cubic centimeters and the y-axis illustrates the distance from the surface of the semiconductor surface. The first profile 702 illustrates the hydrogen concentration of a control wafer that is not exposed to an activated hydrogen gas. The hydrogen concentration of the first profile 702 decreases exponentially from the surface of the wafer in ward. In contrast, the second profile 704 and the third profile 706 illustrate an elevated hydrogen concentration that extends to a depth of approximately 10 nm within the substrate. The second profile 704 illustrates the hydrogen concentration of a substrate exposed to a low concentration of activated hydrogen gas. The third profile 706 illustrates the hydrogen concentration of a wafer exposed to a higher concentration of activated hydrogen gas. The penetration of the activated hydrogen gas into the silicon illustrates that the formation of reactive sites extends into the silicon substrate thereby allowing for dopant atoms to be formed onto the dangling bonds to significant depths. It will be appreciated that while the hydrogen is illustrated in FIG. 7 as extending to approximately 9 nm into the semiconductor body, that it can extend to a different depth (e.g., 1-30 nm) through adjusting parameters of the activated hydrogen gas exposure.

FIG. 8 shows a graph 800 illustrating control of the depth of the dopant distribution by controlling the active hydrogen concentration by diluting it into an inert gas (e.g., helium gas) at a constant time and temperature. The x-axis illustrates the active hydrogen concentration in a helium gas as a percentage. The y-axis illustrates the depth of dopants into the substrate in angstroms. As illustrated in FIG. 8, the depth of the dopant incorporated into the substrate increases as the activated hydrogen gas concentration is increased (e.g., illustrated by trend line 802).

It will be appreciated that the activated hydrogen gas may have an etching effect on the surface of a semiconductor body under certain conditions, thereby resulting in the loss of semiconductor material (e.g., silicon, germanium) from the substrate surface. Therefore, in an alternative embodiment, gas additives may optionally be added to the activated hydrogen gas. The gas additives may be added to help to control the active site formation and/or to reduce damage (e.g., reduce hydrogen etching of silicon) to the surface of the semiconductor body. For example, as shown in FIG. 9, increasing the concentration of N2 gas in an activated hydrogen gas may decrease the effect of hydrogen etching thereby reducing the loss of silicon on the surface of a semiconductor body. More particularly, as shown in FIG. 9, increasing the concentration of nitrogen gas (N2) in an activated hydrogen gas from 0% to 25% results in a decrease of silicon loss (e.g., from hundreds of angstroms of silicon loss to less than 10 angstroms of silicon loss). In alternative embodiments, gas additives that may be inserted to the hydrogen gas may include, but are not limited to, Nitrogen (N2), Ammonia (NH3), Helium (He), Argon (Ar), Neon (Ne), Oxygen (O2), Nitrous oxide (N2O), Carbon dioxide (CO2), and/or Carbon monoxide (CO).

Alternatively, the use of a pulsed plasma source (e.g., a DC generator configured to produce a pulsed plasma) may alternatively used to reduce etching of the semiconductor body or may be used in conjunction with an additive gas to further reduce etching of the semiconductor body.

At 306 and/or 310 a thermal anneal, ultraviolet (UV) exposure, or plasma exposure can be optionally performed on the semiconductor body. The optional thermal anneal, UV exposure, or plasma exposure changes the weakened bond (e.g., Si—H or Si—OH bonds) density. For example, in one embodiment, the optional thermal anneal, UV exposure, or plasma exposure can help to deplete weakened bonds (e.g., Si—H or Si—OH bonds) that have formed in the reactive layer, causing the hydrogen comprised within the weakened bonds to be desorbed, and thereby providing additional dangling bonds for subsequent doping. The optional thermal anneal, UV exposure, or plasma exposure can increase the number of dangling bonds present in the reactive layer, resulting in a higher density of dangling bonds (e.g., and an increased dopant concentration in a subsequent doped layer). Therefore, the optional thermal anneal, UV exposure, or plasma exposure can be used as a control device for dangling bond (e.g., and dopant) concentration in the semiconductor device.

In one embodiment, the optional thermal anneal can be performed using a conventional tube furnace, rapid thermal processor, or laser annealing system. The temperature used for the thermal anneal may vary depending on the bonds formed in the reactive layer of the semiconductor body. For example, in one embodiment, a silicon substrate can be heated to a temperature of between 600° K and 700° K, causing hydrogen from SiH2 species comprised within the reactive layer to be desorbed. In an alternative embodiment, a silicon substrate can be heated to a temperature of between 700° K and 800° K to cause hydrogen to desorb from a SiH species comprised within the reactive layer.

In one alternative embodiment, a UV exposure may result from an exposed semiconductor body being subjected to an ultraviolet illumination source (e.g., a source providing electromagnetic radiation having a wave length between 10 nm and 400 nm). In another alternative embodiment, a plasma exposure may result from an exposed semiconductor body being subjected to a plasma. In yet another alternative embodiment, one or more of the ultraviolet illumination sources and/or plasma exposure may be used in conjunction the thermal anneal to enhance desorption of hydrogen (e.g., breaking Si—H, Si—OH bonds) from the reactive layer. In another alternative embodiment, an ultraviolet illumination source and/or a plasma exposure may be used in place of or in combination with the thermal anneal to desorb hydrogen from the reactive layer.

FIG. 10 illustrates a cross sectional view 1000 of the semiconductor body 402 exposed to a thermal anneal 1002. As illustrated in FIG. 10, during exposure of a semiconductor body 402 to an elevated temperature, Si—H and/or Si—OH bonds in the reactive layer 604 will break, thereby providing additional dangling Si bonds in the reactive layer 604 of the semiconductor body.

A reactant is introduced at 308. The reactant is provided to contact the reactive layer in such a manner that it couples to the dangling bonds in the reactive layer, thereby grafting itself to unmasked parts of the semiconductor body. The reactant may comprise one or more elements. In one embodiment, the reactant may comprise an organic polymer configured to graft itself onto the surface of the semiconductor body. In an alternative embodiment, the reactant may comprise dopant atoms (e.g., boron species, phosphorous species) configured to react with the reactive sites to provide a dopant. The dopants may be provided to contact the reactive layer as a gas phase or as a liquid phase dopant. In various embodiments, the gas phase dopants may comprise B2H6, BF3, BCl3, PH3, ASH3, AsCl3, AsF3, AsF5, P2F4, PH4Cl, PCl2F, PClF2, PF3, PCl3, As(OC2H5)3, etc. Alternatively, the liquid phase dopants may comprise H3BO3, H3PO4, POCL, AsCl3, AsF3, H3AsO4, etc.

In an alternative embodiment, the reactant may comprise a metal configured to react with the reactive sites. The metal reactant may be provided to the reactive layer as a gas phase or a liquid phase. In various embodiments, the gas phase reactants may comprise metal containing gases in the form of a metal hydride, metal carbonyl, metal-organic. Respective metals within the metal containing gases may comprise tungsten, tantalum, titanium, nickel, ruthenium, palladium, platinum, etc.

In one embodiment, the reactant comprises an oxygen or nitrogen containing gas comprising an Oxygen gas (O2), a Nitrogen gas (N2), Ammonia (NH3), Nitrous Oxide (N2O), Carbon Dioxide (CO2), and/or Carbon Monoxide (CO). These reactants may be used to result in the formation of a conformal oxide, nitride, or oxy-nitride structure.

FIG. 11 illustrates a cross sectional view 1100 of the semiconductor body 402 exposed to a dopant gas 1102 (i.e., reactant). As illustrated in FIG. 11, the dopant gas reacts with unmasked sections of the semiconductor body 402, thereby grafting to the exposed dangling bonds of the reactive layer to from a doped layer 1104 comprising dopant atoms coupled to silicon atoms.

It will be appreciated that the method of doping a semiconductor body may vary depending on dopant used. For example, in one embodiment, wherein exposure of a silicon substrate to an activated hydrogen gas results in Si—OH bonds formed in the reactive layer, the silicon substrate can be exposed to a dopant element comprising boric acid (e.g., BOH3). The boric acid may subsequently react with the hydroxyl groups to for Si—O—B linkages, thereby resulting in a doped silicon substrate. Alternatively, other boron compounds such as BCl3, BF3, may also react with the Si—OH bonds comprised within the reactive layer to form a doped layer (e.g., SiOH+BCl3→SiOBCl2+HCl).

An optional activation anneal is performed at 312. The optional anneal activates the dopants that have been formed in the doped layer (i.e., grafted to the reactive layer dangling bonds). The length of the anneal may vary depending on the process. In one example, the anneal may be performed for one millisecond for a diffusionless anneal.

Therefore, as provided herein, the method 300 of FIG. 3 may provide a doping which can provide a doped layer thickness and doping concentration that are substantially independent of the physical orientation of a surface. It will be appreciated that the inventor has contemplated additional processing steps and/or different processing steps which may occur in addition to the method 500 disclosed herein.

FIG. 12 illustrates a semiconductor body as provided by method 300, comprising a doped silicon layer extending over multiple surfaces of a three-dimensional semiconductor body. As illustrated in FIG. 12, the semiconductor body 1200 comprises multiple surfaces (1202, 1204, 1206), wherein the surfaces are configured to have normal directions that are configured to have substantially different angles. For example, in FIG. 12 a first surface 1202 and a second surface 1204 have normal vectors that are perpendicular to each other. Respective surfaces (1202, 1204, 1206) of the semiconductor body 402 comprise a doped layer 1104. In one embodiment, the thickness of the doped layer on respective surfaces of the semiconductor body may be substantially uniform. For example, in FIG. 12, the thickness, t1, of the doped layer 1104 on the first surface 1202 is substantially equal to the thickness, t2, of the doped layer 1104 on the second surface 1204. In alternative embodiments, the thicknesses, t1 and t2, can be formed to substantially different thicknesses.

It will be appreciated that FIG. 12 illustrates one non-limiting example of a conformal doped semiconductor body provided herein. Other doped semiconductor bodies not provided herein (e.g., having different geometries) have also contemplated by the inventors. For example, although FIG. 12 illustrates the reactive layer as having a substantially constant thickness over the one or more surfaces, it will be appreciated that FIG. 12 is a non-limiting example of a substrate produced by method 300 and in alternative embodiments, method 300 may be configured to provide different doped layer thicknesses on different surfaces of the semiconductor body.

Furthermore, it will be appreciated that method 300 may be performed according to various embodiments and is not to be interpreted in a limiting sense. For example, the method 300 may be performed multiple times upon a single semiconductor body, respective performances of method 300 occurring with different reactants thereby resulting in increased control over the dopant layer (e.g., allowing the formation of a complex dopant layer comprising multiple reactants). For example, in one embodiment, method 300 may be performed a first time with a first reactant and a second time (e.g., immediately following the first application of method 300) with a second reactant. Alternatively, method 300 may be performed multiple times with different hydrogen activations and different reactant exposures to generate differing doping levels at different locations and different depths and concentrations.

In another embodiment, one or more different reactants may be mixed together to provide multiple simultaneous reactions. For example, a reactant may be configured to provide a doping comprising both a phosphorous and arsenic doping.

FIG. 13 illustrates a flow diagram of another embodiment of the present invention. FIG. 13 illustrates a method 1300 for providing a doping to one or more surfaces of a multi-gate semiconductor device that may be substantially independent of the physical orientation of the surfaces.

FIG. 13 begins at 1302 wherein a semiconductor body (e.g., silicon substrate, germanium substrate) is selectively masked. A masking layer is deposited onto a cleaned semiconductor body and is configured to define the doping region of the semiconductor device (e.g., leave a channel region of the semiconductor device unmasked so that it can subsequently be exposed to an activated hydrogen gas and dopant).

At 1304 the semiconductor body is exposed to an activated hydrogen gas. As stated above, the activated hydrogen gas may comprise hydrogen ions, hydrogen atoms, hydrogen radicals, hydrogen molecules, and/or hydrogen radicals and is configured to react with the semiconductor body to break existing bonds (e.g., silicon-silicon bonds) and form a reactive layer comprising weakened and/or dangling bonds (e.g., Si—H, Si—OH, and Si dangling bonds).

FIG. 14 illustrates a top view 1400 of a gate-all-around semiconductor device exposed to an activated hydrogen gas. The gate-all-around semiconductor device comprises a semiconductor channel region 1402, comprising the semiconductor body, unmasked on all sides. The activated hydrogen gas 1406 reacts with the semiconductor channel region 1402, modifying the surface region and thereby resulting in a reactive region 1404 comprising weakened and dangling bonds. The reactive region 1404 extends along all surfaces of the semiconductor channel region 1402.

A thermal anneal, ultraviolet (UV) exposure, or plasma exposure can be optionally performed on the semiconductor body at 1306 and/or 1310. As stated above, the optional thermal anneal, ultraviolet (UV) exposure, or plasma exposure depletes weakened bonds of the reactive region.

At 1308 a reactant is introduced. The reactant is introduced to the semiconductor body to chemically react with the reactive layer and to form a doped layer. As stated above, the dopant element may be introduced to the semicodunctor body as a gas phase or as a liquid phase.

FIG. 15 illustrates a top view 1500 of a gate-all-around semiconductor device exposed to a dopant gas 1502. The dopant gas reacts with the reactive region to form a doped region 1504. The doped region comprises the dopant gas 1502, which has been grafted to the reactive sites of the reactive region.

An optional activation anneal is performed at 1312. As stated above, the optional anneal activates the dopants that have been formed in the doped layer.

At 1314, a gate dielectric layer is formed over the semiconductor body. The gate dielectric layer is comprised of a dielectric material, such as oxide, and is formed with a suitable thickness. The dielectric material can include low-k and/or high-k dielectric materials.

A patterned gate layer is formed over the gate dielectric layer at 1316. The gate layer is comprised of a conductive material, such as polysilicon or a high-k metal gate material (e.g., hafnium dioxide (HfO2), zirconium dioxide (ZrO2) and titanium dioxide (TiO2), and is formed with a suitable thickness. A mask may be formed over the gate layer. The mask is configured to expose certain portions of the gate layer and cover other portions of the gate layer. The mask is typically comprised of a photoresist material, however other masking materials can alternatively be employed. The exposed portions of the gate layer may be patterned and the mask layer may be removed.

FIG. 16 illustrates a top view of a gate-all-around semiconductor device 1600 comprising a gate oxide layer 1602 and a gate layer 1604. The gate-all-around semiconductor device 1600 comprises a doped silicon layer 1504 (e.g., conformal doped silicon layer) extending over all surfaces of the device's conducting silicon channel 1402. The gate oxide 1602 is configured between the doped layer 1504 and the device's gates 1604 (e.g., polysilicon gates, metal gates) configured around the outer edge of the semiconductor channel region 1402. Therefore, the gate-all-around device 1600 can be formed from according to a single doping process (e.g., as shown in FIG. 13) applied to a single silicon channel 1402.

In an alternative embodiment, a SOI MOSFET comprising a tri-gate semiconductor device 1700 having a doped silicon layer extending over three surfaces of the device's conducting channel 1706 may also be formed according to method 1300. As illustrated in FIG. 17, the tri-gate semiconductor device 1700 is configured over a buried oxide layer 1704 that is located above a semiconductor body 1702 and comprises a channel region 1706 made of a semiconductor material (i.e., a silicon fin of a finFET device). The device is controlled by three gates 1712 (e.g., doped polysilicon gates), which are configured around three sides of the semiconductor channel region 1706. A thin gate oxide 1710 is configured between the channel region 1706 and the gates 1712. During operation, all three of the gates 1712 can be turned on, causing separate depletion region to form in the semiconductor channel region 1706. As is well known in the art, the multiple gates allow for an enhanced drive current when the device is turned on and a reduction in short channel effects (e.g., leakage current). The semiconductor device as provided in FIG. 17 is configured to have a conformal doped layer 1708 (e.g., n-type doped, p-type doped) extending along the sidewalls and the top of the semiconducting channel region 1706. The thickness and doping concentration of the conformal doped layer 1708 is substantially independent of the orientation of the surface, therefore providing for high quality device characteristics from each of the gates during device operation.

It will be appreciated that alternative embodiments of the devices illustrated in FIGS. 16 and 17, comprising alternative and/or additional layers, configurations, and/or materials, have also been contemplated by the inventors.

Although the invention has been shown and described with respect to a certain aspects and implementations, it will be appreciated that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary implementations of the invention. In this regard, it will also be recognized that the invention includes a computer-readable medium having computer-executable instructions for performing the steps of the various methods of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes”, “including”, “has”, “having”, and variants thereof are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term “comprising”.

Berry, Ivan L.

Patent Priority Assignee Title
10023960, Sep 12 2012 ASM IP Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
10032628, May 02 2016 ASM IP HOLDING B V Source/drain performance through conformal solid state doping
10043661, Jul 13 2015 ASM IP Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
10083836, Jul 24 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Formation of boron-doped titanium metal films with high work function
10087522, Apr 21 2016 ASM IP HOLDING B V Deposition of metal borides
10087525, Aug 04 2015 ASM IP Holding B.V. Variable gap hard stop design
10090316, Sep 01 2016 ASM IP Holding B.V.; ASM IP HOLDING B V 3D stacked multilayer semiconductor memory using doped select transistor channel
10103040, Mar 31 2017 ASM IP HOLDING B V Apparatus and method for manufacturing a semiconductor device
10134757, Nov 07 2016 ASM IP Holding B.V. Method of processing a substrate and a device manufactured by using the method
10167557, Mar 18 2014 ASM IP Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
10177025, Jul 28 2016 ASM IP HOLDING B V Method and apparatus for filling a gap
10179947, Nov 26 2013 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition
10190213, Apr 21 2016 ASM IP HOLDING B V Deposition of metal borides
10211308, Oct 21 2015 ASM IP Holding B.V. NbMC layers
10229833, Nov 01 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
10236177, Aug 22 2017 ASM IP HOLDING B V Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures
10249524, Aug 09 2017 ASM IP Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
10249577, May 17 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method
10262859, Mar 24 2016 ASM IP Holding B.V. Process for forming a film on a substrate using multi-port injection assemblies
10269558, Dec 22 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method of forming a structure on a substrate
10276355, Mar 12 2015 ASM IP Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
10283353, Mar 29 2017 ASM IP HOLDING B V Method of reforming insulating film deposited on substrate with recess pattern
10290508, Dec 05 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming vertical spacers for spacer-defined patterning
10312055, Jul 26 2017 ASM IP Holding B.V. Method of depositing film by PEALD using negative bias
10312129, Sep 29 2015 ASM IP Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
10319588, Oct 10 2017 ASM IP HOLDING B V Method for depositing a metal chalcogenide on a substrate by cyclical deposition
10322384, Nov 09 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Counter flow mixer for process chamber
10340125, Mar 08 2013 ASM IP Holding B.V. Pulsed remote plasma method and system
10340135, Nov 28 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride
10343920, Mar 18 2016 ASM IP HOLDING B V Aligned carbon nanotubes
10361201, Sep 27 2013 ASM IP Holding B.V. Semiconductor structure and device formed using selective epitaxial process
10364496, Jun 27 2011 ASM IP Holding B.V. Dual section module having shared and unshared mass flow controllers
10366864, Mar 18 2013 ASM IP Holding B.V. Method and system for in-situ formation of intermediate reactive species
10367080, May 02 2016 ASM IP HOLDING B V Method of forming a germanium oxynitride film
10378106, Nov 14 2008 ASM IP Holding B.V. Method of forming insulation film by modified PEALD
10381219, Oct 25 2018 ASM IP Holding B.V. Methods for forming a silicon nitride film
10381226, Jul 27 2016 ASM IP Holding B.V. Method of processing substrate
10388509, Jun 28 2016 ASM IP Holding B.V. Formation of epitaxial layers via dislocation filtering
10388513, Jul 03 2018 ASM IP Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
10395919, Jul 28 2016 ASM IP HOLDING B V Method and apparatus for filling a gap
10403504, Oct 05 2017 ASM IP HOLDING B V Method for selectively depositing a metallic film on a substrate
10410943, Oct 13 2016 ASM IP Holding B.V. Method for passivating a surface of a semiconductor and related systems
10435790, Nov 01 2016 ASM IP Holding B.V. Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap
10438965, Dec 22 2014 ASM IP Holding B.V. Semiconductor device and manufacturing method thereof
10446393, May 08 2017 ASM IP Holding B.V. Methods for forming silicon-containing epitaxial layers and related semiconductor device structures
10458018, Jun 26 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Structures including metal carbide material, devices including the structures, and methods of forming same
10468251, Feb 19 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
10468261, Feb 15 2017 ASM IP HOLDING B V Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
10468262, Feb 15 2017 ASM IP Holding B.V. Methods for forming a metallic film on a substrate by a cyclical deposition and related semiconductor device structures
10480072, Apr 06 2009 ASM IP HOLDING B V Semiconductor processing reactor and components thereof
10483099, Jul 26 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming thermally stable organosilicon polymer film
10501866, Mar 09 2016 ASM IP Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
10504742, May 31 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Method of atomic layer etching using hydrogen plasma
10510536, Mar 29 2018 ASM IP Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
10529542, Mar 11 2015 ASM IP Holdings B.V. Cross-flow reactor and method
10529554, Feb 19 2016 ASM IP Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
10529563, Mar 29 2017 ASM IP Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
10535516, Feb 01 2018 ASM IP Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
10541173, Jul 08 2016 ASM IP Holding B.V. Selective deposition method to form air gaps
10541333, Jul 19 2017 ASM IP Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
10559458, Nov 26 2018 ASM IP Holding B.V. Method of forming oxynitride film
10561975, Oct 07 2014 ASM IP Holdings B.V. Variable conductance gas distribution apparatus and method
10566223, Aug 28 2012 ASM IP Holdings B.V.; ASM IP HOLDING B V Systems and methods for dynamic semiconductor process scheduling
10590535, Jul 26 2017 ASM IP HOLDING B V Chemical treatment, deposition and/or infiltration apparatus and method for using the same
10600673, Jul 07 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Magnetic susceptor to baseplate seal
10604847, Mar 18 2014 ASM IP Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
10605530, Jul 26 2017 ASM IP Holding B.V. Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace
10607895, Sep 18 2017 ASM IP HOLDING B V Method for forming a semiconductor device structure comprising a gate fill metal
10612136, Jun 29 2018 ASM IP HOLDING B V ; ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
10612137, Jul 08 2016 ASM IP HOLDING B V Organic reactants for atomic layer deposition
10622375, Nov 07 2016 ASM IP Holding B.V. Method of processing a substrate and a device manufactured by using the method
10643826, Oct 26 2016 ASM IP HOLDING B V Methods for thermally calibrating reaction chambers
10643904, Nov 01 2016 ASM IP HOLDING B V Methods for forming a semiconductor device and related semiconductor device structures
10644025, Nov 07 2016 ASM IP Holding B.V. Method of processing a substrate and a device manufactured by using the method
10655221, Feb 09 2017 ASM IP Holding B.V. Method for depositing oxide film by thermal ALD and PEALD
10658181, Feb 20 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Method of spacer-defined direct patterning in semiconductor fabrication
10658205, Sep 28 2017 ASM IP HOLDING B V Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
10665452, May 02 2016 ASM IP Holdings B.V. Source/drain performance through conformal solid state doping
10672636, Aug 09 2017 ASM IP Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
10683571, Feb 25 2014 ASM IP Holding B.V. Gas supply manifold and method of supplying gases to chamber using same
10685834, Jul 05 2017 ASM IP Holdings B.V. Methods for forming a silicon germanium tin layer and related semiconductor device structures
10692741, Aug 08 2017 ASM IP Holdings B.V.; ASM IP HOLDING B V Radiation shield
10707106, Jun 06 2011 ASM IP Holding B.V.; ASM IP HOLDING B V High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
10714315, Oct 12 2012 ASM IP Holdings B.V.; ASM IP HOLDING B V Semiconductor reaction chamber showerhead
10714335, Apr 25 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Method of depositing thin film and method of manufacturing semiconductor device
10714350, Nov 01 2016 ASM IP Holdings, B.V.; ASM IP HOLDING B V Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
10714385, Jul 19 2016 ASM IP Holding B.V. Selective deposition of tungsten
10720322, Feb 19 2016 ASM IP Holding B.V. Method for forming silicon nitride film selectively on top surface
10720331, Nov 01 2016 ASM IP Holdings, B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
10731249, Feb 15 2018 ASM IP HOLDING B V Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus
10734223, Oct 10 2017 ASM IP Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
10734244, Nov 16 2017 ASM IP Holding B.V. Method of processing a substrate and a device manufactured by the same
10734497, Jul 18 2017 ASM IP HOLDING B V Methods for forming a semiconductor device structure and related semiconductor device structures
10741385, Jul 28 2016 ASM IP HOLDING B V Method and apparatus for filling a gap
10755922, Jul 03 2018 ASM IP HOLDING B V Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
10755923, Jul 03 2018 ASM IP Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
10767789, Jul 16 2018 ASM IP Holding B.V. Diaphragm valves, valve components, and methods for forming valve components
10770286, May 08 2017 ASM IP Holdings B.V.; ASM IP HOLDING B V Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
10770336, Aug 08 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Substrate lift mechanism and reactor including same
10784102, Dec 22 2016 ASM IP Holding B.V. Method of forming a structure on a substrate
10787741, Aug 21 2014 ASM IP Holding B.V. Method and system for in situ formation of gas-phase compounds
10797133, Jun 21 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
10804098, Aug 14 2009 ASM IP HOLDING B V Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
10811256, Oct 16 2018 ASM IP Holding B.V. Method for etching a carbon-containing feature
10818758, Nov 16 2018 ASM IP Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
10829852, Aug 16 2018 ASM IP Holding B.V. Gas distribution device for a wafer processing apparatus
10832903, Oct 28 2011 ASM IP Holding B.V. Process feed management for semiconductor substrate processing
10844484, Sep 22 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
10844486, Apr 06 2009 ASM IP HOLDING B V Semiconductor processing reactor and components thereof
10847365, Oct 11 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Method of forming conformal silicon carbide film by cyclic CVD
10847366, Nov 16 2018 ASM IP Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
10847371, Mar 27 2018 ASM IP Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
10851456, Apr 21 2016 ASM IP Holding B.V. Deposition of metal borides
10854498, Jul 15 2011 ASM IP Holding B.V.; ASM JAPAN K K Wafer-supporting device and method for producing same
10858737, Jul 28 2014 ASM IP Holding B.V.; ASM IP HOLDING B V Showerhead assembly and components thereof
10865475, Apr 21 2016 ASM IP HOLDING B V Deposition of metal borides and silicides
10867786, Mar 30 2018 ASM IP Holding B.V. Substrate processing method
10867788, Dec 28 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method of forming a structure on a substrate
10872771, Jan 16 2018 ASM IP Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
10883175, Aug 09 2018 ASM IP HOLDING B V Vertical furnace for processing substrates and a liner for use therein
10886123, Jun 02 2017 ASM IP Holding B.V. Methods for forming low temperature semiconductor layers and related semiconductor device structures
10892156, May 08 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
10896820, Feb 14 2018 ASM IP HOLDING B V Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
10910262, Nov 16 2017 ASM IP HOLDING B V Method of selectively depositing a capping layer structure on a semiconductor device structure
10914004, Jun 29 2018 ASM IP Holding B.V. Thin-film deposition method and manufacturing method of semiconductor device
10923344, Oct 30 2017 ASM IP HOLDING B V Methods for forming a semiconductor structure and related semiconductor structures
10928731, Sep 21 2017 ASM IP Holding B.V. Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same
10934619, Nov 15 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Gas supply unit and substrate processing apparatus including the gas supply unit
10941490, Oct 07 2014 ASM IP Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
10943771, Oct 26 2016 ASM IP Holding B.V. Methods for thermally calibrating reaction chambers
10950432, Apr 25 2017 ASM IP Holding B.V. Method of depositing thin film and method of manufacturing semiconductor device
10975470, Feb 23 2018 ASM IP Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
11001925, Dec 19 2016 ASM IP Holding B.V. Substrate processing apparatus
11004977, Jul 19 2017 ASM IP Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
11015245, Mar 19 2014 ASM IP Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
11018002, Jul 19 2017 ASM IP Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
11018047, Jan 25 2018 ASM IP Holding B.V. Hybrid lift pin
11022879, Nov 24 2017 ASM IP Holding B.V. Method of forming an enhanced unexposed photoresist layer
11024523, Sep 11 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Substrate processing apparatus and method
11031242, Nov 07 2018 ASM IP Holding B.V. Methods for depositing a boron doped silicon germanium film
11049751, Sep 14 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
11053591, Aug 06 2018 ASM IP Holding B.V. Multi-port gas injection system and reactor system including same
11056344, Aug 30 2017 ASM IP HOLDING B V Layer forming method
11056567, May 11 2018 ASM IP Holding B.V. Method of forming a doped metal carbide film on a substrate and related semiconductor device structures
11069510, Aug 30 2017 ASM IP Holding B.V. Substrate processing apparatus
11081345, Feb 06 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Method of post-deposition treatment for silicon oxide film
11087997, Oct 31 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Substrate processing apparatus for processing substrates
11088002, Mar 29 2018 ASM IP HOLDING B V Substrate rack and a substrate processing system and method
11094546, Oct 05 2017 ASM IP Holding B.V. Method for selectively depositing a metallic film on a substrate
11094582, Jul 08 2016 ASM IP Holding B.V. Selective deposition method to form air gaps
11101370, May 02 2016 ASM IP Holding B.V. Method of forming a germanium oxynitride film
11107676, Jul 28 2016 ASM IP Holding B.V. Method and apparatus for filling a gap
11114283, Mar 16 2018 ASM IP Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
11114294, Mar 08 2019 ASM IP Holding B.V. Structure including SiOC layer and method of forming same
11127589, Feb 01 2019 ASM IP Holding B.V. Method of topology-selective film formation of silicon oxide
11127617, Nov 27 2017 ASM IP HOLDING B V Storage device for storing wafer cassettes for use with a batch furnace
11139191, Aug 09 2017 ASM IP HOLDING B V Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
11139308, Dec 29 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Atomic layer deposition of III-V compounds to form V-NAND devices
11158513, Dec 13 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
11164955, Jul 18 2017 ASM IP Holding B.V. Methods for forming a semiconductor device structure and related semiconductor device structures
11168395, Jun 29 2018 ASM IP Holding B.V. Temperature-controlled flange and reactor system including same
11171025, Jan 22 2019 ASM IP Holding B.V. Substrate processing device
11205585, Jul 28 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Substrate processing apparatus and method of operating the same
11217444, Nov 30 2018 ASM IP HOLDING B V Method for forming an ultraviolet radiation responsive metal oxide-containing film
11222772, Dec 14 2016 ASM IP Holding B.V. Substrate processing apparatus
11227782, Jul 31 2019 ASM IP Holding B.V. Vertical batch furnace assembly
11227789, Feb 20 2019 ASM IP Holding B.V. Method and apparatus for filling a recess formed within a substrate surface
11230766, Mar 29 2018 ASM IP HOLDING B V Substrate processing apparatus and method
11232963, Oct 03 2018 ASM IP Holding B.V. Substrate processing apparatus and method
11233133, Oct 21 2015 ASM IP Holding B.V. NbMC layers
11242598, Jun 26 2015 ASM IP Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
11244825, Nov 16 2018 ASM IP Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
11251035, Dec 22 2016 ASM IP Holding B.V. Method of forming a structure on a substrate
11251040, Feb 20 2019 ASM IP Holding B.V. Cyclical deposition method including treatment step and apparatus for same
11251068, Oct 19 2018 ASM IP Holding B.V. Substrate processing apparatus and substrate processing method
11270899, Jun 04 2018 ASM IP Holding B.V. Wafer handling chamber with moisture reduction
11274369, Sep 11 2018 ASM IP Holding B.V. Thin film deposition method
11282698, Jul 19 2019 ASM IP Holding B.V. Method of forming topology-controlled amorphous carbon polymer film
11286558, Aug 23 2019 ASM IP Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
11286562, Jun 08 2018 ASM IP Holding B.V. Gas-phase chemical reactor and method of using same
11289326, May 07 2019 ASM IP Holding B.V. Method for reforming amorphous carbon polymer film
11295980, Aug 30 2017 ASM IP HOLDING B V Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
11296189, Jun 21 2018 ASM IP Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
11306395, Jun 28 2017 ASM IP HOLDING B V Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
11315794, Oct 21 2019 ASM IP Holding B.V. Apparatus and methods for selectively etching films
11339476, Oct 08 2019 ASM IP Holding B.V. Substrate processing device having connection plates, substrate processing method
11342216, Feb 20 2019 ASM IP Holding B.V. Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
11345999, Jun 06 2019 ASM IP Holding B.V. Method of using a gas-phase reactor system including analyzing exhausted gas
11355338, May 10 2019 ASM IP Holding B.V. Method of depositing material onto a surface and structure formed according to the method
11361990, May 28 2018 ASM IP Holding B.V. Substrate processing method and device manufactured by using the same
11374112, Jul 19 2017 ASM IP Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
11378337, Mar 28 2019 ASM IP Holding B.V. Door opener and substrate processing apparatus provided therewith
11387106, Feb 14 2018 ASM IP Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
11387120, Sep 28 2017 ASM IP Holding B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
11390945, Jul 03 2019 ASM IP Holding B.V. Temperature control assembly for substrate processing apparatus and method of using same
11390946, Jan 17 2019 ASM IP Holding B.V. Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
11390950, Jan 10 2017 ASM IP HOLDING B V Reactor system and method to reduce residue buildup during a film deposition process
11393690, Jan 19 2018 ASM IP HOLDING B V Deposition method
11396702, Nov 15 2016 ASM IP Holding B.V. Gas supply unit and substrate processing apparatus including the gas supply unit
11398382, Mar 27 2018 ASM IP Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
11401605, Nov 26 2019 ASM IP Holding B.V. Substrate processing apparatus
11410851, Feb 15 2017 ASM IP Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
11411088, Nov 16 2018 ASM IP Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
11414760, Oct 08 2018 ASM IP Holding B.V. Substrate support unit, thin film deposition apparatus including the same, and substrate processing apparatus including the same
11417545, Aug 08 2017 ASM IP Holding B.V. Radiation shield
11424119, Mar 08 2019 ASM IP HOLDING B V Method for selective deposition of silicon nitride layer and structure including selectively-deposited silicon nitride layer
11430640, Jul 30 2019 ASM IP Holding B.V. Substrate processing apparatus
11430674, Aug 22 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
11437241, Apr 08 2020 ASM IP Holding B.V. Apparatus and methods for selectively etching silicon oxide films
11443926, Jul 30 2019 ASM IP Holding B.V. Substrate processing apparatus
11447861, Dec 15 2016 ASM IP HOLDING B V Sequential infiltration synthesis apparatus and a method of forming a patterned structure
11447864, Apr 19 2019 ASM IP Holding B.V. Layer forming method and apparatus
11453943, May 25 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
11453946, Jun 06 2019 ASM IP Holding B.V. Gas-phase reactor system including a gas detector
11469098, May 08 2018 ASM IP Holding B.V. Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
11473195, Mar 01 2018 ASM IP Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
11476109, Jun 11 2019 ASM IP Holding B.V. Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method
11482412, Jan 19 2018 ASM IP HOLDING B V Method for depositing a gap-fill layer by plasma-assisted deposition
11482418, Feb 20 2018 ASM IP Holding B.V. Substrate processing method and apparatus
11482533, Feb 20 2019 ASM IP Holding B.V. Apparatus and methods for plug fill deposition in 3-D NAND applications
11488819, Dec 04 2018 ASM IP Holding B.V. Method of cleaning substrate processing apparatus
11488854, Mar 11 2020 ASM IP Holding B.V. Substrate handling device with adjustable joints
11492703, Jun 27 2018 ASM IP HOLDING B V Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
11495459, Sep 04 2019 ASM IP Holding B.V. Methods for selective deposition using a sacrificial capping layer
11499222, Jun 27 2018 ASM IP HOLDING B V Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
11499226, Nov 02 2018 ASM IP Holding B.V. Substrate supporting unit and a substrate processing device including the same
11501956, Oct 12 2012 ASM IP Holding B.V. Semiconductor reaction chamber showerhead
11501968, Nov 15 2019 ASM IP Holding B.V.; ASM IP HOLDING B V Method for providing a semiconductor device with silicon filled gaps
11501973, Jan 16 2018 ASM IP Holding B.V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
11515187, May 01 2020 ASM IP Holding B.V.; ASM IP HOLDING B V Fast FOUP swapping with a FOUP handler
11515188, May 16 2019 ASM IP Holding B.V. Wafer boat handling device, vertical batch furnace and method
11521851, Feb 03 2020 ASM IP HOLDING B V Method of forming structures including a vanadium or indium layer
11527400, Aug 23 2019 ASM IP Holding B.V. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
11527403, Dec 19 2019 ASM IP Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
11530483, Jun 21 2018 ASM IP Holding B.V. Substrate processing system
11530876, Apr 24 2020 ASM IP Holding B.V. Vertical batch furnace assembly comprising a cooling gas supply
11532757, Oct 27 2016 ASM IP Holding B.V. Deposition of charge trapping layers
11551912, Jan 20 2020 ASM IP Holding B.V. Method of forming thin film and method of modifying surface of thin film
11551925, Apr 01 2019 ASM IP Holding B.V. Method for manufacturing a semiconductor device
11557474, Jul 29 2019 ASM IP Holding B.V. Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation
11562901, Sep 25 2019 ASM IP Holding B.V. Substrate processing method
11572620, Nov 06 2018 ASM IP Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
11581186, Dec 15 2016 ASM IP HOLDING B V Sequential infiltration synthesis apparatus
11581220, Aug 30 2017 ASM IP Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
11587814, Jul 31 2019 ASM IP Holding B.V. Vertical batch furnace assembly
11587815, Jul 31 2019 ASM IP Holding B.V. Vertical batch furnace assembly
11587821, Aug 08 2017 ASM IP Holding B.V. Substrate lift mechanism and reactor including same
11594450, Aug 22 2019 ASM IP HOLDING B V Method for forming a structure with a hole
11594600, Nov 05 2019 ASM IP Holding B.V. Structures with doped semiconductor layers and methods and systems for forming same
11605528, Jul 09 2019 ASM IP Holding B.V. Plasma device using coaxial waveguide, and substrate treatment method
11610774, Oct 02 2019 ASM IP Holding B.V. Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process
11610775, Jul 28 2016 ASM IP HOLDING B V Method and apparatus for filling a gap
11615970, Jul 17 2019 ASM IP HOLDING B V Radical assist ignition plasma system and method
11615980, Feb 20 2019 ASM IP Holding B.V. Method and apparatus for filling a recess formed within a substrate surface
11626308, May 13 2020 ASM IP Holding B.V. Laser alignment fixture for a reactor system
11626316, Nov 20 2019 ASM IP Holding B.V. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
11629406, Mar 09 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
11629407, Feb 22 2019 ASM IP Holding B.V. Substrate processing apparatus and method for processing substrates
11637011, Oct 16 2019 ASM IP Holding B.V. Method of topology-selective film formation of silicon oxide
11637014, Oct 17 2019 ASM IP Holding B.V. Methods for selective deposition of doped semiconductor material
11639548, Aug 21 2019 ASM IP Holding B.V. Film-forming material mixed-gas forming device and film forming device
11639811, Nov 27 2017 ASM IP HOLDING B V Apparatus including a clean mini environment
11643724, Jul 18 2019 ASM IP Holding B.V. Method of forming structures using a neutral beam
11644758, Jul 17 2020 ASM IP Holding B.V. Structures and methods for use in photolithography
11646184, Nov 29 2019 ASM IP Holding B.V. Substrate processing apparatus
11646197, Jul 03 2018 ASM IP Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
11646204, Jun 24 2020 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming a layer provided with silicon
11646205, Oct 29 2019 ASM IP Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
11649546, Jul 08 2016 ASM IP Holding B.V. Organic reactants for atomic layer deposition
11658029, Dec 14 2018 ASM IP HOLDING B V Method of forming a device structure using selective deposition of gallium nitride and system for same
11658030, Mar 29 2017 ASM IP Holding B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
11658035, Jun 30 2020 ASM IP HOLDING B V Substrate processing method
11664199, Oct 19 2018 ASM IP Holding B.V. Substrate processing apparatus and substrate processing method
11664245, Jul 16 2019 ASM IP Holding B.V. Substrate processing device
11664267, Jul 10 2019 ASM IP Holding B.V. Substrate support assembly and substrate processing device including the same
11674220, Jul 20 2020 ASM IP Holding B.V. Method for depositing molybdenum layers using an underlayer
11676812, Feb 19 2016 ASM IP Holding B.V. Method for forming silicon nitride film selectively on top/bottom portions
11680839, Aug 05 2019 ASM IP Holding B.V. Liquid level sensor for a chemical source vessel
11682572, Nov 27 2017 ASM IP Holdings B.V. Storage device for storing wafer cassettes for use with a batch furnace
11685991, Feb 14 2018 ASM IP HOLDING B V ; Universiteit Gent Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
11688603, Jul 17 2019 ASM IP Holding B.V. Methods of forming silicon germanium structures
11694892, Jul 28 2016 ASM IP Holding B.V. Method and apparatus for filling a gap
11695054, Jul 18 2017 ASM IP Holding B.V. Methods for forming a semiconductor device structure and related semiconductor device structures
11705333, May 21 2020 ASM IP Holding B.V. Structures including multiple carbon layers and methods of forming and using same
11718913, Jun 04 2018 ASM IP Holding B.V.; ASM IP HOLDING B V Gas distribution system and reactor system including same
11725277, Jul 20 2011 ASM IP HOLDING B V Pressure transmitter for a semiconductor processing environment
11725280, Aug 26 2020 ASM IP Holding B.V. Method for forming metal silicon oxide and metal silicon oxynitride layers
11735414, Feb 06 2018 ASM IP Holding B.V. Method of post-deposition treatment for silicon oxide film
11735422, Oct 10 2019 ASM IP HOLDING B V Method of forming a photoresist underlayer and structure including same
11735445, Oct 31 2018 ASM IP Holding B.V. Substrate processing apparatus for processing substrates
11742189, Mar 12 2015 ASM IP Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
11742198, Mar 08 2019 ASM IP Holding B.V. Structure including SiOCN layer and method of forming same
11746414, Jul 03 2019 ASM IP Holding B.V. Temperature control assembly for substrate processing apparatus and method of using same
11749562, Jul 08 2016 ASM IP Holding B.V. Selective deposition method to form air gaps
11767589, May 29 2020 ASM IP Holding B.V. Substrate processing device
11769670, Dec 13 2018 ASM IP Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
11769682, Aug 09 2017 ASM IP Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
11776846, Feb 07 2020 ASM IP Holding B.V. Methods for depositing gap filling fluids and related systems and devices
11781221, May 07 2019 ASM IP Holding B.V. Chemical source vessel with dip tube
11781243, Feb 17 2020 ASM IP Holding B.V. Method for depositing low temperature phosphorous-doped silicon
11795545, Oct 07 2014 ASM IP Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
11798830, May 01 2020 ASM IP Holding B.V. Fast FOUP swapping with a FOUP handler
11798834, Feb 20 2019 ASM IP Holding B.V. Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
11798999, Nov 16 2018 ASM IP Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
11802338, Jul 26 2017 ASM IP Holding B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
11804364, May 19 2020 ASM IP Holding B.V. Substrate processing apparatus
11804388, Sep 11 2018 ASM IP Holding B.V. Substrate processing apparatus and method
11810788, Nov 01 2016 ASM IP Holding B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
11814715, Jun 27 2018 ASM IP Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
11814747, Apr 24 2019 ASM IP Holding B.V. Gas-phase reactor system-with a reaction chamber, a solid precursor source vessel, a gas distribution system, and a flange assembly
11821078, Apr 15 2020 ASM IP HOLDING B V Method for forming precoat film and method for forming silicon-containing film
11823866, Apr 02 2020 ASM IP Holding B.V. Thin film forming method
11823876, Sep 05 2019 ASM IP Holding B.V.; ASM IP HOLDING B V Substrate processing apparatus
11827978, Aug 23 2019 ASM IP Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
11827981, Oct 14 2020 ASM IP HOLDING B V Method of depositing material on stepped structure
11828707, Feb 04 2020 ASM IP Holding B.V. Method and apparatus for transmittance measurements of large articles
11830730, Aug 29 2017 ASM IP HOLDING B V Layer forming method and apparatus
11830738, Apr 03 2020 ASM IP Holding B.V. Method for forming barrier layer and method for manufacturing semiconductor device
11837483, Jun 04 2018 ASM IP Holding B.V. Wafer handling chamber with moisture reduction
11837494, Mar 11 2020 ASM IP Holding B.V. Substrate handling device with adjustable joints
11840761, Dec 04 2019 ASM IP Holding B.V. Substrate processing apparatus
11848200, May 08 2017 ASM IP Holding B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
11851755, Dec 15 2016 ASM IP Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
11866823, Nov 02 2018 ASM IP Holding B.V. Substrate supporting unit and a substrate processing device including the same
11873557, Oct 22 2020 ASM IP HOLDING B V Method of depositing vanadium metal
11876008, Jul 31 2019 ASM IP Holding B.V. Vertical batch furnace assembly
11876356, Mar 11 2020 ASM IP Holding B.V. Lockout tagout assembly and system and method of using same
11885013, Dec 17 2019 ASM IP Holding B.V. Method of forming vanadium nitride layer and structure including the vanadium nitride layer
11885020, Dec 22 2020 ASM IP Holding B.V. Transition metal deposition method
11885023, Oct 01 2018 ASM IP Holding B.V. Substrate retaining apparatus, system including the apparatus, and method of using same
11887857, Apr 24 2020 ASM IP Holding B.V. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
11891696, Nov 30 2020 ASM IP Holding B.V. Injector configured for arrangement within a reaction chamber of a substrate processing apparatus
11898242, Aug 23 2019 ASM IP Holding B.V. Methods for forming a polycrystalline molybdenum film over a surface of a substrate and related structures including a polycrystalline molybdenum film
11898243, Apr 24 2020 ASM IP Holding B.V. Method of forming vanadium nitride-containing layer
11901175, Mar 08 2019 ASM IP Holding B.V. Method for selective deposition of silicon nitride layer and structure including selectively-deposited silicon nitride layer
11901179, Oct 28 2020 ASM IP HOLDING B V Method and device for depositing silicon onto substrates
11908684, Jun 11 2019 ASM IP Holding B.V. Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method
11908733, May 28 2018 ASM IP Holding B.V. Substrate processing method and device manufactured by using the same
11915929, Nov 26 2019 ASM IP Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
8877655, May 07 2010 ASM IP HOLDING B V Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
8883270, Aug 14 2009 ASM IP HOLDING B V Systems and methods for thin-film deposition of metal oxides using excited nitrogen—oxygen species
8894870, Feb 01 2013 ASM IP Holding B.V.; ASM IP HOLDING B V Multi-step method and apparatus for etching compounds containing a metal
8933375, Jun 27 2012 ASM IP Holding B.V. Susceptor heater and method of heating a substrate
8986456, Oct 10 2006 ASM IP HOLDING B V Precursor delivery system
8993054, Jul 12 2013 ASM IP Holding B.V. Method and system to reduce outgassing in a reaction chamber
9005539, Nov 23 2011 ASM IP Holding B.V. Chamber sealing member
9017481, Oct 28 2011 ASM IP HOLDING B V Process feed management for semiconductor substrate processing
9018111, Jul 22 2013 ASM IP Holding B.V. Semiconductor reaction chamber with plasma capabilities
9021985, Sep 12 2012 ASM IP Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
9029253, May 02 2012 ASM IP Holding B.V. Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same
9096931, Oct 27 2011 ASM IP HOLDING B V Deposition valve assembly and method of heating the same
9105559, Sep 16 2013 GLOBALFOUNDRIES Inc Conformal doping for FinFET devices
9117866, Jul 31 2012 ASM IP Holding B.V.; ASM IP HOLDING B V Apparatus and method for calculating a wafer position in a processing chamber under process conditions
9169975, Aug 28 2012 ASM IP Holding B.V. Systems and methods for mass flow controller verification
9177784, May 07 2012 ASM IP Holdings B.V. Semiconductor device dielectric interface layer
9202727, Mar 02 2012 ASM IP HOLDING B V Susceptor heater shim
9228259, Feb 01 2013 ASM IP Holding B.V. Method for treatment of deposition reactor
9240412, Sep 27 2013 ASM IP Holding B.V.; ASM IP HOLDING B V Semiconductor structure and device and methods of forming same using selective epitaxial process
9299595, Jun 27 2012 ASM IP Holding B.V. Susceptor heater and method of heating a substrate
9324811, Sep 26 2012 ASM IP Holding B.V.; ASM IP HOLDING B V Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
9340874, Nov 23 2011 ASM IP Holding B.V. Chamber sealing member
9341296, Oct 27 2011 ASM IP HOLDING B V Heater jacket for a fluid line
9384987, Apr 04 2012 ASM IP Holding B.V.; ASM IP HOLDING B V Metal oxide protective layer for a semiconductor device
9394608, Apr 06 2009 ASM IP HOLDING B V Semiconductor processing reactor and components thereof
9404587, Apr 24 2014 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
9412564, Jul 22 2013 ASM IP Holding B.V. Semiconductor reaction chamber with plasma capabilities
9447498, Mar 18 2014 ASM IP Holding B.V.; ASM IP HOLDING B V Method for performing uniform processing in gas system-sharing multiple reaction chambers
9455138, Nov 10 2015 ASM IP HOLDING B V Method for forming dielectric film in trenches by PEALD using H-containing gas
9478415, Feb 13 2015 ASM IP Holding B.V. Method for forming film having low resistance and shallow junction depth
9484191, Mar 08 2013 ASM IP Holding B.V. Pulsed remote plasma method and system
9543180, Aug 01 2014 ASM IP Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
9556516, Oct 09 2013 ASM IP Holding B.V; ASM IP HOLDING B V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
9558931, Jul 27 2012 ASM IP HOLDING B V System and method for gas-phase sulfur passivation of a semiconductor surface
9589770, Mar 08 2013 ASM IP Holding B.V. Method and systems for in-situ formation of intermediate reactive species
9605342, Sep 12 2012 ASM IP Holding B.V. Process gas management for an inductively-coupled plasma deposition reactor
9605343, Nov 13 2013 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming conformal carbon films, structures conformal carbon film, and system of forming same
9607837, Dec 21 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming silicon oxide cap layer for solid state diffusion process
9627221, Dec 28 2015 ASM IP Holding B.V. Continuous process incorporating atomic layer etching
9640416, Dec 26 2012 ASM IP Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
9647114, Aug 14 2015 ASM IP Holding B.V. Methods of forming highly p-type doped germanium tin films and structures and devices including the films
9657845, Oct 07 2014 ASM IP Holding B.V. Variable conductance gas distribution apparatus and method
9659799, Aug 28 2012 ASM IP Holding B.V.; ASM IP HOLDING B V Systems and methods for dynamic semiconductor process scheduling
9711345, Aug 25 2015 ASM IP HOLDING B V Method for forming aluminum nitride-based film by PEALD
9735024, Dec 28 2015 ASM IP Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
9754779, Feb 19 2016 ASM IP Holding B.V.; ASM IP HOLDING B V Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
9790595, Jul 12 2013 ASM IP Holding B.V. Method and system to reduce outgassing in a reaction chamber
9793115, Aug 14 2013 ASM IP Holding B.V. Structures and devices including germanium-tin films and methods of forming same
9793135, Jul 14 2016 ASM IP HOLDING B V Method of cyclic dry etching using etchant film
9793148, Jun 22 2011 ASM Japan K.K. Method for positioning wafers in multiple wafer transport
9812320, Jul 28 2016 ASM IP HOLDING B V Method and apparatus for filling a gap
9859151, Jul 08 2016 ASM IP HOLDING B V Selective film deposition method to form air gaps
9887082, Jul 28 2016 ASM IP HOLDING B V Method and apparatus for filling a gap
9890456, Aug 21 2014 ASM IP Holding B.V. Method and system for in situ formation of gas-phase compounds
9891521, Nov 19 2014 ASM IP Holding B.V.; ASM IP HOLDING B V Method for depositing thin film
9892908, Oct 28 2011 ASM IP HOLDING B V Process feed management for semiconductor substrate processing
9899291, Jul 13 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Method for protecting layer by forming hydrocarbon-based extremely thin film
9899405, Dec 22 2014 ASM IP Holding B.V.; ASM IP HOLDING B V Semiconductor device and manufacturing method thereof
9905420, Dec 01 2015 ASM IP HOLDING B V Methods of forming silicon germanium tin films and structures and devices including the films
9909214, Oct 15 2015 ASM IP Holding B.V.; ASM IP HOLDING B V Method for depositing dielectric film in trenches by PEALD
9916980, Dec 15 2016 ASM IP HOLDING B V Method of forming a structure on a substrate
9960072, Sep 29 2015 ASM IP Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
D830981, Apr 07 2017 ASM IP HOLDING B V ; ASM IP Holding B.V. Susceptor for semiconductor substrate processing apparatus
D880437, Feb 01 2018 ASM IP Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
D900036, Aug 24 2017 ASM IP Holding B.V.; ASM IP HOLDING B V Heater electrical connector and adapter
D903477, Jan 24 2018 ASM IP HOLDING B V Metal clamp
D913980, Feb 01 2018 ASM IP Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
D922229, Jun 05 2019 ASM IP Holding B.V. Device for controlling a temperature of a gas supply unit
D930782, Aug 22 2019 ASM IP Holding B.V. Gas distributor
D931978, Jun 27 2019 ASM IP Holding B.V. Showerhead vacuum transport
D935572, May 24 2019 ASM IP Holding B.V.; ASM IP HOLDING B V Gas channel plate
D940837, Aug 22 2019 ASM IP Holding B.V. Electrode
D944946, Jun 14 2019 ASM IP Holding B.V. Shower plate
D947913, May 17 2019 ASM IP Holding B.V.; ASM IP HOLDING B V Susceptor shaft
D948463, Oct 24 2018 ASM IP Holding B.V. Susceptor for semiconductor substrate supporting apparatus
D949319, Aug 22 2019 ASM IP Holding B.V. Exhaust duct
D965044, Aug 19 2019 ASM IP Holding B.V.; ASM IP HOLDING B V Susceptor shaft
D965524, Aug 19 2019 ASM IP Holding B.V. Susceptor support
D975665, May 17 2019 ASM IP Holding B.V. Susceptor shaft
D979506, Aug 22 2019 ASM IP Holding B.V. Insulator
D980813, May 11 2021 ASM IP HOLDING B V Gas flow control plate for substrate processing apparatus
D980814, May 11 2021 ASM IP HOLDING B V Gas distributor for substrate processing apparatus
D981973, May 11 2021 ASM IP HOLDING B V Reactor wall for substrate processing apparatus
ER3967,
ER4489,
ER6015,
ER6328,
ER8750,
Patent Priority Assignee Title
5286340, Sep 13 1991 UNIVERSITY OF PITTSBURGH OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION Process for controlling silicon etching by atomic hydrogen
5527733, Jul 27 1990 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
5532185, Mar 27 1991 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
5660682, Mar 14 1996 Bell Semiconductor, LLC Plasma clean with hydrogen gas
5851909, Aug 10 1990 Seiko Instruments Inc Method of producing semiconductor device using an adsorption layer
6413844, Jan 10 2001 ASM International N.V. Safe arsenic gas phase doping
6984552, Dec 07 2000 Sony Corporation Method for doping semiconductor layer, method for producing thin film semiconductor element and thin film semiconductor element
20020072227,
20030077886,
20050181566,
20060214198,
20070117382,
20080274370,
20090184398,
//////
Executed onAssignorAssigneeConveyanceFrameReelDoc
Jul 29 2009Axcelis Technologies, Inc.(assignment on the face of the patent)
Jul 29 2009BERRY, IVAN L Axcelis Technologies, IncASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0230230654 pdf
Mar 12 2010Axcelis Technologies, IncSilicon Valley BankSECURITY AGREEMENT0242020494 pdf
Apr 25 2011Axcelis Technologies, IncSilicon Valley BankFIRST AMENDMENT TO SECURITY AGREEMENT0262500524 pdf
Jul 31 2020Axcelis Technologies, IncSILICON VALLEY BANK, AS ADMINISTRATIVE AGENTSECURITY INTEREST SEE DOCUMENT FOR DETAILS 0533750055 pdf
Apr 05 2023SILICON VALLEY BANK A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANYAxcelis Technologies, IncRELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0632700277 pdf
Date Maintenance Fee Events
May 26 2015M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
May 14 2019M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Jul 24 2023REM: Maintenance Fee Reminder Mailed.
Jan 08 2024EXP: Patent Expired for Failure to Pay Maintenance Fees.


Date Maintenance Schedule
Dec 06 20144 years fee payment window open
Jun 06 20156 months grace period start (w surcharge)
Dec 06 2015patent expiry (for year 4)
Dec 06 20172 years to revive unintentionally abandoned end. (for year 4)
Dec 06 20188 years fee payment window open
Jun 06 20196 months grace period start (w surcharge)
Dec 06 2019patent expiry (for year 8)
Dec 06 20212 years to revive unintentionally abandoned end. (for year 8)
Dec 06 202212 years fee payment window open
Jun 06 20236 months grace period start (w surcharge)
Dec 06 2023patent expiry (for year 12)
Dec 06 20252 years to revive unintentionally abandoned end. (for year 12)