Method and apparatus for spatially optimizing the arrangement of surface mount pads on a ball grid array package. An array containing t surface mount pads with a diameter less than or equal to 0.4 millimeter is arranged in an array of rows and columns less than or equal to 0.5 millimeters center-to-center. The array of pads is subdivided into N groups of pads respectively numbered Gx (for X from 1 to N), each group containing px pads (for X from 1 to N). Each pad in each group is located so as to maximize the number of empty spaces Sz that are adjacent to each pad, where Sz=(Gx−1). The number of fanout possibilities for each group (px*Sz) is calculated, and then the total number of fanout possibilities, fp, is calculated using the function Σ1N (px*Sz). The resulting spatially optimized pattern has a quality score, fp/t, that is equal to or greater than 2.
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1. A spatially optimized pattern for surface mount pads on a ball grid array package, comprising:
an array of surface mount pads arranged in rows and columns, and spaced less than or equal to 0.5 millimeters measured center-to-center, the array comprising t pads divided into N groups of pads, where t and N are positive integers;
each group of pads consecutively numbered Gx where 1≦X≧N;
each pad in each consecutively numbered group Gx having Sz adjacent empty spaces, where Sz=(Gx−1);
a number of pads px in each of groups Gx equivalent to the total number of pads having the same quantity Sz of adjacent empty spaces, where 0≦X≧T;
each of consecutively numbered groups Gx having (px*Sz) fanout possibilities; a total number of fanout possibilities, fp, equal to Σ1N (px*Sz);
wherein the spatially optimized pattern has a quality score equal to fp/t; and wherein the quality score is greater than or equal to 2.0;
wherein a total area A of the surface mount pads is A=T*(π*(pad diameter/2)2) and wherein the A/(the area of the bottom surface of the ball grid array) is greater than 0.3.
2. A spatially optimized pattern for surface mount pads on a bottom surface of a ball grid array package, comprising:
an array of surface mount pads having a diameter less than or equal to 0.4 millimeter arranged in rows and columns on the bottom surface of the ball grid array, and spaced less than or equal to 0.5 millimeter center-to-center, the array comprising t pads divided into N groups of pads, where t and N are positive integers;
each group of pads consecutively numbered Gx where 1≦X≧N;
each pad in each consecutively numbered group Gx having Sz adjacent empty spaces, where Sz=(Gx−1);
a number of pads px in each of groups Gx equivalent to the total number of pads having the same quantity Sz of adjacent empty spaces, where 0≦X≧T;
each of consecutively numbered groups Gx having (px*Sz) fanout possibilities; a total number of fanout possibilities, fp, equal to Σ1N (px*Sz);
wherein the spatially optimized pattern has a quality score equal to fp/t;
wherein the quality score is greater than or equal to 2.0;
wherein a total area A of the array of surface mount pads is A=T*(π*(diameter/2)2);
and wherein A/(area of the bottom surface of the ball grid array package) is greater than 0.3.
3. A method for spatially optimizing surface mount pads on the bottom surface of a ball grid array package by arranging the pads so as to maximize the number of empty spaces adjacent to each pad, comprising:
arranging an array of t surface mount pads having a diameter less than or equal to 0.4 millimeter into rows and columns;
arranging the rows and columns to be less than or equal to 0.5 millimeters center-to-center;
arranging the pads in the array so as to maximize the number of empty spaces Sz adjacent each pad;
grouping the array into N groups of pads such that the members of each group have the same number of emit spaces Sz adjacent each pad, the N groups of pads groups consecutively numbered Gx where 1≦X≧N.
a number of pads px in each of groups Gx equivalent to the total number of pads having the same quantity Sz of adjacent empty spaces, where 0≦X≧T;
calculating the number of fanout possibilities (px*Sz) for each group Gx;
calculating the total number of fanout possibilities, fp, equal to Σ1N (px*Sz);
wherein the spatially optimized pattern has a quality score equal to fp/t, and the quality score is greater than or equal to 2.0;
wherein a total area of the surface mount pads A=T*(π*(diameter/2)2) and wherein A/(area of the bottom surface of the ball grid array) is greater than 0.3.
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The present invention relates generally to semiconductor packages, and more specifically, to ball grid array packages and a method to spatially optimize the surface mount pads on the package.
Integrated circuit packages of the ball grid array (BGA) type are well known. Conventional BGA packages provide a rectangular or square array of connections on the underside of a multi-layer substrate, utilizing a solder ball located at each connector location. The BGA package is attached to a printed circuit board by reflowing the solder balls to make connection to conductors at the surface of the printed circuit board. The BGA package provides the important advantage of being self-aligning, as the surface tension of the solder will tend to pull the BGA package into proper alignment with the corresponding conductors on the printed circuit board.
There are many benefits to using the BGA package, however its greatest asset—the ability to provide an extremely dense array of thousands of pads—also turns out to be a tremendous problem for designers. The increasing number of pads and decreasing pitch (the center-to-center distance between pads) of the BGA array pattern has outpaced the ability to effectively design these devices. Maintaining signal integrity at high levels and reducing fabrication costs are two important requirements that are at odds with each other. Reducing crosstalk is generally accomplished by increasing the space between conductors, which can increase layer count, increase package size, and thus, fabrication cost. Routing the signal traces on dense BGA packages requires more stringent design rules and more layers in the substrate. Fine pitch high pad count BGAs have thus become difficult, if not impossible to route. If the BGA package has too many pads in a dense array, the only way to minimize the number of layers in the substrate is to utilize all the available space with a pattern of fanouts and traces. Routing the device without an effective pattern wastes space, increases the package size, and requires more layers in the substrate, all undesirable outcomes. Medium to low pad count devices do not present a significant problem, and can be routed using conventional technology, but high pad count devices with a pitch less than 0.8 millimeter require a new paradigm for routing the traces out of the array. Without this, layer count becomes excessive, adversely affecting the fabrication cost and reliability of the BGA.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. In addition, dashed lines and some numbers are added in
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method and apparatus components related to arranging the surface mount pads on a ball grid array package in a spatially optimized pattern. Accordingly, the apparatus components and methods have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
A method and apparatus for spatially optimizing the arrangement of surface mount pads on a ball grid array package is described. Referring now to
Referring now to
Referring now to
TABLE 1
Group
Adjacent
Number
Fanout
number
spaces
of pads
Possibilities
(Gx)
(Sz)
(Px)
(Px * Sz)
G1
1
S0
0
P1
0
0
G2
2
S1
1
P2
4
4
G3
3
S2
2
P3
4
8
G4
4
S3
3
P4
6
18
G5
5
S4
4
P5
6
24
G6
6
S5
5
P6
7
35
G7
7
S6
6
P7
2
12
The number of fanout possibilities, that is, the number of empty adjacent spaces in the group, and therefore the number of possible directions or routes that a signal line can take from the pad 110 to a microvia, are then calculated for each group. Obviously, it is the goal of the designer to maximize the number of fanout possibilities in order to have the most flexibility in routing the signal lines. The number of fanout possibilities is calculated by multiplying the number of empty adjacent spaces by the number of members in that group, or (Px*Sz), as shown in TABLE 1. The total number of fanout possibilities is then calculated by summing up the fanout possibilities FP for each of the groups 1 through N,
Σ1N (Px*Sz). In this example, the total number of fanout possibilities FP for the spatially optimized array equals 101. A Quality Score that reflects the degree of spatial optimization of the array, is calculated by dividing the total fanout possibilities by the number of surface mount pads in the array, or FP/T. In this example, the Quality Score is 3.48. We find that a Quality Score greater than 2 generally indicates that the array has been optimized to a high degree, providing the designer with a wide variety of options in routing the various signal lines. Another measure of the quality of the optimization can be determined by measuring the percentage of the substrate surface area that is covered by surface mount pads. This ratio is determined by calculating the total area of the surface mount pads 110 in the array 100, and dividing this area by the area of the bottom side of the substrate 120. The area of each pad is calculated by standard mathematical formulae. Obviously, higher percentage of area covered indicates higher density arrays, and we find that our spatially optimization tool is most useful when applied to high density ball grid array packages having a coverage percentage greater than 30%.
Referring now to
TABLE 2
Group
Adjacent
Number
Fanout
number
spaces
of pads
Possibilities
(Gx)
(Sz)
(Px)
(Px * Sz)
G1
1
S0
0
P1
8
0
G2
2
S1
1
P2
44
44
G3
3
S2
2
P3
112
224
G4
4
S3
3
P4
64
192
G5
5
S4
4
P5
32
128
G6
6
S5
5
P6
24
120
In summary, a method to spatially optimize the layout of surface mount pads for a ball grid array package has been described, and the resulting layout and package have also been described. The array contains a finite number T of surface mount pads less than or equal to 0.4 millimeter in diameter arranged in rows and columns. The rows and columns are situated so that they are less than or equal to 0.5 millimeters center-to-center. Each pad is situated and located in the array to maximize the number of empty spaces that are adjacent to the pad, in order to maximize the number of fanout possibilities for that pad. The empty spaces are useful for routing signal lines away from the pad and for locating microvias to route the signal upward through the various layers of the substrate for interconnection to the integrated circuit on the opposite side of the array. The number of fanout possibilities for each group is calculated, and then the total number of fanout possibilities, FP, is calculated. The resulting spatially optimized pattern has a Quality Score, FP/T, that is equal to or greater than 2. The disclosed invention enables one to design fine pitch BGA packages (<0.4 mm pitch) such that the number of microvias is reduced compared to the prior art and a large number of the signal lines are routed on the top layer of the substrate. This simplifies board level interconnect and improves overall electrical performance of the BGA package by reducing interconnect length and associated inductances. It also improves the mechanical robustness of the package.
In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.
Swirbel, Thomas J., Watkins, Michael J., Underwood, Jeffrey A.
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Oct 23 2008 | WATKINS, MICHAEL J | Motorola, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 021743 | /0113 | |
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