A multiple time programmable non-volatile memory element and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The multiple time programmable non-volatile memory element includes a capacitor, an access transistor that is electrically coupled to the capacitor at a connection node, and a plurality of one time programmable non-volatile memory cells. Each of the plurality of one time programmable non-volatile memory cells is electrically coupled to the connection node and includes a select transistor that is electrically coupled to an antifuse element. The antifuse element is configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in logic state.
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1. A non-volatile memory, comprising:
a plurality of multiple time programmable non-volatile memory elements, each respective multiple time programmable non-volatile memory element including:
a capacitor;
an access transistor electrically coupled to the capacitor at a connection node; and
a plurality of one time programmable non-volatile memory cells corresponding in number to a number of times the respective multiple time programmable non-volatile memory element can be programmed to have a logic state that is either one of a first logic state and a second logic state that is logically opposite the first logic state, each of the plurality of one time programmable non-volatile memory cells being electrically coupled in parallel with one another to the connection node and including a select transistor that is electrically coupled to an antifuse element, the antifuse element being configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in the logic state of the respective multiple time programmable non-volatile memory element.
2. The non-volatile memory of
3. The multiple time programmable non-volatile memory element of
4. The multiple time programmable non-volatile memory element of
5. The multiple time programmable non-volatile memory element of
6. The multiple time programmable non-volatile memory element of
7. The multiple time programmable non-volatile memory element of
8. The multiple time programmable non-volatile memory element of
9. The multiple time programmable non-volatile memory element of
10. The multiple time programmable non-volatile memory element of
11. The multiple time programmable non-volatile memory element of
12. The multiple time programmable non-volatile memory element of
13. The multiple time programmable non-volatile memory element of
14. The multiple time programmable non-volatile memory element of
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This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application Ser. No. 61/244,791, entitled “MULTIPLE TIME PROGRAMMABLE NON-VOLATILE MEMORY ELEMENT,” filed on Sep. 25, 2009, which is herein incorporated by reference in its entirety. This application is related to U.S. application Ser. No. 12/887,956 entitled “NON-VOLATILE MEMORY ELEMENT INTEGRATABLE WITH STANDARD CMOS CIRCUITRY,” filed on Sep. 22, 2010, and to U.S. application Ser. No. 12/889,659, entitled “METHOD OF SENSING A PROGRAMMABLE NON-VOLATILE MEMORY ELEMENT,” filed on Sep. 24, 2010.
Embodiments of the present invention relate to non-volatile memories, and more particularly, to embedded memories for combination with other integrated circuitry.
The present invention provides a non-volatile memory cell and associated programming methods that allow for the integration of non-volatile memory with other CMOS integrated circuitry utilizing the standard CMOS processing used to manufacture the other CMOS integrated circuitry. The non-volatile cell structure and programming methods of the present invention, therefore, provide a desirable solution for embedded memory architectures.
In accordance with an aspect of the present invention, a multiple time programmable non-volatile memory element is provided. The multiple time programmable non-volatile memory element comprises a capacitor, an access transistor that is electrically coupled to the capacitor at a connection node, and a plurality of one time programmable non-volatile memory cells. Each of the plurality of one time programmable non-volatile memory cells is electrically coupled to the connection node and includes a select transistor that is electrically coupled to an antifuse element. The antifuse element is configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in logic state.
The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:
This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” “having,” “containing,” “involving,” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
The present invention provides non-volatile memory cell and associated programming methods that allow for the integration of non-volatile memory with other CMOS integrated circuitry utilizing the standard CMOS processing used to manufacture the other CMOS integrated circuitry. Thus, the non-volatile cell structure and programming methods, therefore, provide a desirable solution for embedded memory architectures.
It is shown in
The non-volatile memory element 200 advantageously utilizes an antifuse element 206 that can be fabricated in standard CMOS processes without requiring special processing. This antifuse element 206 can be formed, for example, by using a standard gate oxide dielectric layer as an insulator. This insulator can then be made to become conductive by electrical means. For example, insulating layers, such as silicon dioxide (SiO2), can have a voltage applied across them, and the insulator will not permit current to flow. If a sufficiently high field is applied, however, the oxide will breakdown and cause a fast discharge of the voltage to across the oxide. This rapid discharge usually results in a change in the oxide or damage to the oxide that eliminates its insulating characteristic, so that the oxide will now conduct electrical current. This change in resistivity or conductive state can be used to represent the logic state of the antifuse element.
To cause the dielectric layer to become conductive, a voltage of sufficient magnitude must typically be applied across the dielectric layer. Oxides will generally become conductive with exposure to high voltages where stress is induced and charge is conducted through the oxides. Thick oxides generally behave in a manner that is typical of insulators, that is, they will tolerate an increasing field until a certain high potential, and then the oxide will break down. Below this breakdown, there is only a small current (called Fowler-Nordheim tunneling). Then, at a certain voltage level, the current will rise sharply, and significant charge will flow through the oxide. If the current is large enough, damage will occur to the oxide, and the oxide will become conductive. In some cases, one breakdown event may not be enough to cause the oxide to change permanently to a conductive state. Rather, a series of breakdown events may be needed to cause the oxide to become conductive. In thinner oxides, there can be other modes of conduction, such as direct tunneling, and these currents may prevent the easy build up of voltage across the oxide. As the voltage increases, the current through the oxide will increase, and likewise the current will decrease if the voltage is decreased. These oxides must typically conduct a significant amount of charge before the insulating characteristics are lost. This charge to breakdown (Qbd) must be driven through the insulator to cause it to change states, from an insulator to a conductor.
In particular, in the embodiment of
In this write operation, therefore, the disclosed memory cell structure of
To read the state of the antifuse element M1, a voltage is applied across the antifuse element and then read circuitry will detect if there is a current flow through the dielectric layer of the antifuse element. For example, NODE 2 can be driven to an initial voltage, such as 1 volt, and NODE 1 can be driven to a positive voltage, such as Vdd. If the dielectric layer within the antifuse element M1 is conducting, a current will flow from NODE 2, through transistor M2 to NODE 4 and then to NODE 5 and/or NODE 6 through the dielectric layer of antifuse element M1. If the dielectric layer within the antifuse element M1 is not conducting, then there would be no current flowing from NODE 2 to NODE 5 and/or NODE 6 of the antifuse element M1. The current flow determination and the no current flow state are then used to determine the resistivity state of the antifuse element and thereby to determine the logic state of the non-volatile memory cell 200. For example, dielectric layer breakdown and associated current flow could define a logic “1,” and no current flow could define a logic “0.” In the embodiment of
In an alternative embodiment, the transistor M2 is used as the access transistor, but is connected to NODES 5 and 6. In this alternative embodiment, NODES 5 and 6 of the antifuse element are connected together and to NODE 4, and NODE 2 is coupled to NODES 5 and 6 through the access transistor M2. Details on the manner in which an antifuse element may be implemented in CMOS technologies are described in co-pending application Ser. No. 12/887,956, filed Sep. 22, 2010 and entitled “NON-VOLATILE MEMORY ELEMENT INTEGRATABLE WITH STANDARD CMOS CIRCUITRY,” which is incorporated herein by reference in its entirety.
As indicated above with respect to
In particular, in the embodiment of
The present invention may be used to program multiple elements per bit to add redundancy or increase the breakdown conduction for higher reliability applications. This may be accomplished by selecting one or more of the n-BIT select signals during the memory operations. In particular, in the embodiment of
Advantageously, therefore, the benefits of the multiple time programmable non-volatile embedded memory cell structures described herein include: (1) a programming voltage generated internally to the memory cell, (2) no high voltage transistors needed for routing the high programming voltage to the memory cell, (3) unique selection of the memory cell is possible through the use of NODE 1 and NODE 2, (4) one or more times programmable memory cell, (5) capability to increase the breakdown conduction for higher reliability applications, and/or (5) no special structures, special processing techniques and/or process modifications are required to integrate the non-volatile memory cell structure with other CMOS circuitry.
Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. For example, equivalent elements may be substituted for those illustrated and described herein and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.
Fiscus, Timothy, Novosel, David, Novosel, Walter, Sieg, Ethan, Novosel, legal representative, Elaine
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