The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.
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18. A transistor, comprising:
an inverted-T structure comprising a first portion formed of a first semiconductor material selected to provide high mobility to a first carrier type and a second portion abutting the first portion, formed of a second semiconductor material, wherein the second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type;
first and second channel regions formed in the first and second portions, respectively; and
a gate formed over the inverted-T structure.
1. A transistor, comprising:
a first layer formed of a first semiconductor material over a buried oxide layer, the first semiconductor material selected to provide high mobility to a first carrier type;
a second layer formed of a second semiconductor material abutting the first layer, the second semiconductor material selected to provide high mobility to a second carrier type opposite the first carrier type, and
the second layer comprising at least one feature formed in the second layer such that said at least one feature in the second layer forms an inverted-T shape with a portion of the first layer, and wherein the portion of the first layer abuts said at least one feature;
a channel is formed in said at least one feature in the second layer and in the portion of the first layer, and
a gate formed over the inverted structure.
12. A transistor, comprising:
a first layer formed of a first semiconductor material over a buried oxide layer, the first semiconductor material selected to provide a first mobility to a first carrier type; and
a second layer formed of a second semiconductor material abutting the first layer, the second semiconductor material selected to provide a second mobility to a second carrier type that is opposite to the first carrier type, and
the second layer comprising at least one feature formed in the second layer such that said at least one feature in the second layer is in contact with a portion of the first layer to form an inverted-T shape with the portion of the first layer forming the base of the inverted-T shape;
a channel formed in said at least one feature in the second layer and the portion of the first layer, and
a gate formed over the inverted-T structure.
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1. Field of the Invention
This invention relates generally to semiconductor processing, and, more particularly, to forming a hetero-structured, inverted-T field effect transistor.
2. Description of the Related Art
The constant drive to increase the density of semiconductor devices that can be formed on a wafer and the speed at which these devices operate has led to many modifications in the structure of conventional semiconductor devices. For example, as development goals have approached the 22 nm node, attempts to maintain a conventional planar device scaling have encountered roadblocks including inadequate control of the channel region by the gate electrode, which may lead to short channel effects. Multi-directional control of the channel may allow increased immunity to short channel effects such as sub threshold slopes, drain induced barrier leakage, and the like. Many semiconductor devices may therefore be formed using multigate field effect transistors (FETs). One example of a multi-gate FET incorporates a gate structure formed from an ultrathin body (UTB) that is turned on end relative to conventional planar gate structures (i.e., the UTB gate structure is perpendicular to the substrate). These devices are conventionally referred to as Fin-FETs because of the fin-like shape of the structures that connect the source and drain regions of the Fin-FETs to the gate structure. The Fin-FET devices may offer a means of packing more current (and consequently more speed) into each unit area of a chip while keeping the processing, materials, and circuit design factors relatively consistent with previous technology nodes.
The fin structures in conventional Fin-FETs may be configured to provide relatively high drive currents for the CMOS devices that incorporate the Fin-FETs. However, the conventional fin structures have a single orientation and are formed of a single material. Consequently, conventional fin structures can only be optimized to provide high drive currents for a single type of CMOS device, i.e. the fin structures can be optimized for either a PMOS device where high hole mobility is desired or an NMOS device where high electron mobility is desired. Most circuit designs include large numbers of both PMOS and NMOS devices. The process flows used to form the circuit may be optimized for one type of device, but this may also result in a less than optimal process flow for the other type of device.
The subject matter described herein is directed to addressing the effects of one or more of the problems set forth above.
The following presents a simplified summary of the subject matter described herein in order to provide a basic understanding of some aspects of the present invention. This summary is not an exhaustive overview of the present subject matter described herein. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
In one embodiment, a method is provided for forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.
In another embodiment, a transistor is provided. The transistor includes a first layer formed of a first semiconductor material over a buried oxide layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The transistor also includes a second layer formed of a second semiconductor material adjacent the first layer. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The second layer also includes at least one feature formed in the second layer by etching the second layer through a first masking layer such that each feature in the second layer forms an inverted-T shape with a portion of the first layer.
The present subject matter may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
Illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions should be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the subject matter described herein. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Using the strained, tensile or compressive, silicon-on-insulator layer 305 may allow mobility of electrons and/or holes in the hetero-structured, inverted-T fin structures to be controlled, modified, and/or increased. For example, straining the silicon-on-insulator layer 305 may modify the conduction and/or valence band structure of the strained silicon-on-insulator layer 305 to increase the mobility of electrons and/or holes. Furthermore, the strained silicon lattice in the strained silicon-on-insulator layer 305 may also aid in growing high-quality epitaxial layers (e.g., the germanium layers discussed below) by reducing the possible lattice mismatch defects. Techniques for straining silicon-on-insulator layer 305 to control mobility and/or reduce lattice mismatch defects, as well as to achieve other ends, are known in the art and in the interest of clarity will not be discussed further herein.
As shown in
Although silicon and germanium are used to form the first and second layers 305, 315 in the illustrated embodiment, persons of ordinary skill in the art having benefit of the present disclosure should appreciate that the present invention is not limited to forming the first and second layers 305, 315 from these materials. In alternative embodiments, other combinations of semiconductor materials may be selected so that one of the layers 305, 315 provides relatively high electron mobility and the other layer 305, 315 provides relatively high hole mobility. Exemplary combinations of materials that may be used to form the first and second layers 305, 315 include using germanium to form the first layer 305 and silicon to form the second layer 315, using GaAs to form the first layer 305 and germanium to form the second layer 315, and using silicon to form the first layer 305 and GaAs to form the second layer 315.
As shown in
The insulator layer 320 and the second layer 315 may then be etched using the patterned masking layer 325 as a mask, as shown in
At this point in the processing, the fin-shaped structures 330 and the first layer 305 form a hetero-structured, inverted-T fin structure that may be used for a contiguous device such as a contiguous ultra-thin body (UTB) device. For example, the height of the fin-shaped structures 330 may be substantially in the range of 15-90 nm and the thickness of the first layer 305 may be substantially in the range 1-60 nm. The orientation of the semiconductor materials may be chosen to provide the highest mobility of the associated carrier, e.g. holes or electrons. In one embodiment, the first semiconductor material is chosen to have a (100) orientation and so the conduction planes 332 of the first layer 305 have a planar (100) geometry and the conduction planes of the side wall surfaces 334 of the second layer of the fin-shaped structures 330 have a planar (110) geometry. Alternatively, a different orientation of the first semiconductor material may be chosen, e.g. a (110) orientation, to ensure higher carrier mobility, e.g. a higher hole mobility. In this case the second semiconductor material would be formed with another orientation, e.g. a (100) orientation.
In one alternative embodiment, a multiple gate UTB device may be formed by patterning the first layer 305. In the embodiment shown in
The fin-structures 405 shown in the illustrated embodiment include a base 425 that is formed of silicon and a fin 430 that is formed of germanium. In one embodiment, the fin structures 405 may be formed according to the process shown in
The transistor 400 may also be modified in other ways. For example, the channel regions formed by the base 425 and the fin 430 may be intrinsically doped or can be doped, e.g., using ion implantation and annealing techniques. For another example, extensions may be formed using extension implants or by using under lap of dopants from the source region 410 and/or the drain region 415. For yet another example, parasitic resistances may be reduced by a selective epitaxial growth of germanium and/or silicon in regions outside of spacers formed in the transistor 400.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Adhikari, Hemant, Harris, Rusty
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Nov 29 2007 | ADHIKARI, HEMANT | Advanced Micro Devices, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020357 | /0912 | |
Nov 29 2007 | HARRIS, RUSTY | Advanced Micro Devices, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020357 | /0912 | |
Nov 30 2007 | Advanced Micro Devices, Inc. | (assignment on the face of the patent) | / |
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