The display device including pixels has formed therein at least two drive blocks each made up of pixel rows. Each of the pixels includes: a drive transistor; a capacitor element, a luminescence element; a first switching transistor which causes conduction between the gate of the drive transistor and a fixed potential line; and a second switching transistor which causes conduction between the source of the drive transistor and the capacitor element. Each of the pixels further includes a third switching transistor which connects a pixel in a k-th drive block and a first signal line or a fourth switching transistor which connects a pixel in a (k+1)-th drive block and a second signal line.
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1. A display device including pixels arranged in rows and columns, the display device comprising:
a first signal line and a second signal line that are disposed in each of the columns, for supplying the pixels in the corresponding column with a signal voltage that determines luminance of the pixels;
a first power source line and a second power source line;
a scanning line disposed in each of the rows; and
a control line disposed in each of the rows,
wherein the pixels compose at least two drive blocks each of which includes at least two of the rows,
each of the pixels includes:
a luminescence element that includes terminals, one of the terminals being connected to the second power source line, and the luminescence element generating photons according to a flow of a signal current corresponding to the signal voltage;
a drive transistor that includes a gate, a source, and a drain, one of the source and the drain being connected to the first power source line, the other of the source and the drain being connected to the other of the terminals of the luminescence element, and the drive transistor converting the signal voltage applied between the gate and the source of the drive transistor into the signal current;
a capacitor element that includes terminals, one of the terminals being connected to the gate of the drive transistor;
a first switching transistor that includes a gate connected to the scanning line, one of a source and a drain connected to the one of the terminals of the capacitor element, and the other of the source and the drain connected to a fixed potential line; and
a second switching transistor that includes a gate connected to the control line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the source of the drive transistor,
each of the pixels in a k-th drive block of the drive blocks further includes a third switching transistor that includes a gate connected to the scanning line, one of a source and drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the first signal line, k being a positive integer, and
each of the pixels in a (k+1)-th drive block of the drive blocks further includes a fourth switching transistor that includes a gate connected to the scanning line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the second signal line.
6. A method of driving a display device in which pixels are arranged in rows and columns and compose at least two drive blocks each of which includes at least two of the rows, each of the pixels including a drive transistor and a luminescence element, the drive transistor converting one of a luminance signal voltage and a reference voltage supplied by one of signal lines into a signal current corresponding to the one of a luminance signal voltage and the reference voltage, the luminescence element generating photons according to a flow of the signal current, the method comprising:
resetting a gate and a source of the drive transistor of each of the pixels in a k-th drive block of the drive blocks simultaneously, k being a positive integer;
storing a voltage corresponding to the luminance signal voltage, in a pixel row-sequence, in a capacitor element that includes terminals one which is connected to the gate of the drive transistor of each of the pixels in a k-th drive block of the drive blocks, after the resetting in the k-th drive block;
resetting a gate and a source of the drive transistor of each of the pixels in a (k+1)-th drive block of the drive blocks simultaneously, after the resetting in the k-th drive block;
wherein the resetting in the k-th drive block includes:
simultaneously applying a fixed voltage from the fixed potential line to the gate of the drive transistor of each of the pixels in the k-th drive block and (ii) a reference voltage from the first signal line to the source of the drive transistor, the first signal line being disposed in each of the columns; and
simultaneously causing non-conduction between the fixed potential line and the gate of the transistor of each of the pixels in the k-th drive block and simultaneously causing non-conduction between the first signal line and the source of the drive transistor of each of the pixels in the k-th drive block, and
the resetting in the (k+1)-th drive block includes:
simultaneously applying the fixed voltage from the fixed potential line to the gate of the drive transistor of each of the pixels in the (k+1)-th drive block and (ii) the reference voltage from a second signal line to the source of the drive transistor, the second signal line being disposed in each of the columns; and
simultaneously causing non-conduction between the fixed potential line and the gate of the transistor of each of the pixels in the (k+1)-th drive block and simultaneously causing non-conduction between the second signal line and the source of the drive transistor of each of the pixels in the (k+1)-th drive block.
2. The display device according to
wherein the control line is connected to the pixels in a same one of the drive blocks and not connected to the pixels in different ones of the drive blocks.
3. The display device according to
a drive circuit which drives the pixels by controlling the first signal line, the second signal line, the control line, and the scanning line,
wherein the drive circuit:
simultaneously applies (i) a fixed voltage from the fixed potential line to the gate of the drive transistor of each of the pixels in the k-th drive block and (ii) a reference voltage from the first signal line to the source of the drive transistor, by simultaneously applying voltage, from the scanning line, which turn ON the first switching transistor and the third switching transistor of each of the pixels in the k-th drive block, in a state in which the corresponding second switching transistor is ON;
simultaneously causes non-conduction between the fixed potential line and the gate of the transistor of each of the pixels in the k-th drive block and simultaneously causes non-conduction between the first signal line and the source of the drive transistor of each of the pixels in the k-th drive block, by simultaneously applying voltages, from the scanning line, which turn OFF the first switching transistor and the third switching transistor of each of the pixels in the k-th drive block, in a state in which the corresponding second switching transistor is ON;
simultaneously applies (i) the fixed voltage from the fixed potential line to the gate of the drive transistor of each of the pixels in the (k+1)-th drive block and (ii) the reference voltage from the second signal line to the source of the drive transistor, by simultaneously applying voltages, from the scanning line, which turn ON the first switching transistor and the fourth switching transistor of each of the pixels in the (k+1)-th drive block, in a state in which the corresponding second switching transistor is ON; and
simultaneously causes non-conduction between the fixed potential line and the gate of the transistor of each of the pixels in the (k+1)-th drive block and simultaneously causes non-conduction between the second signal line and the source of the drive transistor of each of the pixels in the (k+1)-th drive block, by simultaneously applying voltages, from the scanning line, which turn OFF the first switching transistor and the fourth switching transistor of each of the pixels in the (k+1)-th drive block, in a state in which the corresponding second switching transistor is ON.
4. The display device according to
wherein the signal voltage includes a luminance signal voltage for causing the luminescence element to generate photons and a reference voltage for resetting the drive transistor,
the display device further comprises:
a signal line drive circuit that outputs the signal voltage to the first signal line and the second signal line; and
a timing control circuit that controls the timing at which the signal line drive circuit outputs the signal voltage, and
the timing control circuit (i) causes the signal line drive circuit to output the reference voltage to the second signal line when the signal line drive circuit is outputting the luminance signal voltage to the first signal line, and (ii) causes the signal line drive circuit to output the reference voltage to the first signal line when the signal line drive circuit is outputting the luminance signal voltage to the second signal line.
5. The display device according to
wherein, where a period of time for refreshing all of the pixels is Tf, and a total number of the drive blocks is N, a resetting period for resetting the drive transistor is at most Tf/N.
7. The method according to
wherein each of the pixels includes terminals, one of the terminals being connected to a first power source line and the other of the terminals being connected to the source of the drive transistor,
in the resetting in the k-th drive block, the fixed voltage from the fixed potential line and the reference voltage from the first signal line, respectively, are simultaneously applied to the gate and the source of the drive transistor of each of the pixels in the k-th drive block by causing conduction between a first switching transistor and a third switching transistor, in a state in which conduction is caused in a second switching transistor, the first switching transistor including a gate connected to a scanning line disposed in each of the rows, one of a source and a drain connected to the gate of the drive transistor, and the other of the source and the drain connected to the fixed potential line, the third switching transistor including a gate connected to the scanning line, one of a source and drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the first signal line, and the second switching transistor including a gate connected to a control line disposed in each of the rows, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the source of the drive transistor,
in the resetting in the (k+1)-th drive block, the fixed voltage and the reference voltage from the second signal line, respectively, are simultaneously applied to the gate and the source of the drive transistor of each of the pixels in the (k+1)-th drive block by causing conduction between the first switching transistor and a fourth switching transistor, in a state in which conduction is caused in the second switching transistor, the fourth switching transistor including a gate connected to the scanning line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the second signal line,
in simultaneously causing non-conduction in the k-th drive block, non-conduction is simultaneously caused between the fixed potential line and the gate of the transistor of each of the pixels in the k-th drive block and non-conduction is simultaneously caused between the first signal line and the source of the drive transistor of each of the pixels in the k-th drive block, by causing non-conduction of the first switching transistor and the third switching transistor, in a state in which conduction is caused in the second switching transistor, in simultaneously causing non-conduction in the (k+1)-th drive block, non-conduction is simultaneously caused between the fixed potential line and the gate of the transistor of each of the pixels in the (k+1)-th drive block and non-conduction is simultaneously caused between the second signal line and the source of the drive transistor of each of the pixels in the (k+1)-th drive block, by causing non-conduction of the first switching transistor and the fourth switching transistor, in a state in which conduction is caused in the second switching transistor, and
in the storing of the voltage in the k-th drive block, the luminance signal voltage from the first signal line is applied to the other one of the terminals of the capacitor element by causing conduction of the third switching transistor in a state in which non-conduction is caused in the second switching transistor.
8. The method according to
generating the photons by simultaneously supplying the signal current, as a drain current of the drive transistor, to the luminescence element of each of the pixels in the k-th drive block, after the storing of the voltage in the k-th drive block.
9. The method according to
storing a voltage corresponding to the luminance signal voltage, in a pixel row-sequence, in a capacitor element that includes terminals one of which is connected to the gate of the drive transistor of each of the pixels in a (k+1)-th drive block of the drive blocks, after the resetting in the (k+1)-th drive block; and
generating the photons by simultaneously supplying the signal current, as the drain current of the drive transistor, to the luminescence element of each of the pixels in the (k+1)-th drive block, after the storing of the voltage in the (k+1)-th drive block.
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This is a continuation application of PCT Patent Application No. PCT/JP2010/005456 filed on Sep. 6, 2010, designating the United States of America. The entire disclosure of the above-identified application, including the specification, drawings and claims are incorporated herein by reference in its entirety.
(1) Field of the Invention
The present invention relates to display devices and methods of driving the same, and particularly to a display device using current-driven luminescence elements, and a method of driving the same.
(2) Description of the Related Art
Display devices using organic electroluminescence (EL) elements are well-known as display devices using current-driven luminescence elements. An organic EL display device using such self-luminous organic EL elements does not require backlights needed in a liquid crystal display device and is best suited for increasing device thinness. Furthermore, since viewing angle is not restricted, practical application as a next-generation display device is expected. Furthermore, the organic EL elements used in the organic EL display device are different from liquid crystal cells which are controlled according to the voltage applied thereto, in that the luminance of the respective luminescence elements is controlled according to the value of the current flowing thereto.
In the organic EL display device, the organic EL elements included in the pixels are normally arranged in rows and columns. In an organic EL display referred to as a passive-matrix organic EL display, an organic EL element is provided at each crosspoint between row electrodes (scanning lines) and column electrodes (data lines), and such organic EL elements are driven by applying a voltage equivalent to a data signal, between a selected row electrode and the column electrodes.
On the other hand, in an organic EL display device referred to as an active-matrix organic EL display device, a switching thin film transistor (TFT) is provided in each crosspoint between scanning lines and data lines, the gate of a drive element is connected to the switching TFT, the switching TFT is turned ON through a selected scanning line so as to input a data signal from a signal line to the drive element, and an organic EL element is driven by such drive element.
Unlike in the passive-matrix organic EL display device where, only during the period in which each of the row electrodes (scanning lines) is selected, does the organic EL element connected to the selected row electrode generate photons, in the active-matrix organic EL display device, it is possible to cause the organic EL element to generate photons until a subsequent scan (selection), and thus a reduction in display luminance is not incurred even when the duty ratio increases. Therefore, the active-matrix organic EL display device can be driven with low voltage and thus allows for reduced power consumption. However, in the active-matrix organic EL display device, due to variation in the characteristics of the drive transistors, the luminance of the organic EL elements are different among the respective pixels even when the same data signal is supplied, and thus there is the disadvantage of the occurrence of luminance unevenness.
In response to this problem, for example, Japanese Unexamined Patent Application Publication No. 2008-122633 (Patent Reference 1) discloses a method of compensating for the variation of characteristics for each pixel using a simple pixel circuit, as a method of compensating for the luminance unevenness caused by the variation in the characteristics of the drive transistors.
The scanning line drive unit 504 performs line-sequential scanning of the pixels 501 on a per row basis, by sequentially supplying control signals on a horizontal cycle (1 H) to each of the scanning lines 701 to 70m. The power supply line drive unit 505 supplies, to each of the power supply lines 801 to 80m, power source voltage that switches between a first voltage and a second voltage, in accordance with the line-sequential scanning. The signal selector 503 supplies, to the signal lines 601 to 60n that are in columns, a reference voltage and a luminance signal voltage which serves as an image signal, switching between the two voltages in accordance with the line-sequential scanning.
Here, two each of the respective signal lines 601 to 60n in columns are disposed per column; one of the signal lines supplies the reference voltage and the signal voltage to the pixels 501 in an odd row, and the other of the signal lines supplies the reference voltage and the signal voltage to the pixels 501 in an even row.
In the above-described configuration, the power supply line drive unit 505 switches the voltage of the power supply line 801, from a first voltage (high-voltage) to a second voltage (low-voltage), when the voltage of the signal line 601 is the reference voltage. With this, the pixels in the first row stop generating photons. Likewise, when the voltage of the signal line 601 is the reference voltage, the scanning line drive unit 504 sets the voltage of the scanning line 701 to an “H” level and causes the switching transistor 511 to be in a conductive state so as to apply the reference voltage to the gate of the drive transistor 512 and set the source of the drive transistor 512 to the second voltage. With the above-described operation, the resetting operation of the drive transistor 512 is executed. Here, the resetting operation is the operation of clearing the gate potential and the source potential of the drive transistor in the preceding luminescence production (photon generation) period, and resetting the gate potential and the source potential to the initial state. With the above-described resetting operation, preparation for the correction of a threshold voltage Vth is completed. Next, in the correction period before the voltage of the signal line 601 switches from the reference voltage to the signal voltage, the power supply line drive unit 505 switches the voltage of the power supply line 801, from the second voltage to the first voltage, and causes a voltage equivalent to the threshold voltage Vth of the drive transistor 512 to be stored in the storing capacitor 513. Next, the power supply line drive unit 505 sets the voltage of the switching transistor 511 to the “H” level and causes the signal voltage to be held in the storing capacitor 513. Specifically, the signal voltage is added to the previously stored voltage equivalent to the threshold voltage Vth of the drive transistor 512, and stored into the storing capacitor 513. Then, the drive transistor 512 receives a supply of current from the power supply line 801 to which the first voltage is being applied, and supplies the luminescence element 514 with a drive current corresponding to the held voltage.
In the above-described operation, the period of time during which the reference voltage is applied to the respective signal lines is prolonged through the placement of two of the signal lines 601 in every column. This secures the resetting period of the drive transistor 512 and the correction period for storing the voltage equivalent to the threshold voltage Vth in the storing capacitor 513.
In this manner, in the conventional image display device disclosed in Patent Reference 1, even when there is a variation in the threshold voltage Vth of the drive transistor 512 for each pixel, by ensuring a sufficient resetting period and threshold voltage correction period, the variation is canceled on a pixel basis, and unevenness in the luminance of an image is inhibited.
However, in the conventional image display device disclosed in Patent Reference 1, there is frequent turning ON and OFF of the signal level of the scanning lines and power supply lines provided to each of the pixel rows. For example, the resetting period and the threshold voltage correction period need to be set for each of the pixel rows. Furthermore, when sampling luminance signal voltage from a signal line via a switching transistor, luminescence production periods need to be provided successively. Therefore, the resetting period, the threshold voltage correction timing, and photon generation timing for each pixel row need to be set. As such, since the number of rows increases with an increase in the area of a display panel, the signals outputted from each drive circuit increases and the frequency for the signal switching thereof rises, and the signal output load of the scanning line drive circuit and the power supply line drive circuit increases.
Furthermore, in the conventional image display device disclosed in Patent Reference 1, the resetting period and the correction period for the threshold voltage Vth of the drive transistor is under 2 H, and thus there is a limitation for a display device in which high-precision correction is required. In particular, since the current driving operation of the drive transistor includes hysteresis, it is necessary to ensure a sufficient resetting period and precisely initialize the gate potential and the source potential. When the photon generation operation is executed while the resetting period is still insufficient, the fluctuation histories of the threshold voltage and the mobility for each of the pixels remain for a long time, and thus image luminance unevenness is not sufficiently suppressed, and display deterioration such as afterimages cannot be suppressed.
In view of the aforementioned problem, the present invention has as an object to provide a display device having reduced drive circuit output load and improved display quality due to high-precision resetting operation.
In order to achieve the aforementioned object, the display device according to an aspect of the present invention is a display device including pixels arranged in rows and columns, the display device including: a first signal line and a second signal line that are disposed in each of the columns, for supplying the pixels in the corresponding column with a signal voltage that determines luminance of the pixels; a first power source line and a second power source line; a scanning line disposed in each of the rows; and a control line disposed in each of the rows, wherein the pixels compose at least two drive blocks each of which includes at least two of the rows, each of the pixels includes: a luminescence element that includes terminals, one of the terminals being connected to the second power source line, and the luminescence element generating photons according to a flow of a signal current corresponding to the signal voltage; a drive transistor that includes a gate, a source, and a drain, one of the source and the drain being connected to the first power source line, the other of the source and the drain being connected to the other of the terminals of the luminescence element, and the drive transistor converting the signal voltage applied between the gate and the source of the drive transistor into the signal current; a capacitor element that includes terminals, one of the terminals being connected to the gate of the drive transistor; a first switching transistor that includes a gate connected to the scanning line, one of a source and a drain connected to the one of the terminals of the capacitor element, and the other of the source and the drain connected to a fixed potential line; and a second switching transistor that includes a gate connected to the control line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the source of the drive transistor, each of the pixels in a k-th drive block of the drive blocks further includes a third switching transistor that includes a gate connected to the scanning line, one of a source and drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the first signal line, k being a positive integer, and each of the pixels in a (k+1)-th drive block of the drive blocks further includes a fourth switching transistor that includes a gate connected to the scanning line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the second signal line.
According to the display device and the method of driving the same according to the present invention, the drive transistor resetting periods as well as the timings thereof can be made uniform within a drive block, and thus the number of times that the signal level is switched from ON to OFF and from OFF to ON can be reduced and thus reducing the load on the drive circuit which drives the respective circuits of the pixels. In addition, through the above-described forming of drive blocks and the two signal lines provided for each pixel column, the drive transistor resetting period can take a large part of a 1-frame period, and thus a highly precise drive current flows to the luminescence elements and image display quality improves.
These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the present invention. In the Drawings:
In order to achieve the aforementioned object, the display device according to an aspect of the present invention is a display device including pixels arranged in rows and columns, the display device including: a first signal line and a second signal line that are disposed in each of the columns, for supplying the pixels in the corresponding column with a signal voltage that determines luminance of the pixels; a first power source line and a second power source line; a scanning line disposed in each of the rows; and a control line disposed in each of the rows, wherein the pixels compose at least two drive blocks each of which includes at least two of the rows, each of the pixels includes: a luminescence element that includes terminals, one of the terminals being connected to the second power source line, and the luminescence element generating photons according to a flow of a signal current corresponding to the signal voltage; a drive transistor that includes a gate, a source, and a drain, one of the source and the drain being connected to the first power source line, the other of the source and the drain being connected to the other of the terminals of the luminescence element, and the drive transistor converting the signal voltage applied between the gate and the source of the drive transistor into the signal current; a capacitor element that includes terminals, one of the terminals being connected to the gate of the drive transistor; a first switching transistor that includes a gate connected to the scanning line, one of a source and a drain connected to the one of the terminals of the capacitor element, and the other of the source and the drain connected to a fixed potential line; and a second switching transistor that includes a gate connected to the control line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the source of the drive transistor, each of the pixels in a k-th drive block of the drive blocks further includes a third switching transistor that includes a gate connected to the scanning line, one of a source and drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the first signal line, k being a positive integer, and each of the pixels in a (k+1)-th drive block of the drive blocks further includes a fourth switching transistor that includes a gate connected to the scanning line, one of a source and a drain connected to the other of the terminals of the capacitor element, and the other of the source and the drain connected to the second signal line.
According to this aspect, the drive transistor threshold resetting period and the timing thereof can be made uniform within the same drive block by way of (i) a pixel circuit provided with: the first switching transistor which connects the gate of the drive transistor and the fixed potential line; and the second switching transistor which connects the current path between the capacitor element for storing a voltage corresponding to the luminance signal voltage of the drive transistor and the source of the drive transistor, and (ii) the arrangement of control lines, scanning lines, and signal lines to the respective pixels which are grouped into drive blocks. Therefore, the load on the drive circuit which outputs signals for controlling current paths, and controls signal voltages is reduced. In addition, through the above-described forming of drive blocks and the two signal lines arranged for every pixel column, the drive transistor resetting period can take a large part of a 1 frame period Tf which is the time in which all the pixels are refreshed. This is because the resetting period is provided in the (k+1)-th drive block in the period in which the luminance signal is sampled in the k-th drive block. Therefore, the resetting period is not divided on a per pixel row basis, but is divided on a per drive block basis. Therefore, as the display area is increased, a long relative resetting period can be set with respect to 1 frame period, without allowing luminescence duty to decrease with the increase in the display area. With this, a drive current based on luminance signal voltage that has been corrected with a high degree of precision flows to the luminescence elements, and thus image display quality improves.
Furthermore, in a display device according to an aspect of the present invention, the control line may be connected to the pixels in a same one of the drive blocks and not connected to the pixels in different ones of the drive blocks.
According to this aspect, by sharing in the same driving block the second switching transistor which connects the current path between the capacitor element and the source of the drive transistor, the load on the drive circuit which outputs signals to the control line can be reduced.
Furthermore, a display device according to an aspect of the present invention further includes a drive circuit which drives the pixels by controlling the first signal line, the second signal line, the control line, and the scanning line, wherein the drive circuit: simultaneously applies (i) a fixed voltage from the fixed potential line to the gate of the drive transistor of each of the pixels in the k-th drive block and (ii) a reference voltage from the first signal line to the source of the drive transistor, by simultaneously applying voltage, from the scanning line, which turn ON the first switching transistor and the third switching transistor of each of the pixels in the k-th drive block, in a state in which the corresponding second switching transistor is ON; simultaneously causes non-conduction between the fixed potential line and the gate of the transistor of each of the pixels in the k-th drive block and simultaneously causes non-conduction between the first signal line and the source of the drive transistor of each of the pixels in the k-th drive block, by simultaneously applying voltages, from the scanning line, which turn OFF the first switching transistor and the third switching transistor of each of the pixels in the k-th drive block, in a state in which the corresponding second switching transistor is ON; simultaneously applies (i) the fixed voltage from the fixed potential line to the gate of the drive transistor of each of the pixels in the (k+1)-th drive block and (ii) the reference voltage from the second signal line to the source of the drive transistor, by simultaneously applying voltages, from the scanning line, which turn ON the first switching transistor and the fourth switching transistor of each of the pixels in the (k+1)-th drive block, in a state in which the corresponding second switching transistor is ON; and simultaneously causes non-conduction between the fixed potential line and the gate of the transistor of each of the pixels in the (k+1)-th drive block and simultaneously causes non-conduction between the second signal line and the source of the drive transistor of each of the pixels in the (k+1)-th drive block, by simultaneously applying voltages, from the scanning line, which turn OFF the first switching transistor and the fourth switching transistor of each of the pixels in the (k+1)-th drive block, in a state in which the corresponding second switching transistor is ON.
According to this aspect, the drive circuit which controls the voltage of the first signal line, the second signal line, the control line, and the scanning line controls the resetting period, the signal voltage storing period, and the luminescence production (photon generation) period.
Furthermore, in a display device according to an aspect of the present invention, the signal voltage includes a luminance signal voltage for causing the luminescence element to generate photons and a reference voltage for resetting the drive transistor, the display device further includes: a signal line drive circuit that outputs the signal voltage to the first signal line and the second signal line; and a timing control circuit that controls the timing at which the signal line drive circuit outputs the signal voltage, and the timing control circuit (i) causes the signal line drive circuit to output the reference voltage to the second signal line when the signal line drive circuit is outputting the luminance signal voltage to the first signal line, and (ii) causes the signal line drive circuit to output the reference voltage to the first signal line when the signal line drive circuit is outputting the luminance signal voltage to the second signal line.
According to this aspect, the resetting period is provided in the (k+1)-th drive block, in the period in which the luminance signal is sampled in the k-th drive block. Therefore, the resetting period is not divided on a per pixel row basis, but is divided on a per drive block basis. Therefore, as the display area is increased, a long relative resetting period can be provided.
Furthermore, in the display device according to an aspect of the present invention, where a period of time for refreshing all of the pixels is Tf, and a total number of the drive blocks is N, a period of time for resetting the drive transistors is at most Tf/N. Furthermore, the present invention can be implemented, not only as a display device including such characteristic units, but also as display device driving method having the characteristic units included in the display device as steps.
A display device according to the present embodiment is a display device including pixels arranged in rows and columns, the display device including: a first signal line and a second signal line that are disposed in each of the columns; and a control line disposed in each of the rows, wherein the pixels compose at least two drive blocks each of which includes at least two of the rows, each of the pixels includes: a drive transistor; a capacitor element having one of terminals connected to the gate of the drive transistor; a luminescence element connected to the source of the drive transistor; a first switching transistor inserted between the source of the drive transistor and a fixed potential line, and including a gate connected to the scanning line; and a second switching transistor inserted between the source of the drive transistor and the other of the terminals of the capacitor element, each of the pixels in an odd drive block further includes a third switching transistor inserted between the first signal line and the other of the terminals of the capacitor element, and each of the pixels in an even drive block further includes a fourth switching transistor inserted between the second signal line and the other of the terminals of the capacitor element. With this, the drive transistor resetting periods can be made uniform within the drive block. Therefore, the load on the drive circuit is reduced. Furthermore, since a long resetting period can be taken with respect to one frame period, image display quality is improved.
Hereinafter, an embodiment of the present invention shall be described with reference to the Drawings.
The pixels 11A and 11B are arranged in rows and columns on the display panel 10. Here, the pixels 11A and 11B compose two or more drive blocks each of which is one drive block made up of plural pixel rows. The pixels 11A compose a k-th drive block (k is a positive integer) and the pixels 11B compose a (k+1)-th drive block. However, in the case where the display panel 10 is divided into N drive blocks, (k+1) is a positive integer less than or equal to N. This means that, for example, the pixels 11A compose odd drive blocks and the pixels 11B compose even drive blocks.
The signal line group 12 includes plural signal lines disposed in each of the pixel columns. Here, two signal lines are disposed in each of the pixel columns, the pixels of odd drive blocks are connected to a first signal line, and the pixels of even drive blocks are connected to a second signal line different from the first signal line.
The control line group 13 includes scanning lines and control lines, with each of the scanning lines and each of the control lines disposed on a per pixel basis.
The scanning/control line drive circuit 14 drives the circuit element of each pixel by outputting a scanning signal to the respective scanning lines of the control line group 13 and outputting a control signal to the respective control lines of the control line group 13.
The signal line drive circuit 15 drives the circuit element of each pixel by outputting a luminance signal or a reference signal to the respective signal lines of the signal line group 12.
The timing control circuit 20 controls the output timing of scanning signals and control signals outputted from the scanning/control line drive circuit 14. Furthermore, the timing control circuit 20 controls the timing for the outputting of luminance signals or reference signals outputted to the first signal line and the second signal line from the signal line drive circuit 15. The timing control circuit 20 causes the signal line drive circuit 15 to output the reference voltage to the second signal line while causing the outputting of the luminance signal to the first signal line, and causes the signal line drive circuit 15 to output the reference voltage to the first signal line while causing the outputting of the luminance signal to the second signal line.
The voltage control circuit 30 controls the voltage level of the scanning signals and the control signals outputted from the scanning/control line drive circuit 14.
In
The drive transistor 114 is a drive transistor having a drain connected to the power source line 110 which is a first power source line, and a source connected to the anode of the organic EL element 113. The drive transistor 114 converts a signal voltage applied between the gate and source into a drain current corresponding to such signal voltage. Subsequently, the drive transistor 114 supplies this drain current, as a drive current, to the organic EL element 113. The drive transistor 114 is configured of, for example, an n-type thin film transistor (n-type TFT).
The switching transistor 115 has a gate connected to the scanning line 133, and one of a source and a drain connected to a second electrode of the electrostatic storing capacitor 118, which is the other of the terminals of the electrostatic storing capacitor 118. Furthermore, the other of the source and the drain is connected to the first signal line 151 and functions as a third switching transistor in the pixel 11A in the odd drive block, and is connected to the second signal line 152 and functions as a fourth switching transistor in the pixel 11B in the even drive block.
The switching transistor 116 is a first switching transistor having a gate connected to the scanning line 133, one of a source and a drain connected to the gate of the drive transistor 114 and a first electrode of the electrostatic storing capacitor 118, which is one of the terminals of the electrostatic storing capacitor 118, and the other of the source and the drain connected to a fixed potential line 119. The switching transistor 116 has a function of determining the timing for applying a fixed voltage VREF of the fixed potential line 119 to the gate of the drive transistor 114.
The switching transistor 117 is a second switching transistor having a gate connected to the control line 131, one of a source and a drain connected to the second electrode of the electrostatic storing capacitor 118, and the other of the source and the drain connected to the source of the drive transistor 114. The switching transistor 117 turns OFF in the in the period for storing the luminance voltage from the signal line, and thus leak current from the electrostatic storing capacitors 118 and 119 to the drive transistor 114 is not generated in such period. Therefore, the switching transistor 117 has a function of causing accurate voltages corresponding to the signal voltage and to the threshold voltage of the drive transistor 114 to be stored in the electrostatic storing capacitors 118 and 119. On the other hand, the switching transistor 117 has the function of setting the source of the drive transistor 114 to the reset potential by turning ON in the resetting period, and is capable of instantaneously resetting the drive transistor 114 and the organic EL element 113. The switching transistors 115, 116, and 117 are each configured of, for example, an n-type thin film transistor (n-type TFT).
The electrostatic storing capacitor 118 is a capacitor element having the first electrode, which is one of its terminals, connected to the gate of the drive transistor 114 and the second electrode, which is the other of the terminals, connected to the one of the source and the drain of the switching transistor 115. The electrostatic storing capacitor 118 has a function of storing voltage corresponding to a luminance signal voltage and a reset voltage supplied from the first signal line 151 or the second signal line 152, and controlling a signal current supplied from the drive transistor 114 to the organic EL element 113 when the switching transistor 117 turns ON after the switching transistor 115 is turned OFF for example.
The control line 131 is connected to the scanning/control line drive circuit 14, and is connected to the respective pixels belonging to the pixel row including the pixels 11A or 11B. With this, the control line 131 has a function of selecting a conductive or non-conductive state between the source of the drive transistor 114 and the second electrode of the electrostatic storing capacitor 118.
The scanning line 133 has a function of supplying the respective pixels belonging to the pixel row including the pixels 11A or 11B with the timing for storing a signal voltage which is the luminance signal voltage or the reference voltage.
Each of the first signal line 151 and the second signal line 152 is connected to the signal line drive circuit 15 and the respective pixels belonging to the pixel column including the pixels 11A or 11B, and has a function of supplying the reference voltage for resetting the drive transistor and the signal voltage which determines luminance intensity.
It should be noted that, although not shown in
Next, the inter-pixel connection relationship of the control line 131, the scanning line 133, the first signal line 151, and the second signal line 152 shall be described.
As previously described, a drive block includes plural pixel rows, and there are two or more drive blocks within the display panel 10. For example, each of the drive blocks shown in
In the k-th drive block shown at the top stage of
Furthermore, the same connections as those in the k-th drive block are also carried out on the (k+1)-th drive block shown in the bottom stage of
Furthermore, in the k-th drive block, the first signal line 151 is connected to the other of the source and drain of the respective switching transistors 115 included in all of the pixels 11A in the drive block. Meanwhile, in the (k+1)-th drive block, the second signal line 152 is connected to the other of the source and drain of the respective switching transistors 115 included in all of the pixels 11B in the drive block.
With the above-described formation of drive blocks, the number of control lines 131 for controlling the connection between the source of the respective drive transistors 114 and second electrode of the respective electrostatic storing capacitors 118 is reduced. Therefore, the number of output lines of the scanning/control line drive circuit 14 which outputs drive signals to these control lines is reduced, thus allowing a reduction in circuit size.
Next, the driving method of the display device 1 according to the present embodiment shall be described using
First, at a time t01, the scanning/control line drive circuit 14 causes the voltage levels of the scanning lines 133 (k, 1) to 133 (k, m) to simultaneously change from LOW to HIGH so as to turn ON the respective switching transistors 115 included in all of the pixels 11A belonging to the k-th drive block. Furthermore, with the aforementioned change in the voltage levels of the scanning lines 133 (k, 1) to 133 (k, m), the respective switching transistors 116 simultaneously turn ON (S11 in
Furthermore, since the photon generation of the organic EL element 113 is stopped at the time t01, the fixed voltage VREF and the reference voltage VR1 are set in advance to satisfy the relationship shown in Expression 1 and Expression 2, respectively.
VREF−VCAT<Vth+Vt(EL) (Expression 1)
VR1−VCAT<Vt(EL) (Expression 2)
A numerical example satisfying Expression 1 and Expression 2 is for example, VREF=VCAT=VR1=0 V.
Here, Vth and Vt(EL) are the threshold voltages of the drive transistor 114 and the organic EL element 113 respectively, and VCAT is the cathode voltage of the organic EL element 113. Expression 1 is the condition under which current does not flow in a current path from the fixed potential line 119 to the drive transistor 114, to the organic EL element 113, and to the power source line 112, at the time t01. On the other hand, Expression 2 is the condition under which current does not flow in a current path from the first signal line 151 to the switching transistor 115, to the switching transistor 117, to the organic EL element 113, and to the power source line 112.
As described thus far, at the time t01, the photon generation of the respective organic EL elements 113 included in the pixels 11A belonging to the k-th drive block is stopped, and the operation of resetting the drive transistor 114 is started.
Next, at the time t02, the scanning/control line drive circuit 14 causes the voltage levels of the scanning lines 133 (k, 1) to 133 (k, m) to simultaneously change from HIGH to LOW so as to turn OFF the respective switching transistors 115 included in the pixels 11A belonging to the k-th drive block (S12 in
Simultaneously applying a fixed voltage and simultaneously causing non-conduction in the k-th drive block which are described above correspond to the resetting in the k-th drive block.
It should be noted that since the characteristics of the gate-source voltage applied to the drive transistor 114 and the drain current include hysteresis, it is necessary to secure the above-described reset period sufficiently and precisely initialize the gate potential and the source potential. When the threshold voltage correction or storing operation is executed while the resetting period is still insufficient, the fluctuation histories of the threshold voltage and the mobility for each of the pixels remain for a long time due to hysteresis and so on, and thus image luminance unevenness is not sufficiently suppressed, and display deterioration such as afterimages cannot be suppressed. Furthermore, by securing a sufficiently long resetting period, the gate potential and the source potential of the drive transistor 114 become steady, and thus a highly-precise resetting operation is realized.
As described thus far, in the period from the time t01 to the time t02, the operation of resetting the drive transistor 114 is executed simultaneously in the k-th drive block, and VREF and VR1 which are steady reset voltages are set to the gate and source of the respective drive transistors 114 included in all of the pixels 11A in the k-th drive block.
Next, at a time t03, the scanning/control line drive circuit 14 causes the voltage level of the control line 131 (k) to change from HIGH to LOW so as to turn ON the respective switching transistors 116 included in the pixels 11A belonging to the k-th drive block. With this, the switching transistor 117 is placed in the non-conductive state in the period for storing the luminance signal voltage which starts from the time t04, and thereby leak current from the electrostatic storing capacitor 118 to the source of the drive transistor 114 is not generated, and thus a precise voltage corresponding to a signal voltage can be stored in the electrostatic storing capacitor 118.
Next, between the time t04 and a time t05, the scanning/control line drive circuit 14 causes the voltage level of the scanning line 133 (k, 1) to change from LOW to HIGH to LOW so as to turn ON the respective switching transistors 115 included in the pixels in the first row (S13 in
It should be noted that from the time t04 to the time t05, the switching transistor 117 is in the non-conductive state, and the source potential of the drive transistor 114 is maintained at VR1 which is the potential during the resetting period, and thus current for photon generation does not flow in the forward direction of the organic EL element 113.
Therefore, a voltage corresponding to the luminance signal voltage Vdata is stored in the electrostatic storing capacitor 118 after both electrodes are precisely reset. The above-described operation of storing the voltage corresponds to the storing of the voltage (corresponding to the luminance signal voltage) in the k-th drive block.
Next, in the period up to the time t06, the storing operation from the time t04 to the time t05 is executed, row-by-row sequentially, in the pixels from the second row to the m-th row in the k-th drive block.
Next, at a time t07, the scanning/control line drive circuit 14 causes the voltage level of the control line 131 (k) to change from LOW to HIGH so as to turn ON the respective switching transistors 117 included in the pixels 11A belonging to the k-th drive block (S14 in
Vgs=(VREF−Vdata) (Equation 3)
Here, Vgs is, for example, 0 V to 5 V, and thus, as shown in (a) in
At this time, the source potential of the drive transistor 114 becomes a potential that is higher than the cathode potential VCAT of the organic EL element by as much as Vt(EL).
VS=Vt(EL)+VCAT (Expression 4)
Furthermore, from the Vgs defined in Expression 3 and the source potential defined in Expression 4, the gate potential of the drive transistor 114 is expressed using Expression 5.
VG=(VREFVdata)+Vt(EL)+VCAT (Expression 5)
As described thus far, by forming the pixel rows into drive blocks, the operation of resetting the drive transistors 114 is executed simultaneously in the respective drive blocks. Furthermore, by forming the pixel rows into drive blocks, the control line 131 can be shared in the respective drive blocks.
Furthermore, although the scanning lines 133 (k, 1) to 133 (k, m) are separately connected to the scanning/control line drive circuit 14, the timing of the drive pulse in the resetting period is the same. Therefore, the scanning/control line drive circuit 14 can suppress the rising of the frequency of the pulse signals to be outputted, and thus the output load on the drive circuit is reduced.
The above-described driving method having little output load on the drive circuit is difficult to realize with the conventional image display device 500 disclosed in Patent Reference 1. Even in the pixel circuit diagram shown in
In contrast, in each of the pixels 11A and 11B included in the display device 1 according to the present invention, the switching transistor 116 is added between the gate of the drive transistor 114 and the fixed potential line 119, and the switching transistor 117 is added between the source of the drive transistor 114 and the second electrode of the electrostatic storing capacitor 118 as previously described. With this, the potential in the gate and source of the drive transistor 114 is stabilized, and thus the time from the completion of resetting to the storing of the luminance signal voltage and the time from the storing up to the luminescence production can be arbitrarily set on a per pixel row basis According to this circuit configuration, it is possible to form drive blocks, and the resetting periods as well as the luminescence production periods can be made uniform within the same drive block.
Here, the comparison of luminescence duty defined according to the resetting period is performed in the conventional image display device using the two signal lines described in Patent Reference 1, and the display device having the drive blocks according to the present invention. It should be noted that for the image display device disclosed in Patent Reference 1, luminescence duty is calculated assuming that the threshold voltage detection period is the resetting period.
t1H=tD+PWD+tR(D)+tF(D) (Expression 6)
In addition, assuming PWD=tD, one horizontal period t1H is expressed as in Expression 7.
tD+PWD+tR(D)+tF(D)=2tD+tR(D)+tF(D) (Expression 7)
From Expression 6 and Expression 7, tD is expressed using Expression 8.
tD=(t1H−tR(D)−tF(D))/2 (Expression 8)
Furthermore, since the resetting period must begin and end within the reference voltage generation period, tD is expressed using Expression 9 when a maximum resetting period is secured.
tD=PWS+tR(S)+tF(S) (Expression 9)
From Expression 8 and Expression 9, PWS is expressed as in Expression 10.
PWS=(t1H−tR(D)−tF(D)−2tR(S)−tF(S))/2 (Expression 10)
With respect to Expression 10, for example, the luminescence duty of a panel having a vertical resolution of 1,080 scanning lines (+30 lines for blanking) and which is driven at 120 Hz.
In the conventional image display device, one horizontal period t1H in the case of having two signal lines is twice that of the case of having one signal line, and is thus expressed through the subsequent expression.
t1H={1 sec./(120 Hz×1110 lines)}×2=7.5 μS×2=15 μS
Here, tR(D)=tF(D)=2 μS and tR(S)=tF(S)=1.5 μS are assumed, and when these are substituted into Expression 10, the resetting period PWS becomes 2.5 μS.
Here, assuming that 1000 μS is required for a resetting period to have sufficient precision, at least 1000 μS/2.5 μS=400 of horizontal period is needed as a non-luminescence production period in the horizontal period required for such resetting operation. Therefore, the luminescence duty of the conventional image display device using two signal lines becomes (1110 horizontal period−400 horizontal period)/1110 horizontal period=64% or less.
Next, the luminescence duty of the display device having the drive blocks according to the present invention shall be calculated. Assuming that 1000 μS is required for a resetting period to have sufficient precision as in the above described condition, in the case of block driving, the resetting period shown in
According to the above comparison result, compared to the conventional image display device using two signal lines, combining block driving as in the present invention ensures a longer luminescence duty even when the same resetting period is set. Therefore, it is possible to realize a display device that ensures sufficient luminescence luminance and has long operational life due to reduced output load on drive circuits.
Conversely, it is understood that when the same luminescence duty is set to the conventional image display device using two signal lines and the display device combining block driving as in the present invention, the display device according to the present invention ensures a longer resetting period.
The driving method of the display device 1 according to the present embodiment shall be described once again.
On the other hand, the resetting operation for the drive transistors 114 in the (k+1)-th drive block is started immediately after the time t04 at which the resetting period for the drive transistors 114 in the k-th drive block is completed and the storing period is started.
First, at a time t11, the scanning/control line drive circuit 14 causes the voltage levels of the scanning lines 133 (k+1, 1) to 133 (k+1, m) to simultaneously change from LOW to HIGH so as to turn ON the respective switching transistors 115 included in the pixels 11B belonging to the (k+1)-th drive block. Furthermore, with the aforementioned change in the voltage levels of the scanning lines scanning lines 133 (k+1, 1) to 133 (k+1, m), the respective switching transistors 116 simultaneously turn ON (S21 in
Furthermore, since the photon generation of the organic EL element 113 is stopped at the time t11, the fixed voltage VREF and the reference voltage VR1 are set in advance to satisfy the relationship shown in Expression 1 and Expression 2, respectively.
As described thus far, at the time t11, the photon generation of the respective organic EL elements 113 in the pixels 11B belonging to the (k+1)-th drive block stops, and the resetting operation for the drive transistors 114 starts.
Next, at a time t12, the scanning/control line drive circuit 14 causes the voltage levels of the scanning lines 133 (k+1, 1) to 133 (k+1, m) to simultaneously change from HIGH to LOW so as to turn OFF the respective switching transistors 115 included in the pixels 11B belonging to the (k+1)-th drive block (S22 in
Simultaneously applying a fixed voltage in the (k+1)-th drive block and simultaneously causing non-conduction in the (k+1)-th drive block that are described above correspond to the resetting in the (k+1)-th drive block.
It should be noted that since the characteristics of the gate-source voltage applied to the drive transistor 114 and the drain current include hysteresis, it is necessary to secure the above-described resetting period sufficiently and precisely initialize the gate and source potentials. When the threshold voltage correction and storing operation are executed while the resetting period is still insufficient, the fluctuation histories of the threshold voltage and the mobility for each of the pixels remain for a long time due to the hysteresis and so on, and thus image luminance unevenness is not sufficiently suppressed, and display deterioration such as afterimages cannot be suppressed. Furthermore, by securing a sufficiently long resetting period, the gate potential and the source potential of the drive transistor 114 become steady, and thus a highly-precise resetting operation is realized.
As described thus far, in the period from the time t11 to the time t12, the resetting operation of the drive transistor 114 is performed simultaneously in the (k+1)-th drive block, and VREF and VR1 which are steady reset voltages are set respectively to the gate and source of the respective drive transistors 114 of all the pixels 11B in the (k+1)-th drive block.
Next, at a time t13, the scanning/control line drive circuit 14 causes the voltage level of the control line 131 (k+1) to change from HIGH to LOW so as to turn OFF the respective switching transistors 117 included in the pixels 11B belonging to the (k+1)-th drive block. With this, the switching transistor 117 is placed in the non-conductive state in the period for storing the luminance signal voltage which starts from the time t14, and thereby leak current from the electrostatic storing capacitor 118 to the source of the drive transistor 114 is not generated, and thus a precise voltage corresponding to a signal voltage can be stored in the electrostatic storing capacitor 118.
Furthermore, with the switching transistor 117, such period is not restricted to high-speed storing for controlling the leak current, and thus the ideal storing period necessary for storing an accurate luminance signal voltage can be secured.
Next, between the time t14 and a time t15, the scanning/control line drive circuit 14 causes the voltage level of the scanning line 133 (k+1, 1) to change from LOW to HIGH to LOW so as to turn ON the respective switching transistors 115 included in the pixels in the first row (S23 in
It should be noted that from the time t14 to the time t15, the switching transistor 117 is in the non-conductive state, and the source potential of the drive transistor 114 is maintained at VR1 which is the potential during the resetting period, and thus current for photon generation does not flow in the forward direction of the organic EL element 113.
Therefore, a voltage corresponding to the luminance signal voltage Vdata is stored into the electrostatic storing capacitor 118 after both electrodes are precisely reset. The above-described operation of storing the voltage corresponds to the storing of the voltage (corresponding to the luminance signal voltage) in the (k+1)-th drive block.
Next, in the period up to the time t16, the above-described storing operation from the time t14 to the time t15 is executed, row-by-row sequentially, in the pixels from the second row to the m-th row in the (k+1)-th drive block.
Next, at a time t17, the scanning/control line drive circuit 14 causes the voltage level of the control line 131 (k+1) to change from LOW to HIGH so as to turn ON the respective switching transistors 117 included in the pixels 11B belonging to the (k+1)-th drive block (S24 in
Here, Vgs is, for example, 0 V to 5 V, and thus the drive transistor 114 turns ON, drain current flows to the organic EL element 113, and the pixels 11B belonging to the (k+1)-th drive block concurrently generate photons according to the Vgs defined in Expression 3. This concurrent photon generation operation corresponds to the generating of the photons in the (k+1)-th step.
As described thus far, by forming the pixel rows into drive blocks, the operation of resetting the drive transistors 114 is executed simultaneously in the respective drive blocks. Furthermore, by forming the pixel rows into drive blocks, the control line 131 can be shared in the respective drive blocks.
Furthermore, although the scanning lines 133 (k+1, 1) to 133 (k+1, m) are separately connected to the scanning/control line drive circuit 14, the timing of the drive pulse in the resetting period is the same. Therefore, the scanning/control line drive circuit 14 can suppress the rising of the frequency of the pulse signals to be outputted, and thus the output load on the drive circuit is reduced.
As described thus far, in the period from the time t17 onward, the generation of photons in the organic EL elements 113 is executed simultaneously in the (k+1)-th drive block.
The operations described thus far are also executed sequentially in the (k+2)-th drive block onward in the display panel 10.
According to the driving method of the display device according to the embodiment of the present invention, luminescence production periods are concurrently set in the same drive block. Therefore, among the drive blocks, the luminescence production periods appear in a staircase pattern with respect to the row scanning direction.
As described thus far, the drive transistor 114 resetting periods as well as the timings thereof can be made uniform within the same drive block through the pixel circuits in which the switching transistors 116 and 117 are provided, the arrangement of the control lines, scanning lines, and signal lines to the respective pixels that are formed into drive blocks, and the above-described driving method. Therefore, the load on the scanning/control line drive circuit 14 which outputs signals for controlling current paths, and on the signal line drive circuit 15 which controls signal voltages is reduced. In addition, through the above-described forming of drive blocks and the two signal lines arranged for every pixel column, the drive transistor 114 resetting period can take a large part of a 1 frame period Tf which is the time in which all the pixels are refreshed. This is because the resetting period is provided in the (k+1)-th drive block in the period in which the luminance signal is sampled in the k-th drive block. Therefore, the resetting period is not divided on a per pixel row basis, but is divided on a per drive block basis. Thus, even when the display area is increased, a long relative resetting period with respect to a 1 frame period can be set without a significant increase in the number of outputs of the scanning/control line drive circuit 14 and without reducing luminescence duty. With this, a drive current based on luminance signal voltage that has been corrected with a high degree of precision flows to the luminescence elements, and thus image display quality improves.
For example, in the case where the display panel 10 is divided into N drive blocks, the resetting period allocated to each pixel is at most Tf/N. In contrast, in the case where the resetting period is set at a different timing for each of the pixel rows, and it is assumed that there are M rows of pixel rows (M>>N), resetting period allocated to each pixel is at most Tf/M. Furthermore, even in the case where two signal lines are disposed for each pixel column as disclosed in Patent Reference 1, threshold voltage correction period allocated to each pixel is at most 2Tf/M.
Furthermore, with the above-described formation of drive blocks, the control line for controlling the conduction between the source of the drive transistor 114 and the second electrode of the electrostatic storing capacitor 118 can be shared within the respective drive blocks. Therefore, the number of control lines outputted from the scanning/control line drive circuit 14 is reduced. Therefore, the load on the drive circuit is reduced.
For example, in the conventional image display device 500 disclosed in Patent Reference 1, two control lines (power supply line and scanning line) are disposed per pixel row. Assuming that the image display device 500 includes M rows of pixel rows, the control lines would total 2M lines.
In contrast, in the display device 1 according to the embodiment of the present invention, one scanning line per pixel row and one control line per drive block are outputted from the scanning/control line drive circuit 14. Therefore, assuming that the display device 1 includes M rows of pixel rows, the control lines (including scanning lines) would total (M+N) lines.
Since M>>N is realized in the case of a large surface area and a large number of rows of pixels, in such case, the number of control lines in the display device 1 according to the present invention can be reduced to approximately half compared to the number of control lines in the conventional image display device 500.
Although the embodiment has been described thus far, the display device according to the present invention is not limited to the above-described embodiment. The present invention includes other embodiments implemented through a combination of arbitrary components of the embodiment, or modifications obtained through the application of various modifications to the embodiment that may be conceived by a person of ordinary skill in the art, that do not depart from the essence of the present invention, or various devices in which the display device according to the present invention is built into.
It should be noted that in the pixels 11A and 11B shown in
It should be noted that although, in the aforementioned embodiment, description is carried out under the assumption that the switching transistors are n-type transistors which turn ON when the voltage level of the gate of switching transistor is HIGH, the forming of drive blocks described in the above-described embodiment can also be applied in pixels in which these switching transistors are configured of p-type transistors.
Even in a display device in which the switching transistors and the drive transistor are configured of p-type transistors as shown in
Furthermore, although in the above-described embodiment the cathode-side of the respective organic EL elements is connected in common with another pixel, the same advantageous effects are produced as in the above-described embodiment even with a display device in which the anode-side is shared and the cathode-side is connected to a pixel circuit.
Furthermore, for example, the display device according to the present invention is built into a thin flat-screen TV such as that shown in
Although only an exemplary embodiment of the present invention has been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiment without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of this invention.
The present invention is particularly useful in an active-type organic EL flat panel display which causes luminance to fluctuate by controlling pixel photon generation intensity according to a pixel signal current.
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