Provided is a reference voltage circuit having a soft start function, which is small in circuit size and is capable of providing a continuous voltage. The reference voltage circuit includes a reference voltage section and a soft start circuit. The reference voltage section includes a depletion mode mos transistor and a first enhancement mode mos transistor. The soft start circuit includes: a second enhancement mode mos transistor having a gate connected to a gate and a drain of the first enhancement mode mos transistor, and a drain connected to an output terminal of the reference voltage circuit; a mos switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode mos transistor; and a constant current source and a capacitor connected in series between a power supply and a ground.
|
1. A reference voltage circuit, comprising:
a reference voltage section comprising a depletion mode mos transistor and a first enhancement mode mos transistor; and
a soft start circuit,
wherein the soft start circuit comprises:
a second enhancement mode mos transistor having a gate connected to a gate and a drain of the first enhancement mode mos transistor, and a drain connected to an output terminal of the reference voltage circuit;
a mos switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode mos transistor; and
a constant current source and a capacitor connected in series between a power supply and a ground, and
wherein the mos switch is gradually turned ON by a voltage supplied when the capacitor is charged with a current of the constant current source, to thereby gradually raise a reference voltage.
2. A reference voltage circuit, comprising:
a reference voltage section; and
a soft start circuit,
the reference voltage section comprising:
a depletion mode mos transistor having a gate and a source, which are connected to a ground;
a first enhancement mode pmos transistor having a source connected to a power supply terminal, and a gate and a drain connected to a drain of the depletion mode mos transistor;
a second enhancement mode pmos transistor having a gate connected to the gate of the first enhancement mode pmos transistor, and a source connected to the power supply terminal; and
a first enhancement mode nmos transistor having a gate and a drain connected to a drain of the second enhancement mode pmos transistor,
wherein the soft start circuit comprises:
a second enhancement mode nmos transistor having a gate connected to the gate and the drain of the first enhancement mode nmos transistor, and a drain connected to an output terminal of the reference voltage circuit;
a mos switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode nmos transistor; and
a constant current source and a capacitor connected in series between a power supply and a ground, and
wherein the mos switch is gradually turned ON by a voltage supplied when the capacitor is charged with a current of the constant current source, to thereby gradually raise a reference voltage.
3. A reference voltage circuit according to
4. A reference voltage circuit according to
5. A reference voltage circuit according to
6. A reference voltage circuit according to
|
|||||||||||||||||||||||||||
This application claims priority under 35 U.S.C. §119 to Japanese Patent Application Nos. 2010-067067 filed on Mar. 23, 2010 and 2010-244376 filed on Oct. 29, 2010, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a reference voltage circuit, and more particularly, to a reference voltage circuit having a soft start function in which a reference voltage gradually rises after an elapse of a predetermined time period.
2. Description of the Related Art
Generally, in a reference voltage circuit having a soft start function, a charge period of charging a capacitor by a constant current source is set as a soft start time period. After a charged voltage exceeds a predetermined voltage, a switch is switched, to thereby transit from the soft start voltage to a predetermined reference voltage (for example, see Japanese Patent Application Laid-open No. 2000-56843).
A conventional reference voltage circuit is described.
A connection point between the constant current source 102 and the capacitor C is connected to an output terminal Vref of the reference voltage circuit. The comparator 103 has a non-inverting input terminal connected to the output terminal Vref, and an inverting input terminal connected to an output terminal of the constant voltage source 101 via an offset voltage Vos. Further, the comparator 103 has an output terminal connected to the switch SW2, the constant current source 102, and the delay circuit 104. The delay circuit 104 has an output terminal connected to the switch SW3.
The capacitor C receives a constant current Ic from the constant current source 102 to be charged. The comparator 103 compares a voltage obtained by subtracting the predetermined offset voltage Vos from an output voltage Vbgr of the constant voltage source 101 with a voltage at the connection point between the constant current source 102 and the capacitor C. Then, the comparator 103 outputs an output voltage reflecting the comparison result. When the voltage at the connection point between the constant current source 102 and the capacitor C is higher than the voltage obtained by subtracting the predetermined offset voltage Vos from the output voltage Vbgr of the constant voltage source 101, the switch SW2 is turned ON, the constant current source 102 stops supplying current, and the delay circuit 104 starts its operation. When the switch SW2 is turned ON, the capacitor C is charged by the constant voltage source 101 via the resistor R with an RC time constant. The output of the delay circuit 104 is connected to the switch SW3, and causes the switch SW3 to turn ON after an elapse of a predetermined time period from the operation start of the delay circuit 104. When the switch SW3 is turned ON, the output voltage Vbgr of the constant voltage source 101 is directly connected to the reference voltage Vref.
An operation of the conventional reference voltage circuit is described.
Under a state in which the switch SW1 is ON, the operation of the reference voltage circuit is stopped, and the reference voltage of the output terminal Vref is 0 V.
When the switch SW1 is turned OFF, the reference voltage circuit starts its operation. The capacitor C receives the constant current Ic from the constant current source 102 to start constant current charging. At this time, the reference voltage Vref increases linearly depending on the constant current Ic and the capacity of the capacitor C. When the voltage charged in the capacitor C exceeds Vbgr-Vos, the output signal of the comparator 103 is inverted. Thus, the switch SW2 is turned ON, the constant current source 102 stops supplying current, and the delay circuit 104 starts its operation. Because the constant current source 102 stops supplying current, the capacitor C is charged with power supplied from the output voltage Vbgr of the constant voltage source 101 via the resistor R.
After an elapse of a predetermined time period from the operation start of the delay circuit 104, the switch SW3 is turned ON, and thus the output voltage Vbgr of the constant voltage source 101 is directly provided as the reference voltage Vref.
In the conventional reference voltage circuit, switches are switched to set a soft start period and a predetermined reference voltage Vref. In this case, in order to generate switching signals for the switches, it is necessary to provide a comparator for comparing the internal reference voltage with the soft start voltage, and a delay circuit. As a result, the circuit size increases.
Further, there is a problem in that there appears discontinuity in the linearly increasing reference voltage because switching between the soft start period and the reference voltage output period is performed by the switches.
The present invention has been made in view of the above-mentioned problems, and therefore provides a reference voltage circuit having a soft start function, which is capable of providing a reference voltage without discontinuity.
In order to solve the above-mentioned problems, the reference voltage circuit according to the present invention has a configuration as follows.
A reference voltage circuit includes: a reference voltage section including a depletion mode MOS transistor and a first enhancement mode MOS transistor; and a soft start circuit, in which the soft start circuit includes: a second enhancement mode MOS transistor having a gate connected to a gate and a drain of the first enhancement mode MOS transistor, and a drain connected to an output terminal of the reference voltage circuit; a MOS switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode MOS transistor; and a constant current source and a capacitor connected in series between a power supply and a ground, and in which the MOS switch is gradually turned ON by a voltage supplied when the capacitor is charged with a current of the constant current source, to thereby gradually raise a reference voltage.
According to the reference voltage circuit of the present invention as described above, a comparator or a delay circuit for generating a switch signal of a switch SW is unnecessary, and hence the circuit size may be reduced. With the reduction in chip size, there is an effect that the manufacture cost can be reduced to form an inexpensive product.
Further, the reference voltage can be output continuously between the soft start operation and the stable operation.
Still further, even in a case where the output terminal of the reference voltage circuit is connected only to the gate of the MOS transistor, a stable soft start operation can be performed because an initial value of the reference voltage in the soft start operation is 0 V.
In the accompanying drawings:
Hereinafter, a reference voltage circuit according to the present invention is described with reference to the drawings.
(First Embodiment)
The reference voltage circuit includes a reference voltage generation section and a soft start circuit. The reference voltage generation section includes a depletion mode MOS transistor 20 and a first enhancement mode MOS transistor 21. The soft start circuit includes a constant current source 10, a capacitor 11, a MOS switch 12, and a second enhancement mode MOS transistor 22.
The depletion mode MOS transistor 20 has a drain connected to a power supply, and a gate and a source connected to each other. The first enhancement mode MOS transistor 21 has a gate and a drain connected to each other, and a source connected to a ground. The gate and the source of the depletion mode MOS transistor 20 are connected to the gate and the drain of the first enhancement mode MOS transistor 21, and a connection point therebetween corresponds to an output terminal of the reference voltage generation section.
The second enhancement mode MOS transistor 22 has a gate connected to the gate and the drain of the first enhancement mode MOS transistor 21, a source connected to the ground, and a drain connected to an output terminal of a reference voltage Vref. The MOS switch 12 is connected to the output terminal of the reference voltage generation section and the drain of the second enhancement mode MOS transistor 22, and is turned ON/OFF under the control of a voltage at a node N1.
The capacitor 11 has one side connected to the constant current source 10 and another side connected to the ground. A connection point between the constant current source 10 and the capacitor 11 is used to provide a control signal for the MOS switch 12.
Next, an operation of the reference voltage circuit is described.
When a power supply voltage is applied to the reference voltage circuit, the reference voltage generation section and the soft start circuit therein operate as described below.
A current flows through the depletion mode MOS transistor 20 from the drain to the source. The current flowing through the depletion mode MOS transistor 20 flows to the drain of the first enhancement mode MOS transistor 21, and then to the ground. Based on the current flowing from the drain of the first enhancement mode MOS transistor 21 to the ground, a voltage Vref1 generated at the output terminal of the reference voltage generation section is determined.
The constant current source 10 allows a constant current Ic to flow to the capacitor 11 to start charging the capacitor 11. At this time, the voltage at the node N1 is equal to a ground voltage because the capacitor 11 is not sufficiently charged. Therefore, the MOS switch 12 is in an OFF state. Although the voltage Vref1 is applied to the gate of the second enhancement mode MOS transistor 22, the drain thereof is connected to the MOS switch 12 in the OFF state, and hence a drain current does not flow. Therefore, the output terminal of the reference voltage circuit outputs the reference voltage Vref of 0 V.
After that, the charging of the capacitor 11 with the constant current Ic is continued to increase the voltage at the node N1, which causes the MOS switch 12 to gradually turn ON. Therefore, the current flowing through the depletion mode MOS transistor 20 also starts to flow through the second enhancement mode MOS transistor 22. As the current flowing through the second enhancement mode MOS transistor 22 gradually increases, the reference voltage Vref gradually increases, which realizes the soft start operation.
After the capacitor 11 is sufficiently charged with the constant current Ic, the MOS switch 12 is completely turned ON. As a result, an on-resistance value of the MOS switch 12 becomes small enough to be negligible. Here, in a case where the first enhancement mode MOS transistor 21 and the second enhancement mode MOS transistor 22 are formed in the same size, the same current flows through the two enhancement mode MOS transistors when the MOS switch 12 is completely turned ON, and hence the voltage Vref1 substantially equals the reference voltage Vref. By setting the voltage obtained at the time when the same current flows through the first enhancement mode MOS transistor 21 and the second enhancement mode MOS transistor 22 as the reference voltage Vref in advance, the reference voltage may be increased from the soft start period to reach the reference voltage Vref while maintaining continuity.
Next, an operation is described with reference to an operation explanatory diagram illustrated in
At a timing of time T0, the power supply voltage is applied. The voltage Vref1 is generated at the connection point between the depletion mode MOS transistor 20 and the first enhancement mode MOS transistor 21. The voltage Vref1 is not output to the output terminal of the reference voltage circuit because the voltage at the node N1 does not increase and the MOS switch 12 is in an OFF state until time T1. The reference voltage Vref is 0 V because the second enhancement mode MOS transistor 22 is turned ON.
The MOS switch 12 is gradually turned ON from a timing at time T1. Accordingly, a current starts to flow through the second enhancement mode MOS transistor 22, and hence the reference voltage Vref gradually increases. On the other hand, the current flowing through the first enhancement mode MOS transistor 21 decreases, and hence the voltage Vref1 decreases. At a timing of time T2, the same amount of current flows through the first enhancement mode MOS transistor 21 and the second enhancement mode MOS transistor 22. However, the voltage Vref1 is influenced by the on-resistance of the MOS switch 12, and hence takes a current value larger than that of the reference voltage Vref. Then, at a timing of time T3, the on-resistance of the MOS switch 12 becomes small enough to be negligible, and hence the voltage Vref1 and the reference voltage Vref become substantially equal to each other.
As described above, the voltage at the node N1 gradually increases to reduce the on-resistance of the MOS switch 12. As a result, the voltage Vref1 gradually decreases, and on the other hand, the reference voltage Vref gradually increases. Thus, the soft start operation with a continuous voltage is obtained.
Further, an initial value of the reference voltage Vref is 0 V owing to the action of the second enhancement mode MOS transistor 22, and hence a stable soft start operation may be performed.
Still further, by changing the settings of the capacitor 11 and the constant current source 10, the soft start period may be arbitrary set.
Note that, an embodiment of the reference voltage circuit according to the present invention is described with reference to the circuit of
(Second Embodiment)
The depletion mode MOS transistor 501 has a gate and a source, which are connected to the ground, and a drain connected to a drain and a gate of the enhancement mode PMOS transistor 502. The enhancement mode PMOS transistor 502 has a source connected to the power supply terminal. The enhancement mode PMOS transistor 503 has a gate connected to the gate of the enhancement mode PMOS transistor 502, a drain connected to a drain and a gate of the enhancement mode MOS transistor 504, and a source connected to the power supply terminal. The enhancement mode MOS transistor 504 has the gate and the drain connected to the MOS switch 12 and a gate of the enhancement mode MOS transistor 22, and a source connected to the ground.
Next, an operation of the reference voltage circuit according to the second embodiment is described. When a power supply voltage is applied, a current flows through the depletion mode MOS transistor 501, and a current flows through the enhancement mode MOS transistor 504 via a current mirror between the enhancement mode PMOS transistors 502 and 503. Then, because the current flows through the enhancement mode MOS transistor 504, the voltage Vref1 is generated between the gate and the source thereof, and the voltage Vref1 is input to the MOS switch 12 and the gate of the enhancement mode MOS transistor 22.
The constant current source 10 allows the constant current Ic to flow to the capacitor 11 to start charging the capacitor 11. At this time, the voltage at the node N1 is equal to the ground voltage because the capacitor 11 is not sufficiently charged. Therefore, the MOS switch 12 is in an OFF state. Although the voltage Vref1 is applied to the gate of the enhancement mode MOS transistor 22, the drain thereof is connected to the MOS switch 12 in the OFF state, and hence a drain current does not flow. Therefore, the output terminal of the reference voltage circuit outputs the reference voltage Vref of 0 V.
After that, the charging of the capacitor 11 with the constant current Ic is continued to increase the voltage at the node N1, which causes the MOS switch 12 to gradually turn ON. Therefore, the current flowing through the enhancement mode PMOS transistor 503 also starts to flow through the enhancement mode MOS transistor 22. As the current flowing through the enhancement mode MOS transistor 22 gradually increases, the reference voltage Vref gradually increases, which realizes the soft start operation.
After the capacitor 11 is sufficiently charged with the constant current Ic, the MOS switch 12 is completely turned ON. As a result, an on-resistance value of the MOS switch 12 becomes small enough to be negligible. Here, in a case where the enhancement mode MOS transistor 504 and the enhancement mode MOS transistor 22 are formed in the same size, the same current flows through the two enhancement mode MOS transistors when the MOS switch 12 is completely turned ON, and hence the voltage Vref1 substantially equals the reference voltage Vref. By setting the voltage obtained at the time when the same current flows through the enhancement mode MOS transistor 504 and the enhancement mode MOS transistor 22 as the reference voltage Vref in advance, the reference voltage may be increased from the soft start period to reach the reference voltage Vref while maintaining continuity.
As described above, the voltage at the node N1 gradually increases to reduce the on-resistance of the MOS switch 12. As a result, the voltage Vref1 gradually decreases, and on the other hand, the reference voltage Vref gradually increases. Thus, the soft start operation with a continuous voltage is obtained.
Further, an initial value of the reference voltage Vref is 0 V owing to the action of the enhancement mode MOS transistor 22, and hence a stable soft start operation may be performed.
Still further, by changing the settings of the capacitor 11 and the constant current source 10, the soft start period may be arbitrary set.
| Patent | Priority | Assignee | Title |
| 9076511, | Feb 21 2013 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and memory system including the same |
| 9425789, | Feb 26 2015 | ABLIC INC | Reference voltage circuit and electronic device |
| Patent | Priority | Assignee | Title |
| 5514948, | Sep 02 1992 | Hitachi, Ltd. | Reference voltage generating circuit |
| 6194955, | Sep 22 1998 | SOCIONEXT INC | Current source switch circuit |
| 6198337, | Dec 11 1996 | A & CMOS COMMUNICATION DEVICE INC | Semiconductor device for outputting a reference voltage, a crystal oscillator device comprising the same, and a method of producing the crystal oscillator device |
| 6348833, | Aug 04 1998 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Soft starting reference voltage circuit |
| 6798278, | Jun 23 2000 | Ricoh Company, Ltd. | Voltage reference generation circuit and power source incorporating such circuit |
| JP2000056843, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Mar 03 2011 | SUZUKI, TERUO | Seiko Instruments Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 025967 | /0839 | |
| Mar 16 2011 | Seiko Instruments Inc. | (assignment on the face of the patent) | / | |||
| Feb 01 2016 | Seiko Instruments Inc | SII Semiconductor Corporation | CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 037903 | /0928 | |
| Feb 09 2016 | Seiko Instruments Inc | SII Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 037783 | /0166 | |
| Jan 05 2018 | SII Semiconductor Corporation | ABLIC INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 045567 | /0927 | |
| Apr 24 2023 | ABLIC INC | ABLIC INC | CHANGE OF ADDRESS | 064021 | /0575 |
| Date | Maintenance Fee Events |
| Sep 10 2015 | ASPN: Payor Number Assigned. |
| Jul 28 2016 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Jul 30 2020 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Sep 30 2024 | REM: Maintenance Fee Reminder Mailed. |
| Date | Maintenance Schedule |
| Feb 12 2016 | 4 years fee payment window open |
| Aug 12 2016 | 6 months grace period start (w surcharge) |
| Feb 12 2017 | patent expiry (for year 4) |
| Feb 12 2019 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Feb 12 2020 | 8 years fee payment window open |
| Aug 12 2020 | 6 months grace period start (w surcharge) |
| Feb 12 2021 | patent expiry (for year 8) |
| Feb 12 2023 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Feb 12 2024 | 12 years fee payment window open |
| Aug 12 2024 | 6 months grace period start (w surcharge) |
| Feb 12 2025 | patent expiry (for year 12) |
| Feb 12 2027 | 2 years to revive unintentionally abandoned end. (for year 12) |