The present invention provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer is formed over the substrate and then a stacked layer is formed on the dielectric layer. The stacked layer includes a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer on the dielectric layer in sequence. Afterward, a first portion of the dielectric layer is removed using the stacked layer as a first mask to form a first opening that exposes a surface of the conductive region.
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1. A fabrication method of a dual damascene opening, the method comprising:
providing a substrate having a conductive region therein;
forming a single dielectric layer over the substrate;
forming a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer on the single dielectric layer, wherein the patterned metal hard mask layer, the patterned silicon oxynitride layer and the patterned silicon oxide layer, each having the same pattern on the single dielectric layer to form a stacked layer;
forming a first opening extending into but not penetrating through the single dielectric layer; and
removing a first portion of the single dielectric layer beneath and adjacent to the first opening to form the dual damascene opening comprising a second opening that exposes a surface of the conductive region by using the stacked layer as a first mask.
9. A fabrication method of a dual damascene opening, the method comprising:
providing a substrate having a conductive region therein;
forming a single dielectric layer over the substrate;
forming sequentially a metal hard mask layer and a silicon oxynitride layer over the single dielectric layer;
performing a surface property alteration process to form a modified layer on the silicon oxynitride layer;
patterning the modified layer, the silicon oxynitride layer and the metal hard mask layer to form a patterned modified layer, a patterned silicon oxynitride layer and a patterned metal hard mask layer having the same pattern so as to form a stacked layer;
forming a first opening extending into but not penetrating through the single dielectric layer; and
removing a first portion of the single dielectric layer beneath and adjacent to the first opening to form the dual damascene opening comprising a second opening that exposes a surface of the conductive region by using the stacked layer as a first mask.
2. The method of
forming sequentially a metal hard mask layer, a silicon oxynitride layer and a silicon oxide layer on the single dielectric layer;
forming sequentially a first bottom antireflection layer and a patterned photoresist layer on the silicon oxide layer;
removing the metal hard mask layer, the silicon oxynitride layer, the oxide layer and the first bottom antireflection layer that are not covered by the patterned photoresist layer in a single process step until a part of a surface of the single dielectric layer is exposed so as to form the patterned metal hard mask layer, the patterned silicon oxynitride layer, the patterned silicon oxide layer and a patterned first bottom antireflection layer; and
removing the patterned photoresist layer and the patterned first bottom antireflection layer.
3. The method of
4. The method of
forming a second patterned photoresist layer over the substrate to expose a surface of a second portion of the single dielectric layer not covered by the patterned oxide layer and the patterned silicon oxynitride layer; and
removing the second portion of the single dielectric layer to form the first opening in the single dielectric layer by using the second patterned photoresist layer as a second mask; and
removing the second patterned photoresist layer.
5. The method of
8. The method of
10. The method of
11. The method of
forming sequentially a metal hard mask layer and a silicon oxynitride layer on the single dielectric layer before the step of performing the surface property alteration process is conducted;
forming sequentially a first bottom antireflection layer and a patterned photoresist layer, on the modified layer;
removing the metal hard mask layer, the silicon oxynitride layer, the modified layer and the first bottom antireflection layer that are not covered by the patterned photoresist layer in a single process step until a part of a surface of the single dielectric layer is exposed so as to form the patterned metal hard mask layer, the patterned silicon oxynitride layer, the patterned modified layer and a patterned first bottom antireflection layer; and
removing the patterned photoresist layer and the patterned first bottom antireflection layer.
12. The method of
13. The method of
forming a second patterned photoresist layer over the substrate to expose a surface of a second portion of the single dielectric layer not covered by the patterned oxide layer and the patterned silicon oxynitride layer; and
removing the second portion of the single dielectric layer to form the first opening in the dielectric layer by using the second patterned photoresist layer as a second mask; and
removing the second patterned photoresist layer.
14. The method of
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This is a continuation application of and claims priority benefit of patent application Ser. No. 11/309,097, filed on Jun. 22, 2006. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
1. Field of the Invention
The present invention relates to a method for fabricating an interconnect structure and an interconnect opening. More particularly, the present invention relates to a method for fabricating a single-damascene structure, a dual-damascene structure, and an opening thereof.
2. Description of Related Art
With the advancement of semiconductor technologies, the dimensions of semiconductor devices continuously reduce to the deep sub-micron territory. As the level of integration of integrated circuits increases, the surface of a chip is inadequate to accommodate all the required interconnects. In order to accommodate the increase of interconnects after the miniaturization of semiconductor devices, the design of a multilevel interconnect is used in ultra large scale integration circuits (ULSI).
In general, the multilevel interconnection is formed using a damascene process, which includes the single-damascene process or the dual-damascene process. Currently, the damascene process that involves the defining of a trench (or opening) in a dielectric layer requires forming a titanium nitride layer on the dielectric layer first. Thereafter, a photoresist layer with a trench (or opening) pattern is formed over the titanium nitride layer. The trench (or opening) pattern of the photoresist layer is then transferred to the titanium nitride layer. Further using the titanium nitride layer with the trench (or opening) pattern as a hark mask, a trench (or opening) is then defined in the dielectric layer. Limited by the yellow light process, a plasma-enhanced oxide (PE-oxide) layer is typically formed on the titanium nitride layer to increase the process window, wherein both the titanium nitride layer and the PE-oxide layer serve as the hard mask layer in the damascene process.
However, there are problems still needed to be resolved in a damascene process. For example, before defining the trench (or opening) in the dielectric layer, two etching steps are performed in order to define the trench (or opening) pattern in the hard mask layer. The two etching steps include a first etching step and a second etching step. The first etching step includes removing a portion of the PE-oxide layer until the surface of the titanium nitride layer is exposed using the photoresist layer as a mask. The second etching step includes etching a portion of the titanium nitride layer until the surface of the dielectric layer is exposed. Accordingly, the conventional damascene process requires performing multiple steps, and thus a longer cycle time is resulted.
Accordingly, the present invention at least provides a method for fabricating an opening, in which the process step is simplified and the cycle time is conserved.
The present invention provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer is formed over the substrate and then a stacked layer is formed on the dielectric layer. The stacked layer includes a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer having the same pattern on the dielectric layer in sequence. Afterward, a first portion of the dielectric layer is removed using the stacked layer as a first mask to form a second opening that exposes a surface of the conductive region.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the step of forming the stacked layer includes forming sequentially a metal hard mask layer, a silicon oxynitride layer and a silicon oxide layer on the dielectric layer. Thereafter, a first bottom antireflection layer and a patterned photoresist layer on the silicon oxide layer are formed sequentially. After this, the metal hard mask layer, the silicon oxynitride layer, the oxide layer and the first bottom antireflection layer that are not covered by the patterned photoresist layer are removed in a single process step until a part of a surface of the dielectric layer is exposed so as to form the patterned metal hard mask layer, the patterned silicon oxynitride layer, the patterned silicon oxide layer and a patterned first bottom antireflection layer. Afterward, the patterned photoresist layer and the patterned first bottom antireflection layer are removed.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the patterned hard mask layer includes, but not limited to, tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the second opening is a single-damascen opening
According to an embodiment of the present invention, the fabrication method of the above-mentioned opening further includes before the first portion of the dielectric layer is removed, forming a first opening in the dielectric layer, so that a dual damascene opening constructs the second opening after the step of removing the first portion of the dielectric layer is performed.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the step of forming the first opening in the dielectric layer includes forming a second patterned photoresist layer over the substrate to expose a surface of a second portion of the dielectric layer and to cover the patterned oxide layer, the patterned silicon oxynitride layer and a third portion of the dielectric layer. Thereafter, the second portion of the dielectric layer is removed to form the first opening in the dielectric layer using the second patterned photoresist layer as a second mask. After this, the second patterned photoresist layer is removed.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, before the second patterned photoresist layer is formed, a second bottom antireflection layer is further formed over the substrate.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the stacked layer has a trench pattern.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the conductive region is a conductive line.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the dielectric layer is formed with a material including a low dielectric constant material.
The present invention also provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer over the substrate is formed and then a metal hard mask layer and a silicon oxynitride layer are formed sequentially over the dielectric layer. After this, a surface property alteration process is performed to form a modified layer on the silicon oxynitride layer. Afterward, the modified layer, the silicon oxynitride layer and the metal hard mask layer are patterned to form a stacked layer including a patterned modified layer, a patterned silicon oxynitride layer and a patterned metal hard mask layer having the same pattern. A first portion of the dielectric layer is removed to form a second opening that exposes a surface of the conductive region using the stacked layer as a first mask.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the surface property alteration process includes a plasma process.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the step of forming the stacked layer includes forming sequentially a metal hard mask layer and a silicon oxynitride layer on the dielectric layer before the surface property alteration process is performed to form the modified layer on the silicon oxynitride layer. A first bottom antireflection layer and a patterned photoresist layer are formed sequentially on the modified layer. Afterward, the metal hard mask layer, the silicon oxynitride layer, the modified layer and the first bottom antireflection layer that are not covered by the patterned photoresist layer are removed in a single process step until a part of a surface of the dielectric layer is exposed so as to form the patterned metal hard mask layer, the patterned silicon oxynitride layer, the patterned silicon oxide layer and a patterned first bottom antireflection layer. The patterned photoresist layer and the patterned first bottom antireflection layer are removed.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the patterned hard mask layer includes, but not limited to, tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the second opening is a single-damascen opening.
According to an embodiment of the present invention, the fabrication method of the above-mentioned opening further includes before the first portion of the dielectric layer is removed, forming a first opening in the dielectric layer, so that a dual damascene opening constructs the second opening after the first portion of the dielectric layer is removed.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the step of forming the first opening in the dielectric layer includes forming a second patterned photoresist layer over the substrate to expose a surface of a second portion of the dielectric layer and to cover the patterned oxide layer, the patterned silicon oxynitride layer and a third portion of the dielectric layer. After this, the second portion of the dielectric layer is removed to form the first opening in the dielectric layer using the second patterned photoresist layer as a second mask. Thereafter, the second patterned photoresist layer is removed.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, before the second patterned photoresist layer is formed, a second bottom antireflection layer is further formed over the substrate.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the stacked layer has a trench pattern.
According to an embodiment of the present invention, in the fabrication method of the above-mentioned opening, the conductive region is a conductive line.
According to the fabrication method and the damascene structure of the present invention, the plasma enhanced oxide layer (PE-oxide) in the prior art is replaced by the silicon oxynitride layer. Moreover, before the step of defining the trench in the dielectric layer, only a single etching step is required to define the trench (or opening) pattern in the hard mask layer. Therefore, the process step of the fabrication method of the present invention is simplified and the cycle time is reduced.
Several exemplary embodiments of the invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the foregoing general description and the following detailed description of preferred purposes, features, and merits are exemplary and explanatory towards the principles of the invention only and are not restrictive of the invention, as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention. It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
Referring to
Still referring to
The material of the photoresist layer 114 includes silicon nitride or other suitable materials. The photoresist layer 114 is formed by chemical vapor deposition, for example. The barrier layer 104 serves to prevent the oxidation of the copper surface and the diffusion of copper to the dielectric layer 106. The dielectric layer 106 is, for example, a low dielectric constant dielectric layer which is formed with a low dielectric constant material including inorganic materials, such as hydrogen silsesquioxane (HSQ), fluronated silicon glass (FSG), etc., or organic materials, such as fluorinated poly(arylene ether) (Flare), aromatic hydrocarbons (SILK), poly-arylethers (parylene), etc. The dielectric layer 106 is formed by chemical vapor deposition, for example. In one embodiment, the dielectric layer 106 is constituted with a low dielectric constant dielectric layer and an insulation layer, wherein the insulation layer can also serve as a chemical mechanical polishing (CMP) stop layer to prevent the dielectric layer 106 from being polished during the CMP process. The material of the metal hard mask layer 108 includes tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride, and the metal hard mask layer 108 is formed by chemical vapor deposition. The bottom antireflection layer is an organic bottom antireflection layer or inorganic bottom antireflection layer. The inorganic antireflection layer is formed by chemical vapor deposition, for example. The material of the inorganic antireflection layer includes, but not limited to, a non-crystalline phase carbon film, silicon nitride, silicon oxynitride or titanium nitride, etc.
In one embodiment, after forming the silicon oxynitride layer 110 and before forming the bottom antireflection layer 112, a silicon oxide layer (not shown) can also form on the silicon oxynitride layer 110 so that the refractive index (n) and the dielectric constant (k) of the silicon oxynitride layer 110 remain unchanged over time.
In another embodiment, after forming the silicon oxynitride layer 110, and before forming the bottom antireflection layer 112, a surface property alteration process can perform on the silicon oxynitride layer 110 to form an oxide layer (not shown) on the silicon oxynitride layer 110 in order to maintain the refractive index and the dielectric constant of the silicon oxynitride layer 110 from varying over time. The surface property alteration process includes a plasma process using an oxygen containing gas.
More particularly, the silicon oxynitride layer 110 can reduce the reflective light of the underlying reflective material (metal hard mask layer 108). Consequently, the photolithograph process is improved.
Referring to
Continuing to
After this, as shown in
It is worthy to note that before the step of defining an opening in the dielectric layer, only a single etching step is performed to define the opening in the hard mask layer. Therefore, not only the process step is simplified, the cycle time is greatly conserved.
The single-damascene structure formed according the method of the fabrication is disclosed as follows. Since the materials of the parts of the damascene structure have been disclosed in the above embodiment, they will not be reiterated herein.
Still referring to
In one embodiment, single-damascene structure further can include a silicon oxide layer (not shown), disposed on the silicon oxynitride layer 112.
In another embodiment, the single-damascene structure can include an oxide layer (not shown), disposed on the silicon oxynitride layer 112. The oxide layer is formed by performing a plasma process on the silicon oxynitride layer 112 to alter the surface property of silicon oxynitride layer 112. The above silicon oxide layer and oxide layer can serve to maintain the refractive index and the dielectric constant of the silicon oxynitride layer from changing over time.
Referring to
Still referring to
In one embodiment, after forming the silicon oxynitride layer 110 and before forming the bottom antireflection layer 112, a silicon oxide layer (not shown) can also form on the silicon oxynitride layer 110 so that the refractive index (n) and the dielectric constant (k) of the silicon oxynitride layer 110 remain unchanged over time.
In another embodiment, after forming the silicon oxynitride layer 110, and before forming the bottom antireflection layer 112, a surface property alteration process is performed on the silicon oxynitride layer 110 to form an oxide layer (not shown) on the silicon oxynitride layer 110 in order to maintain the refractive index and the dielectric constant of the silicon oxynitride layer 110 from changing over time. The surface property alteration process includes a plasma process using an oxygen containing gas.
As shown in
Similarly, the silicon oxynitride layer 110 and the metal hard mask layer 108 are removed under the same etching condition. Therefore, unlike the conventional practice in which the metal hard mask layer and the overlying layer have different properties and are removed under different etching conditions, the process step of the present invention is greatly simplified and the cycle time is conserved to increase the yield.
Thereafter, as shown in
In one embodiment, before forming the patterned photoresist layer 122, a bottom antireflection layer (not shown) is formed over the substrate 100 to cover the silicon oxynitride layer 110 and the dielectric layer 106.
Referring to
Continuing to
Thereafter, as shown in
Continuing to
The dual-damascene structure formed according the fabrication method of the present invention is disclosed as follows. Since the materials for the parts of the damascene structure have been disclosed in the above embodiment, they will not be reiterated herein.
Referring again to
In one embodiment, the dual-damascene structure further includes a silicon oxide layer (not shown), disposed on the silicon oxynitride layer 112.
In another embodiment, the dual-damascene structure includes an oxide layer (not shown), disposed on the silicon oxynitride layer 112. The oxide layer is formed by performing a plasma process on the silicon oxynitride layer 112 to alter the surface property of the silicon oxynitride layer 112. The above silicon oxide layer and oxide layer serve to maintain the refractive index and the dielectric constant of the silicon oxynitride layer from altering over time.
According to the present invention, before defining a trench (or opening) in the dielectric layer, only a single etching step is performed to define a trench (or opening) pattern in the hard mask layer. Not only the process step is simplified, the cycle time is conserved. Further, the silicon oxynitride layer can absorb the reflective light from the metal mask layer to enhance the photolithograph process.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Liu, Ming-Hsing, Yu, Chia-Hsiun
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