A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
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1. A semiconductor device having a static memory cell array, the static memory cell array comprising:
first and second static memory cells; and
a word line,
wherein each of the first and second static memory cells includes a latch circuit having a first inverter and a second inverter, and a first access transistor and a second access transistor connected to the latch circuit thereof,
wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor,
wherein the word line is electrically connected to gate electrode of the first and second access transistors of the first and second static memory cells, and the word line elongates along a first direction,
wherein the first and second static memory cells are disposed adjacently along the first direction,
wherein a gate electrode of each transistor of the first static memory cell and a gate electrode of each transistor of the second static memory cell are disposed as a mirror symmetry with respect to a line along a second direction perpendicular to the first direction,
wherein a first gate wiring is integrated by the gate electrodes of the first driver transistor and the first load transistor of the first static memory cell,
wherein a second gate wiring is integrated by the gate electrodes of the first driver transistor and the first load transistor of the second static memory cell,
wherein a third gate wiring is integrated by the gate electrodes of the second driver transistor and the second load transistor of the first static memory cell,
wherein a fourth gate wiring is integrated by the gate electrodes of the second driver transistor and the second load transistor of the second static memory cell,
wherein a fifth gate wiring is integrated by the gate electrodes of the second access transistor of the first static memory cell and the second access transistor of the second static memory cell,
wherein a sixth gate wiring includes the gate electrode of the first access transistor of the first static memory cell,
wherein a seventh gate wiring includes the gate electrode of the first access transistor of the second static memory cell,
wherein the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring, the fifth gate wiring, the sixth gate wiring, and the seventh gate wiring have a rectangular shape with a pair of longer sides along the first direction and a pair of shorter side along the second direction, respectively,
wherein active regions of transistors of the first and second static memory cells have opposing first sides, and the first sides are disposed along the second direction, respectively,
wherein the sixth gate wiring, the third gate wiring, the fourth gate wiring and the seventh gate wiring are disposed on a first straight line along the first direction in turn,
wherein the first gate wiring, the fifth gate wiring and the second gate wiring are disposed on a second straight line along the first direction in turn,
wherein a first distance between an edge of the first sides of the active region of each access transistor and an edge of the shorter side of the gate wiring of each access transistor is longer than a second distance between an edge of the sides of the active region of each driver transistor and an edge of the shorter side of the gate wiring of each driver transistor,
wherein the first distance is a shortest distance along the first direction between the edge of the first side of the active region of each access transistor and the edge of the shorter side of the gate electrode of each access transistor, and the second distance is a shortest distance along the first direction between the edge of the first side of the active region of each driver transistor and the edge of the shorter side of the gate electrode of each driver transistor,
wherein the sixth gate wiring, the third gate wiring, the fourth gate wiring and the seventh gate wiring are arranged to have a third distance between each adjacent gate wiring, and
wherein the first gate wiring, the fifth gate wiring and the second gate wiring are arranged to have the third distance between each adjacent gate wiring.
6. A semiconductor device comprising:
a memory cell array comprising first and second static memory cells and a word line,
wherein each static memory cell includes a latch circuit having a first inverter and a second inverter, and a first access transistor and a second access transistor connected to the latch circuit thereof,
wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor,
wherein the word line is electrically connected to a gate electrode of the first and second access transistors of the first and second static memory cells, and the word line elongates along a first direction,
wherein the first and second static memory cells are disposed adjacently along the first direction,
wherein a first cell first invert gate electrode is integrated by the gate electrodes of the first driver transistor and the first load transistor of the first static memory cell,
wherein a second cell first invert gate electrode is integrated by the gate electrodes of the first driver transistor and the first load transistor of the second static memory cell,
wherein a first cell second invert gate electrode is integrated by the gate electrodes of the second driver transistor and the second load transistor of the first static memory cell,
wherein a second cell second invert gate electrode is integrated by the gate electrodes of the second driver transistor and the second load transistor of the second static memory cell,
wherein a two-cells gate electrode is integrated by the gate electrodes of the second access transistor of the first static memory cell and the second access transistor of the second static memory cell,
wherein a first access gate electrode includes the gate electrode of the first access transistor of the first static memory cell,
wherein a second access gate electrode includes the gate electrode of the first access transistor of the second static memory cell,
wherein the first cell first invert gate electrode, the second cell first invert gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode, the first access gate electrode, the second access gate electrode, and the two-cells gate electrode are rectangular-shaped having a pair of longer sides along the first direction and a pair of shorter sides along a second direction crossing the first direction,
wherein active regions of transistors of the first and second static memory cells have opposing first sides, and the longer sides are disposed along the second direction, respectively,
wherein the first access gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode and the second access gate electrode are disposed on a first straight line along the first direction in turn,
wherein the first cell first invert gate electrode, the two-cells gate electrode and the second cell first invert gate electrode are disposed on a second straight line along the first direction in turn,
wherein a first distance between an edge of the first side of the active region of each access transistor and an edge of the shorter side of the gate electrode of each access transistor is longer than a second distance between an edge of the first side of the active region of each driver transistor and an edge of the shorter side of the gate electrode of each driver transistor,
wherein the first distance is a shortest distance along the first direction between the edge of the first side of the active region of each access transistor and the edge of the shorter side of the gate electrode of each access transistor, and the second distance is a shortest distance along the first direction between the edge of the first side of the active region of each driver transistor and the edge of the shorter side of the gate electrode of each driver transistor,
wherein the first access gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode and the second access gate electrode are arranged to have a third distance between each adjacent gate electrode, and wherein the first cell invert gate electrode, the two-cells gate electrode and the second cell first invert gate electrode are arranged to have the third distance between each adjacent gate electrode.
10. A semiconductor device comprising:
a memory cell array comprising first and second static memory cells, first neighbor and second neighbor static memory cells and a word line,
wherein each static memory cell includes a latch circuit having a first inverter and a second inverter, and a first access transistor connected to a first output of the first inverter and a second access transistor connected to a second output of the second inverter,
wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter having a second driver transistor and a second load transistor,
wherein the word line is electrically connected to gate electrode of the first and second access transistors of the first and second static memory cells, and the word line is arranged along a first direction,
wherein the first and second static memory cells are disposed adjacently along the first direction,
wherein the first and second neighbor static memory cells are disposed adjacently along the first direction,
wherein the first neighbor static memory cell and the first static memory cell are disposed adjacently along a second direction perpendicular to the first direction,
wherein the second static memory cell and the second neighbor static memory cell are disposed adjacently along the second direction,
wherein a gate electrode of each transistor of the first static memory cell and a gate electrode of each transistor of the second static memory cell are disposed as a mirror symmetry with respect to the second direction,
wherein a gate electrode of each transistor of the first neighbor static memory cell and a gate electrode of each transistor of the second neighbor static memory cell are disposed as a mirror symmetry with respect to a second direction,
wherein the gate electrode of each transistor of the first static memory cell and the gate electrode of each transistor of the first neighbor static memory cell are disposed as a mirror symmetry with respect to the first direction,
wherein the gate electrode of each transistor of the second static memory cell and the gate electrode of each transistor of the second neighbor static memory cell are disposed as a mirror symmetry with respect to the first direction,
wherein a first cell first invert gate electrode is integrated by the gate electrodes of the first driver transistor and the first load transistor of the first static memory cell,
wherein a second cell first invert gate electrode is integrated by the gate electrodes of the first driver transistor and the first load transistor of the second static memory cell,
wherein a first cell second invert gate electrode is integrated by the gate electrodes of the second driver transistor and the second load transistor of the first static memory cell,
wherein a second cell second invert gate electrode is integrated by the gate electrodes of the second driver transistor and the second load transistor of the second static memory cell,
wherein a two-cells gate electrode is integrated by the gate electrodes of the second access transistor of the first static memory cell and the second access transistor of the second static memory cell,
wherein a first access gate electrode includes the gate electrode of the first access transistor of the first static memory cell,
wherein a second access gate electrode includes the gate electrode of the first access transistor of the second static memory cell,
wherein the first cell first invert gate electrode, the second cell first invert gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode, the two-cells gate electrode, the first access gate electrode and the second access gate electrode are rectangular-shaped having a pair of opposing longer sides along the first direction and a pair of opposing shorter sides along the second direction,
wherein active regions of transistors of the first and second static memory cells have a pair of opposing first sides, and the first sides are disposed along the second direction, respectively,
wherein the first access gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode and the second access gate electrode are disposed on a first straight line along the first direction in turn,
wherein the first cell first invert gate electrode, the two-cells gate electrode and the second cell first invert gate electrode are disposed on a second straight line along the first direction in turn,
wherein the first access transistors of the first and second memory cells have a first distance between an edge of the first side of its active region and an edge of the shorter side of its gate electrode,
wherein the second access transistors of the first and second memory cells have a second distance between an edge of the first side of its active region and an edge of the shorter side of gate electrode,
wherein the first driver transistors of the first and second memory cells have a third distance between an edge of the first side of its active region and an edge of the shorter edge of its gate electrode,
wherein the second driver transistors of the first and second memory cells have a fourth distance between an edge of the first side of its active region and an edge of the shorter side of its gate electrode,
wherein the first distance is longer than the third distance,
wherein the second distance is longer than the fourth distance,
wherein the first distance is a shortest distance along the first direction between the edge of the first side of the active region of the first access transistors and the edge of the shorter side of the gate electrode of the first access transistors, the second distance is a shortest distance along the first direction between the edge of the first side of the active region of the second access transistors and the edge of the shorter side of the gate electrode of the second access transistors, the third distance is a shortest distance along the first direction between the edge of the first side of the active region of the first driver transistors and the edge of the shorter side of the gate electrode of the first driver transistors, and the fourth distance is a shortest distance along the first direction between the edge of the first side of the active region of the second driver transistors and the edge of the shorter side of the gate electrode of the second driver transistors,
wherein the first access gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode and the second access gate electrode are arranged to have a fifth distance between each adjacent gate electrode, and
wherein the first cell invert gate electrode, the two-cells gate electrode and the second cell first invert gate electrode are arranged to have the fifth distance between each adjacent gate electrode.
2. The semiconductor device according to
3. The semiconductor device according to
wherein the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring and fifth gate wiring each have an aspect ratio of the longer side of the gate wiring to the shorter side of not less than 5, and
wherein the shorter side of the gate wiring of each transistor has a length not longer than 0.15 μm.
4. The semiconductor device according to
wherein a first edge is the edge of the first side of the active region of each access transistor and the first edge configures the edge of the first side of the first distance,
wherein a first opposite edge is the edge of the first side of the active region of each access transistor and the first opposite edge opposes the first edge,
wherein a second edge is the edge of the first side of the active region of each driver transistor and the second edge configures the edge of the first side of the second distance,
wherein a second opposite edge is the edge of the first side of the active region of each driver transistor and the second opposite edge opposes the second edge,
wherein a first long edge includes the first edge in the access transistor and the second opposite edge in the driver transistor beside the access transistor, and the first long edge is uneven,
wherein a second long edge includes the first opposite edge in the access transistor and the second edge in the driver transistor beside the access transistor, and the second long edge is uneven, and
wherein an access transistor gate width of each access transistor is narrower than a driver transistor gate width of each driver transistor.
5. The semiconductor device according to
wherein immediately adjacent gate electrodes along the first direction are spaced apart substantially equal distances from each other.
7. The semiconductor device according to
wherein the longer sides of the first cell second invert gate electrode, the second cell second invert gate electrode, the first cell first invert gate electrode, the two-cells gate electrode and the second cell first invert gate electrode have a substantially equal length to each other.
8. The semiconductor device according to
wherein the first cell first invert gate electrode, the second cell first invert gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode and the two-cells gate electrode each have an aspect ratio of the longer side of the gate electrode to the shorter side of not less than 5, and
wherein the shorter side of the gate electrode of each transistor has a length not longer than 0.15 μm.
9. The semiconductor device according to
wherein a fourth distance is a shortest distance along the first direction between the edge of the first side of the active region of each driver transistor and the edge of the shorter side of the gate electrode of each access transistor,
wherein a fifth distance is a shortest distance along the first direction between the edge of the first side of the active region of each access transistor and the edge of the shorter side of the gate electrode of each driver transistor,
wherein the first distance is longer than the fourth distance, and
wherein the second distance is shorter than the fifth distance.
11. The semiconductor device according to
wherein the longer sides of the first cell second invert gate electrode, the second cell second invert gate electrode, the first cell first invert gate electrode, the two-cells gate electrode and the second cell first invert gate electrode have a substantially equal length to each other.
12. The semiconductor device according to
wherein the first cell first invert gate electrode, the second cell first invert gate electrode, the first cell second invert gate electrode, the second cell second invert gate electrode and the two-cells gate electrode each have an aspect ratio of the longer side of the gate electrode to the shorter side of not less than 5, and wherein the shorter side of the gate electrode of each transistor has a length not longer than 0.15 μm.
13. The semiconductor device according to
wherein immediately adjacent gate electrodes along the second direction are spaced apart substantially equal distances from each other.
14. The semiconductor device according to
wherein a sixth distance is a shortest distance along the first direction between the edge of the first side of the active region of the first driver transistors and the edge of the shorter side of the gate electrode of the first access transistors,
wherein a seventh distance is a shortest distance along the first direction between the edge of the first side of the active region of the second driver transistors and the edge of the shorter side of the gate electrode of the second access transistors,
wherein a eighth distance is a shortest distance along the first direction between the edge of the first side of the active region of the first access transistors and the edge of the shorter side of the gate electrode of the first driver transistors,
wherein a ninth distance is a shortest distance along the first direction between the edge of the first side of the active region of the second access transistors and the edge of the shorter side of the gate electrode of the second driver transistors,
wherein the first distance is longer than the sixth distance,
wherein the second distance is longer than the seventh distance,
wherein the third distance is shorter than the eighth distance, and
wherein the fourth distance is shorter than the ninth distance.
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This application is a Continuation of U.S. application Ser. No. 12/237,037 filed on Sep. 24, 2008 now abandoned, which is a Continuation of U.S. application Ser. No. 11/727,040, filed on Mar. 23, 2007 now abandoned, which is a Continuation of U.S. application Ser. No. 10/971,115, filed on Oct. 25, 2004, now abandoned, which is a Divisional of U.S. application Ser. No. 10/190,715, filed on Jul. 9, 2002, now U.S. Pat. No. 6,812,574, claiming priority of Japanese Patent Application No. 2002-003266, filed on Jan. 10, 2002, the entire contents of each of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor storage device and, more particularly, to a static random access memory.
2. Description of the Prior Art
A static random access memory (hereinafter referred to “SRAM”) is useful because it does not require refresh operation. However, the number of elements constituting one memory cell in the SRAM is large to increase an occupied area by the memory cell. For this reason, it is required to reduce a cell area. For example, Japanese Laid-open Patent Publication No. 9-270468 (U.S. Pat. No. 5,744,844) and Japanese Laid-open Patent Publication No. 10-178110 (U.S. Pat. No. 5,930,163) illustrate examples of cell layout in which one cell having a length in a word line direction which is larger than a length in a bit line direction. Of the examples, a flat configuration of the SRAM described in Japanese Laid-open Patent Publication No. 10-178110 is shown in FIGS. 16 and 17. FIG. 16 is a plan view related to one memory cell of the SRAM. FIG. 17 is an equivalent circuit diagram corresponding to the memory cell shown in FIG. 16. The length in the bit line direction is shortened to increase the speed, and the layout of an active layer and a gate wiring element has a simple shape to reduce a cell area.
From a viewpoint of decreasing patterning size, a phenomenon (optical proximity) in which a resist pattern on a wafer is distorted becomes conspicuous due to the interference of light in an exposure device. In addition, even in an etching process, pattern distortion is generated by the micro-loading effect after etching. The micro-loading effect is a phenomenon in which an etching rate decreases in a direction of depth when a pattern having a large difference in density. In recent years, in order to minimize these pattern distortions phenomena, a technique for the optical proximity correction (OPC) is developed and used in which a mask pattern is automatically corrected in advance in a photography process.
In general, in order to form a contact by forming a contact hole in a gate wiring element, a cover margin such as a lithographic margin and a machining margin must be set in consideration of blur in photolithography process. For this reason, a portion in which a contact hole should be formed on the gate wiring element must be deformed by increasing the width of the portion by a length corresponding to a cover margin. In addition, since a width must be partially increased to make the width of the gate wiring element fine, decreasing patterning size cannot be achieved easily.
In order to decrease patterning size in consideration of an optical proximity correction (OPC) pattern obtained by the optical proximity correction (OPC) technique, when gate wiring elements are complicatedly arranged, margins for the optical proximity correction must be set in the longitudinal and lateral directions. For this reason, a memory cell area cannot be reduced sufficiently because sufficient decrease in size cannot be achieved, and the margins are factors which hinder decrease in size.
It is an object of the present invention to secure lithographic and machining margins without complicatedly deforming a gate shape in formation of a gate wiring element of a semiconductor storage device, especially, an SRAM.
In accordance with one aspect of the present invention, there is a semiconductor storage device including a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element, a second gate wiring element, a first connector, and a second connector. The memory cell array has a plurality of memory cells. Each memory cell has first and second driver transistors, first and second load transistors, and first and second access transistors. That is to say, first and second sets each having a driver transistors, a load transistors, and an access transistors are designed in each memory cell within SRAM. The memory cells are two-dimensionally arranged on a semiconductor substrate. The word lines are connected to the memory cells and are arranged in parallel to each other along a first direction. The bit lines are connected to the memory cells and are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element composes a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element composes a gate electrode of the access transistor, and has a rectangular shape having straight line on opposite sides. That is to say, the first and second gate wiring element have fair lines such as notch-less shape. The first connector connects the first gate wiring element, an active region of the second driver transistor, and an active region of the second load transistor to each other. The second connector connects the second gate wiring element to the word lines.
In another aspect of the present invention, there is a semiconductor storage device including a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element, and a second gate wiring element. The memory cell array has a plurality of memory cells. Each memory cell has first and second driver transistors, first and second load transistors, and first and second access transistors are two-dimensionally arranged on a semiconductor substrate. The word lines are connected to the memory cells and arranged in parallel to each other along a first direction. The bit lines are connected to the memory cells and arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element composes a gate electrode of the first driver transistor and the first load transistor. The second gate wiring element is connected to the access transistor.
In the semiconductor storage device according to the present invention, the first gate wiring element and the second gate wiring element have rectangular shapes each having straight line on opposite sides and being free from a notch or a projection, and are linearly laid out. In this manner, since the first and second gate wiring elements can be formed at high accuracy, the characteristics of transistors constituting a memory cells can be stabilized. For this reason, a semiconductor storage device having stable characteristics can be obtained. In the semiconductor storage device, contacts to the respective wiring elements are formed by using local inter connectors (LICs). More specifically, the contacts of the respective gate wiring elements are not formed through via holes directly formed on the gate wiring elements, but the contacts are formed by the local inter connectors (LICs) formed by tungsten damascene. When the local inter connectors (LICs) are used, regular gate wiring elements each having a rectangular shape can be laid out without making a cover margin for contact in formation of the gate wiring elements. In addition, since the first gate wiring elements and the second gate wiring elements are laid out in parallel to each other, in the step of forming gate wiring elements by photolithography process, pattern distortion caused by interference can be suppressed. Therefore, an optical proximity effect in the photolithography process can be suppressed.
The present invention will become readily understood from the following description of preferred embodiments thereof made with reference to the accompanying drawings, in which like parts are designated by like reference numeral and in which:
Semiconductor storage devices according to embodiments of the present invention and a method of fabricating the same will be described below with reference to the accompanying drawings.
A semiconductor storage device according to first embodiment of the present invention and a method of fabricating the same will be described below with reference to
In Japanese Laid-open Patent Publications Nos. 2000-124332, 2000-208643, and 2000-31298 describe SRAMs each having a linearly arranged gate wiring element. However, in all the SRAMs described in these publications, contacts are formed by directly forming contact holes in the gate wiring elements. In fact, since a cover margin for making a contact is required, the gate wiring element is deformed or has an excessive width. For this reason, in contrast to the present invention, a rectangular gate wiring element cannot be obtained to have straight line on opposite sides and to be free from a notch and a projection. The “notch” mentioned here is a crena or a depression. Therefore, the “straight line” means that a side has substantially linear line formed without the notch.
In this semiconductor storage device, contacts to the gate wiring elements are formed by using the local inter connector (LIC) described in U.S. Pat. No. 5,541,427. More specifically, as the contacts to the respective gate wiring elements, contacts are not formed through via holes directly formed on the gate wiring elements, and they are formed by the local inter connectors (LICs) formed by tungsten damascene. By using the local inter connector LIC as described above, a cover margin for contact is not needed in fabrication of the gate wiring elements, and rectangular gate wiring elements can be laid out having straight line on opposite sides without a notch or a projection. Since the first gate wiring elements 3a and 3b and the second ones 3c and 3d are laid out in parallel to each other, pattern distortion caused by interference can be suppressed in the step of forming the gate wiring elements by photolithography process. For this reason, optical proximity effect in the photolithography process can be suppressed. Therefore, the gate wiring element can be in a small size.
In addition, the configuration of the semiconductor storage device will be described below. As shown in
Furthermore, a configuration extending from the substrate surface of a semiconductor substrate 1 of the semiconductor storage device in the vertical direction will be described below with reference to
A method of fabricating the semiconductor storage device will be described below with reference to
(a) A semiconductor substrate 1 is provided.
(b) The element isolation oxide film 2 is formed at a predetermined portion of the semiconductor substrate 1.
(c) Ions are implanted in a predetermined portion to form a well region. In this case, as shown in
(d) After a gate oxide film is deposited, and poly-silicon wiring layers 3 serving as gate wiring layers are deposited.
(e) Ion implantation is performed to form the transistors 11, 12, and 13.
(f) Thereafter patterning is performed, as shown in
(g) A sidewall 4 is formed.
(h) A source S and a drain D are formed by ion implantation.
(i) A CoSi2 layer is formed.
(j) An etching stopper film is deposited. A flattening insulating film 6a is deposited.
(k) The flattening insulating film 6a is etched by using a mask for an local inter connector LIC. At this time, the etching is stopped by the etching stopper.
(l) The etching stopper film exposed by etching the flattening insulating film 6a is removed to form a trench for a local inter connector LIC.
(m) Tungsten is deposited in the trench for local inter connector LIC, and the resultant structure is flattened. The tungsten is left in only the trench (W damascene process) to form a local inter connector LIC 5 made of tungsten. The first local inter connectors (LICs) 5a and 5b and the second local inter connectors (LICs) 5c and 5d can be formed. Since contacts to the gate wiring elements can be formed through the local inter connectors (LICs) 5a, 5b, 5c, and 5d, the shapes of the gate wiring elements need not deformed to make a margin for contact. As the damascene method with respect to the first local inter connectors (LICs) 5a and 5b, a damascene method for forming only the wires can be used.
(n) A flattening insulating film 6b is deposited.
(o) Holes for stack via holes 7 are formed.
(p) Tungsten is removed except for the local inter connectors (LICs) 5 and the stack via holes 7, as shown in
(q) A first metal layer 8 is deposited on the entire surface of the resultant structure.
(r) The first metal layer 8 is removed by using a mask for a first metal wiring element except for on a predetermined portion. In this manner, as shown in
(s) An insulating interlayer 6c is deposited.
(t) A hole for a first via hole 14 is formed.
(u) Tungsten is buried in the first via hole 14, and tungsten is removed by etching except for the tungsten in the first via hole 14, as shown in
(v) A second metal layer 9 is deposited, and it is removed except for predetermined portions. In this manner, a bit line, a VDD line, and a ground (GND) line can be formed by the second metal layer 9.
(w) An insulating interlayer 6d is deposited.
(x) A hole for a second via hole is formed by etching.
(y) Tungsten is buried in the second via hole, and the tungsten is removed except for the second via hole.
(z) A third metal wiring element 15 is deposited, and it is removed except for predetermined portions, as shown in
With the above steps, the semiconductor storage device described above can be obtained. A semiconductor storage device is fabricated by this method. The semiconductor storage device includes first and second gate wiring elements 3 each having a rectangular shape having straight line on opposite sides opposite to each other without a notch or a projection. In addition, the first and second gate wiring elements 3 can be regularly laid out along the longitudinal direction of the word line. In this manner, the transistor characteristics of the driver transistor 11, the load transistor 12, the access transistor 13, and the like constituting the semiconductor storage device can be stabilized and uniformed. Therefore, a semiconductor storage device having stable characteristics can be obtained.
A semiconductor storage device according to second embodiment of the present invention will be described below with reference to plan views showing the configurations of four memory cells in
The semiconductor storage device, as shown in
As shown in
A semiconductor storage device according to third embodiment of the present invention will be described below. This semiconductor storage device is different from that according to second embodiment except that the lengths and distance between gate wiring elements in the longitudinal direction in the first gate wiring elements 3a and 3b and the second gate wiring elements 3c and 3d are substantially equal to each other, respectively, and the widths and the distance between the gate wiring elements in a direction (second direction) perpendicular to the longitudinal direction are equal to each other, respectively. For this reason, since generation of optical proximity effect can be suppressed in a photolithography process, the shapes of gate wiring elements need not be deformed for optical proximity correction (OPC). Therefore, a yield can be prevented from being deteriorated by a shortage of lithographic margin. In addition, when a regular layout pattern is used, photolithography can be performed at high accuracy by using super resolution technique.
The lengths, widths, and the like of the first and second gate wiring elements are made substantially equal to each other, respectively, and the distance between the gate wiring elements are made equal to each other, so that burying spacing between the layers can be kept uniform. Therefore, as an insulating interlayer, not only a boron phosphorous silicate glass (BPSG) film having good overhang properties, but also a film such as an nitride silicate glass (NSG) film or a phosho-silicate glass (PSG) film using a material having relatively poor overhang properties can be used. For this reason, a high degree of freedom of material selection can be obtained, and the cost can be reduced. In addition, a material of the insulating interlayer can be selected depending on conditions such as machining difficulties, a dielectric constant to be set, the degree of difficulty of void generation, and a soft error.
A semiconductor storage device according to fourth embodiment of the present invention will be described below with reference to the graph in
In the semiconductor storage device according to the present invention, the first gate wiring element and the second gate wiring element have rectangular shapes each having straight line on opposite sides and being free from a notch or a projection, and are linearly laid out. In this manner, since the first and second gate wiring elements can be formed at high accuracy, the characteristics of transistors constituting a memory cells can be stabilized. For this reason, a semiconductor storage device having stable characteristics can be obtained. In the semiconductor storage device, contacts to the respective wiring elements are formed by using local inter connectors (LICs). More specifically, the contacts of the respective gate wiring elements are not formed through via holes directly formed on the gate wiring elements, but the contacts are formed by the local inter connectors (LICs) formed by tungsten damascene. When the local inter connectors (LICs) are used, regular gate wiring elements each having a rectangular shape can be laid out without making a cover margin for contact in formation of the gate wiring elements. In addition, since the first gate wiring elements and the second gate wiring elements are laid out in parallel to each other, in the step of forming gate wiring elements by photolithography process, pattern distortion caused by interference can be suppressed. Therefore, an optical proximity effect in the photolithography process can be suppressed.
In the semiconductor storage device according to the present invention, the longitudinal directions of the first and second gate wiring elements extend in the direction of the gate width of an access transistor. For this reason, the longitudinal directions of the gate wiring elements can be made equal to the longer side of the memory cell.
In addition, in the semiconductor storage device according to the present invention, the distance (pitches) of the first and second gate electrodes are made substantially equal to each other in the longitudinal direction (first direction). In this manner, since generation of an optical proximity effect can be suppressed in photolithography process, the shapes of the gate wiring elements need not be deformed for optical proximity effect correction (OPC). A decrease in yield caused by a shortage of lithographic margin can be prevented. A lithographic resolution can also be improved. In addition, since the characteristics of the respective transistors obtained as described above can be made uniform and stable, a semiconductor storage device having stable characteristics can be obtained.
In the semiconductor storage device according to the present invention, since the distance between the first and second gate wiring elements can be made substantially equal to each other, an optical proximity effect can be further suppressed in photolithography process. For this reason, a decrease in yield caused by a shortage of lithographic margin can be prevented. A lithographic resolution can also be improved. In addition, since the characteristics of the respective transistors obtained as described above can be made uniform and stable, a semiconductor storage device having stable characteristics can be obtained.
Furthermore, in the semiconductor storage device according to the present invention, since the first and second gate wiring elements have shorter sides having lengths which are substantially equal to each other, a optical proximity effect can be further suppressed in photolithography process. For this reason, a decrease in yield caused by a shortage of lithographic margin can be prevented. A lithographic resolution can also be improved.
Still furthermore, in the semiconductor storage device according to the present invention, the shapes of the first gate wiring elements and the second gate wiring elements projected on a plane parallel to the substrate can be made substantially equal to each other, so that burying spacing between the layers can be kept uniform. Therefore, as an insulating interlayer, not only a BPSG film having good overhang properties, but also a film such as an NSG film or a PSG film using a material having relatively poor overhang properties can be used. For this reason, a high degree of freedom of material selection can be obtained, and the cost can be reduced. In addition, a material of the insulating interlayer can be selected depending on conditions such as machining difficulties of chemical mechanical polishing, a dielectric constant to be set, the degree of difficulty of void generation, and a soft error.
In the semiconductor storage device according to the present invention, the first and second gate wiring elements are symmetrically arranged with respect to a predetermined symmetrical point. For this reason, a mask can be used such that the mask is rotated about the predetermined symmetrical point.
Furthermore, in the semiconductor storage device according to the present invention, an aspect ratio x of longer side L to shorter side W of each of the first and second gate wiring elements is 5 or more. When the aspect ratio of the gate wiring element is set to be 5 or more, the number of generated defects such as pattern disappearance can be considerably reduced.
Still furthermore, in the semiconductor storage device according to the present invention, the lengths of the shorter sides of the first and second gate wiring elements are 0.15 μm or less, the respective memory cells can be decreased patterning size.
In the semiconductor storage device according to the present invention, since the first and second local inter connectors consist of tungsten damascene, a contact margin for making a contact to a gate wiring element is not required. For this reason, the shapes of the gate wiring elements need not be deformed for a margin for contact in formation of the gate wiring elements.
In the semiconductor storage device according to the present invention, the longitudinal directions of the first and second gate wiring elements are arranged in parallel to each other. For this reason, formation of the gate wiring elements can be simplified. Therefore, the fabricating steps can be simplified.
In the semiconductor storage device according to the present invention, since the distance between the first and second gate wiring elements adjacent to each other in at least one of the first and second directions are made substantially equal to each other, an optical proximity effect can be suppressed in photolithography process. For this reason, a decrease in yield caused by a shortage of lithographic margin can be prevented. A lithographic resolution can also be improved. In addition, since the characteristics of the respective transistors obtained as described above can be made uniform and stable, a semiconductor storage device having stable characteristics can be obtained.
In the semiconductor storage device according to the present invention, the projected shapes of the first gate wiring elements and the second gate wiring elements on a plane parallel to the substrate can be made substantially equal to each other, so that burying spacing between the layers can be kept uniform. Therefore, as an insulating interlayer, not only a BPSG film having good overhang properties, but also a film such as an NSG film or a PSG film using a material having relatively poor overhang properties can be used. For this reason, a high degree of freedom of material selection can be obtained, and the cost can be reduced. In addition, a material of the insulating interlayer can be selected depending on conditions such as machining difficulties of chemical mechanical polishing, a dielectric constant to be set, the degree of difficulty of void generation, and a soft error.
In the semiconductor storage device according to the present invention, the contacts are made by the first and second connectors without directly forming contact holes in the first and second gate wiring elements. Therefore, the gate wiring elements do not require contact margins for contact. Therefore, the shapes of the gate wiring elements need not be deformed for contact margins in formation of the gate wiring elements.
In the method of fabricating a semiconductor storage device according to the present invention, the first and second gate wiring elements having rectangular shapes each having straight line on opposite sides and being free from a notch or a projection can be formed. In addition, the first and second gate wiring elements can be regularly laid out along the longitudinal direction of a word line. For this reason, the characteristics of transistors such as a driver transistor and an access transistor constituting the semiconductor storage device can be made stable and uniform. Therefore, a semiconductor storage device having stable characteristics can be obtained.
Although the present invention has been described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom.
Ishigaki, Yoshiyuki, Ohbayashi, Shigeki, Tomita, Hidemoto
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