Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a direct memory access (dma) channel managed by a dma controller/engine. A control data block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the dma controller. A CDB processor operating within the dma controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the dma controller, the dma controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption. The data modification engines that perform the data manipulation operations may be implemented on the dma controller such that the use of memory during data manipulation operations uses local RAM so as to avoid a need to access external memory during data manipulation operations.
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9. A direct memory access (dma) controller that performs a plurality of data modification operations on data being transferred via a direct memory access (dma) channel managed by said dma controller comprising:
a control data block (CDB) processor subsystem that fetches a control data block (CDB), said CDB containing instructions for reading said data from at least one data source, performing said plurality of data modification operations on said data, and writing said data to at least one destination;
a fill subsystem that retrieves said data from at least one data source in accord with said instructions encoded in said CDB;
a plurality of data modification engines within said dma controller that each perform at least one of a variety of data modification operations for each data modification operation of said plurality of data modification operations on said data received by fill subsystem in accord with said instructions encoded in said CDB such that at least two of said plurality of data modification operations are performed concurrently by said dma controller and a first data modification engine of said plurality of data modification engines creates first data results that are used as a basis of computation for a second data modification engine of said plurality of data modification engines to perform at least one data modification operation of said plurality of data modification operations; and
a drain subsystem that sends results of said plurality of data modification operations to at least one destination in accord with said instructions encoded in said CDB.
1. A method to perform a plurality of data modification operations on data being transferred via a direct memory access (dma) channel managed by a dma controller comprising:
providing a plurality of data modification engines within said dma controller that each perform at least one of a variety of data modification operations;
fetching a control data block (CDB) by said dma controller, said CDB containing instructions for reading said data from at least one data source, performing said plurality of data modification operations on said data, and writing said data to at least one destination;
retrieving by said dma controller said data from at least one data source in accord with said instructions encoded in said CDB;
performing within said dma controller each data modification operation of said plurality of data modification operations on said data received by said dma controller using one of said plurality of data modification engines provided on said dma controller for each data modification operation in accord with said instructions encoded in said CDB such that at least two of said plurality of data modification operations are performed concurrently by said dma controller and a first data modification engine of said plurality of data modification engines creates first data results that are used as a basis of computation for a second data modification engine of said plurality of data modification engines to perform at least one data modification operation of said plurality of data modification operations; and
sending by said dma controller results of said plurality of data modification operations to at least one destination in accord with said instructions encoded in said CDB.
17. A direct memory access (dma) controller that performs a plurality of data modification operations on data being transferred via a direct memory access (dma) channel managed by said dma controller comprising:
means for providing a plurality of data modification engines within said dma controller that each perform at least one of a variety of data modification operations;
means for fetching a control data block (CDB) by said dma controller, said CDB containing instructions for reading said data from at least one data source, performing said plurality of data modification operations on said data, and writing said data to at least one destination;
means for retrieving by said dma controller said data from at least one data source in accord with said instructions encoded in said CDB;
means for performing within said dma controller each data modification operation of said plurality of data modification operations on said data received by said dma controller using one of said plurality of data modification engines provided on said dma controller for each data modification operation in accord with said instructions encoded in said CDB such that at least two of said plurality of data modification operations are performed concurrently by said dma controller and a first data modification engine of said plurality of data modification engines creates first data results that are used as a basis of computation for a second data modification engine of said plurality of data modification engines to perform at least one data modification operation of said plurality of data modification operations; and
means for sending by said dma controller results of said plurality of data modification operations to at least one destination in accord with said instructions encoded in said CDB.
2. The method of
creating read commands within said dma controller in accord with said instructions encoded in said CDB to read said data from said at least one data source;
sending said read commands from said dma controller to said at least one data source; and
receiving at said dma controller said data from said at least one data source sent by said at least one data source in accord with said read commands.
3. The method of
creating write commands within said dma controller in accord with said instructions encoded in said CDB to write said results of said plurality of data modification operations to said at least one destination; and
sending by said dma controller said results of said plurality of data modification operations to said at least one destination in accord with said write commands.
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10. The dma controller of
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Direct Memory Access (DMA) is an essential feature of modern computers. DMA permits particular hardware subsystems of a computer to have read and/or write access to system memory independent of the Central Processing Unit (CPU). Some example hardware systems that may use DMA include, but are not limited to: disk drive controllers, RAID (Redundant Array of Independent Disks)-On-a-Chip (ROC) controllers, graphics cards, network cards, and sound cards. DMA may also be used for intra-chip data transfer on multi-core processors. Management and implementation of a DMA channel is typically performed by a DMA controller. Many times the DMA controller is equipped with local memory such that the DMA controller transfers data to and from the local DMA memory and the external main memory. Since the DMA controller manages the transfer of data and not the computer CPU, the data transfers that use DMA use much less computer CPU processing time, thus, increasing the effective computing power of a computer having a DMA controller. Without DMA, communication with peripheral devices or between cores of a multi-core system may fully occupy the CPU during the entire read/write operation, which makes the CPU unavailable for performing other computing tasks. With DMA, the CPU would initiate the transfer then do other operations while the transfer is in progress, and receive an interrupt from the DMA controller once the operation has been completed. Freeing the CPU from performing the data transfer with peripheral devices is especially important since communication with peripheral devices is typically slower than for normal system Random Access Memory (RAM), so the CPU would be unavailable for even longer periods of time during communication with peripheral devices without the use of a DMA channel managed by a DMA controller.
A typical DMA transfer copies a block of memory from one device to another. The CPU initiates the data transfer, but the CPU does not execute the data transfer itself. For an Industry Standard Architecture (ISA) bus, the data transfer is performed by a DMA controller, which is typically incorporated as part of the computer motherboard chipset. A Peripheral Component Interconnect (PCI) bus uses a bus mastering DMA where the peripheral device takes control of the bus and performs the transfer itself.
An embedded processor may include a DMA engine/controller within the chip to allow the processing element to issue a data transfer while continuing to perform other tasks during the data transfer. When the DMA controller is incorporated within a chip, the DMA controller is commonly referred to as a DMA engine. Multi-core embedded processors often include one or more DMA engines in combination with local DMA memory as subsystems within the chip multi-core processor chip.
An embodiment of the present invention may comprise a method to perform a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller comprising: providing a plurality of data manipulation engines within the DMA controller that each perform at least one of a variety of data manipulation operations; fetching a Control Data Block (CDB) by the DMA controller, the CDB containing instructions for reading the data from at least one data source, performing the plurality of data manipulation operations on the data, and writing the data to at least one destination; retrieving by the DMA controller the data from at least one data source in accord with the instructions encoded in the CDB; performing within the DMA controller each data manipulation operation of the plurality of data manipulation operations on the data received by the DMA controller using one of the plurality of data manipulation engines provided on the DMA controller for each data manipulation operation in accord with the instructions encoded in the CDB such that at least two of the plurality of data manipulation operations are performed concurrently by the DMA controller; and sending by the DMA controller results of the plurality of data manipulation operations to at least one destination in accord with the instructions encoded in the CDB.
An embodiment of the present invention may further comprise a Direct Memory Access (DMA) controller that performs a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by the DMA controller comprising: a Control Data Block (CDB) processor subsystem that fetches a Control Data Block (CDB), the CDB containing instructions for reading the data from at least one data source, performing the plurality of data manipulation operations on the data, and writing the data to at least one destination; a fill subsystem that retrieves the data from at least one data source in accord with the instructions encoded in the CDB; a plurality of data manipulation engines within the DMA controller that each perform at least one of a variety of data manipulation operations for each data manipulation operation of the plurality of data manipulation operations on the data received by fill subsystem in accord with the instructions encoded in the CDB such that at least two of the plurality of data manipulation operations are performed concurrently by the DMA controller; and a drain subsystem that sends results of the plurality of data manipulation operations to at least one destination in accord with the instructions encoded in the CDB.
An embodiment of the present invention may further comprise a Direct Memory Access (DMA) controller that performs a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by the DMA controller comprising: means for providing a plurality of data manipulation engines within the DMA controller that each perform at least one of a variety of data manipulation operations; means for fetching a Control Data Block (CDB) by the DMA controller, the CDB containing instructions for reading the data from at least one data source, performing the plurality of data manipulation operations on the data, and writing the data to at least one destination; means for retrieving by the DMA controller the data from at least one data source in accord with the instructions encoded in the CDB; means for performing within the DMA controller each data manipulation operation of the plurality of data manipulation operations on the data received by the DMA controller using one of the plurality of data manipulation engines provided on the DMA controller for each data manipulation operation in accord with the instructions encoded in the CDB such that at least two of the plurality of data manipulation operations are performed concurrently by the DMA controller; and means for sending by the DMA controller results of the plurality of data manipulation operations to at least one destination in accord with the instructions encoded in the CDB.
In the drawings,
As modern computer systems become more sophisticated, additional data manipulation operations are expected to be performed on data being transferred within a computer system and to peripheral devices connected to the computer system. For instance, a RAID (Redundant Array of Independent Disks)-On-a-Chip (ROC) system may be expected to perform a number of data manipulation operations on data being transferred as part of the ROC system operations. An ROC system typically includes a Direct Memory Access (DMA) engine/controller as a subsystem within the ROC architecture. Some typical data manipulation operations include: hash, Hash Message Authentication Code (HMAC), hash/HMAC combined, fill pattern, Linear Feedback Shift Register (LFSR), End-to-End Data Protection (EEDP) check/add/update/remove, exclusive OR (XOR), encryption, and decryption. The DMA engine/controller of an embodiment may incorporate performing various data manipulation operations on data being transferred within the DMA engine/controller to reduce processing requirements for other systems/subsystems within a computer system. Further, the DMA engine/controller of an embodiment may concurrently perform a plurality of data manipulations on the data being transferred such that the plurality of data manipulations are performed more quickly than performing the plurality of data manipulation operations one at a time in a serial fashion. Thus, an embodiment allows data to move freely from source to destination with as little interruption as possible. The data manipulation operations performed on the data being transferred by the DMA engine/controller of an embodiment may also store and retrieve data/modified data into memory local to the DMA engine/controller (i.e., local memory) avoiding unnecessary overhead to access memory external to the DMA engine/controller (i.e., external memory).
For example, the DMA engine/controller of an embodiment may encrypt and store data in a first data buffer located in local DMA memory using an encryption engine on the DMA engine/controller. While the encrypted data is being placed into the first data buffer, an XOR engine on the DMA engine/controller may concurrently perform an XOR operation on the encrypted data and store the XOR data in a second data buffer located in local DMA memory without any interruption to the data flow of the encrypted data to the first data buffer. By performing the XOR operation on the encrypted data as the encrypted data is being produced, an embodiment may avoid the latency of waiting for the encrypted data to be completely written to a data buffer before performing the XOR operation. In addition, the DMA engine/controller of an embodiment may also perform EEDP check, add, and/or remove operations in parallel with the encryption and XOR data manipulation operations, further reducing latency involved in performing a plurality of data manipulation operations on data being transferred by a DMA engine/controller.
Various embodiments may be implemented on DMA engines/controllers in a variety of computer systems and electronic devices having DMA engines/controllers. If desired, a computer system and/or electronic device may include multiple DMA engines/controllers if multiple DMA channels are desired. Also, some DMA engines/controllers may provide multiple DMA channels such that including multiple DMA engines/controllers in a system result in a multiplier effect where the number of available DMA channels is a product of the number of DMA engines/controllers times the number of DMA channels available on each DMA engine/controller. DMA controllers for an embodiment may be implemented as separate systems that are incorporated into a computer system and/or electronic device as a separate dedicated computer “card,” a separate dedicated chip, or as a separate dedicated electronic device. Often, however, the DMA controller is incorporated as a subsystem, or engine, of a larger multi-function chip, card, or circuitry integrated into a computer system or electronic device. Thus, DMA controllers for an embodiment may be implemented as DMA engine subsystems included within a larger multi-function chip, card, or circuit. Typically, when a DMA controller is included as subsystem of a larger multi-function chip, card, or circuit, the DMA controller is called a DMA engine. Hence, throughout this document, the terms DMA controller and DMA engine will be used interchangeably such that when there is a reference to a DMA controller it is also a reference to a DMA engine and vice versa.
For an embodiment, the data source(s) 102-104 may be any data source 102-104 compatible with typical DMA controllers/engines 106. An embodiment may gather/read data from a single data source 102 or from a plurality of sources 102-104. For instance, source data from a single memory area may be read from external memory (i.e., memory external to the DMA controller 106) and transferred to various data destinations 116-118. Likewise, source data from a multiple memory areas may be read from external and transferred to various data destinations 116-118 in one data transfer operation.
Data modification engines may be created to perform any data modifications desired for data being transferred via a DMA controller/engine 106. For example, some data modification engines may include, but are not limited to: hash, HMAC, hash/HMAC combined, fill pattern, Linear Feedback Shift Register (LFSR), End-to-End Data Protection (EEDP) check/add/update/remove, exclusive OR (XOR), encryption, and decryption. Some types of supported hashing algorithms include the standard Secure Hash Algorithm (SHA)-224, SHA-256, SHA-384, and SHA-512 algorithms which may be performed individually or concurrently by a hash engine. The input data for a data manipulation engine 110-112 may be designated to come from another data manipulation engine 110-112 as an intermediate data result in order to permit multiple data manipulations combined into a single result. The intermediate result may also be sent to one of the destination locations 116-118 if desired as encoded in the CDB 120. However, the intermediate data result does not necessarily need to be sent to a data destination 116-118. When working on data coming from another data manipulation engine, the second data manipulation engine may operate concurrently with the first data manipulation engine, but the second data manipulation may start slightly behind the first data manipulation engine in order to allow the first data manipulation engine to begin streaming intermediate result data before starting the second data manipulation engine calculations. For various embodiments, concurrent operation of data manipulation engines 110-112 may also occur as different data manipulation engines 110-112 perform operations on the same data (intermediate results and/or originally received data) at the same time in parallel. Further, various embodiments may deliver both the original data and the modified data results to the data destinations 116-118.
Various embodiments may implement the local source data storage 108 and the local modify data storage 114 within the DMA controller 106 as one or more local electronic memory circuits. Electronic memory may also be called computer readable memory even though the computer readable (i.e., electronic) memory may be included in electronic devices that require memory storage, but would not typically be considered to be computers. A typical implementation of the electronic memory would be to provide a set of electronic Random Access Memory (RAM) that may be portioned by the DMA controller 106 into source data storage 108 and modify data storage 114. The electronic memory may be in fixed partitions for the source data storage 108 and the modify data storage 114, but the DMA controller may also dynamically allocate the electronic memory RAM as needed for the source data storage and the modify data storage 114 so that the entire electronic memory may be more efficiently utilized. Further, the modify data storage 114 may be subdivided into multiple segments in order to store data from multiple data modify engines 110-112.
Data destinations 116-118 for an embodiment may be any data destination 116-118 compatible with typical DMA controllers/engines 106. Various embodiments may write data and/or modified data results to multiple data destinations 116-118 or to a single data destination 116. Individual data results may be sent to all, or only a subgroup, of the available data destinations 116-118. That is one result may be sent to data destinations 116-118 while other results may be sent only to a single destination 116 or to a subset of destinations 116-118. Typical data destinations 116-118 may include, but are not limited to: disk drives, computer peripherals, a separate external memory segment, and/or other external devices.
For the embodiment 500 shown in
In an example operation of a multi source move for the data modification engines of the embodiment shown in
An embodiment implementing the configuration 600 shown in
For the embodiment 700 shown in
In the ROC embodiment 802 shown in
Various embodiments may provide the control and management functions detailed herein via an application operating on a computer system, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), other programmable logic circuits, or other electronic devices. Embodiments may be provided as a computer program product which may include a computer-readable, or machine-readable, medium having stored thereon instructions which may be used to program/operate a computer (or other electronic devices) or computer system to perform a process or processes in accordance with the present invention. The computer-readable medium may include, but is not limited to, hard disk drives, floppy diskettes, optical disks, Compact Disc Read-Only Memories (CD-ROMs), Digital Versatile Disc ROMS (DVD-ROMs), Universal Serial Bus (USB) memory sticks, magneto-optical disks, ROMs, random access memories (RAMs), Erasable Programmable ROMs (EPROMs), Electrically Erasable Programmable ROMs (EEPROMs), magnetic optical cards, flash memory, or other types of media/machine-readable medium suitable for storing electronic instructions. The computer program instructions may reside and operate on a single computer/electronic device/electronic circuit or various portions may be spread over multiple computers/devices/electronic circuits that comprise a computer system. Moreover, embodiments may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection, including both wired/cabled and wireless connections).
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.
Olson, David M., Piccirillo, Gary
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