In-hierarchy circuit analysis and modification

Abstract

Modifying a hierarchical circuit design includes accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis and modifications on a selected portion of the hierarchical circuit data to achieve inter-block timing closure; and performing timing analysis and modifications on the hierarchical circuit data, while accounting for a modification made on the selected portion of the hierarchical circuit data, to achieve intra-block timing closure.

Description

BACKGROUND OF THE INVENTION

Electronic design automation (EDA) technology is becoming increasingly sophisticated, allowing circuit designers to create highly complex integrated circuits with greater functionality and better performance.

The place and route (P&R) stage of circuit design typically involves multiple steps. The typical P&R tool first partitions design data (e.g., netlist) into a top-level design and many block-level designs, outputting block-level circuit descriptions as Design Exchange Format (DEF) files. Boundary/timing constraints of the blocks are generated in standard formats such as Synopsis Design Constraints (SDC). Individual blocks are then flattened and processed by a block level P&R engine designed to process flat, non-hierarchical circuit blocks. The timing of individual blocks is obtained based on analysis by the block level engine. A block may be assigned certain timing budget such as maximum/minimum input/output delays. The block-level P&R engine would find the optimal placement and routing implementation for the block designs, while ensuring all block-level timing budgets are met. After the block-level P&R, the block designs are translated into abstract representation with necessary timing and physical boundary information, before they are incorporated into the top-level design. If any of the block-level I/O budget is not met, the corresponding inter-block timing path may not reach closure. In such case, the blocks involved in the critical timing path will need to be re-budgeted. New SDC files will need to be regenerated and block-level P&R will need to be refined. This iterative process goes on until all block-level and inter-block timings are closed.

A number of issues exist in the typical P&R process. Since the process is broken down into several steps involving different data representations, data management is complex, expensive, and error-prone. The top level and the block level are processed using separate engines, which can lead to timing correlation and tool compatibility problems. Since the top level designers and block level designers typically only have access to data for their respective levels, the assignment and modification of timing budgets tend to be inflexible. Also, the process usually goes through multiple iterations that require extensive coordination between block level and top level designers. For example, the designers usually have to exchange modified data by exporting and importing different files and merge modified data into the overall design. As a result, the turn-around time required to achieve timing closure is often lengthy.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings.

FIG. 1A is a diagram illustrating an embodiment of a data model used in a place and route process.

FIG. 1B is a flowchart illustrating an embodiment of an in-hierarchy place and route process.

FIG. 2 is a flowchart illustrating an embodiment of an in-hierarchy place and route process for achieving inter-block timing closure.

FIGS. 3A-3B are block diagrams of an example circuit design that is processed using a P&R process similar to 200 of FIG. 2.

FIG. 4 is a flowchart of an embodiment of an RC analysis process.

FIGS. 5A-5B are block diagrams illustrating an example circuit design in which intra-block circuits are affected by modifications made to the boundary circuits.

FIG. 6 is a flowchart illustrating an embodiment of a process for achieving intra-block timing closure.

DETAILED DESCRIPTION

The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions.

A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

Modifying a hierarchical circuit design to achieve timing closure is disclosed. The hierarchical design includes multiple circuit blocks arranged in a hierarchical structure. In some embodiments, timing analysis and modifications are performed on selected circuit data, such as selected portions of the top level data and the block level data, to achieve inter-block timing closure. In some embodiments, the selected circuit data includes boundary path data, i.e., inter-block paths that extend across block boundaries. Further timing analysis and modification are performed on the block level data, while accounting for modifications made on the selected circuit data, such as the boundary paths, to achieve intra-block timing closure.

FIG. 1A is a diagram illustrating an embodiment of a data model used in a place and route process. In the example shown, data in a hierarchical circuit design 100 is processed. Data associated with components from different hierarchical levels are loaded by a top level process 150 into memory 152. Each hierarchical component is treated as a container of information that may include subcontainers corresponding to components at a lower level in the hierarchy. For example, container 102, which stores top level chip assembly data such as top level assembly information of a graphic chip, includes subcontainers 104-110 storing block level data of circuit component blocks such as input/output circuit, digital signal processor, etc. Additional hierarchical levels and containers may be included in other designs. A single unified project file format is used for importing and exporting the design data, thus achieving a homogenous design environment.

In some embodiments, the circuit data includes netlists of circuit components and routing information. RC information (i.e., resistance and capacitance information) is derived from routing information. During the P&R process, the hierarchical data structure is maintained. In other words, as shown in this example, the top level process retains the structures for the top level container and the subcontainers and tracks the block boundaries, even though portions of the block level data from the subcontainers can be selected, flattened and placed in the top level container for the top level process to perform analysis and make modifications. Because the hierarchical structure and the boundary information are maintained throughout, changes made to top level and/or lower level block data by the top level process can be put back into the respective containers, without requiring manual manipulation. This technique, referred to as in-hierarchy P&R, allows timing analysis and modifications to be made directly by the top level process to achieve both block level and top level timing closure.

FIG. 1B is a flowchart illustrating an embodiment of an in-hierarchy place and route process. Process 180 may be performed on a computer system or any other appropriate device.

At 182, hierarchical circuit data is accessed in a hierarchical circuit design. Referring to FIG. 1A for a hierarchical circuit design example, hierarchical data that is accessed includes block level data within lower level blocks (such as regions 104-110) and top level data that lies only within the top level block ((such as region 120). Netlist, routing, and/or RC data may be accessed. In some embodiments, the data is stored as project files in a storage location and is read from the storage location into memory. The hierarchical data structure is maintained.

The typical P&R process includes the main stages of floor planning, block-level design, and chip assembly. The timing constraints within individual circuit blocks are usually met during design stages prior to the final assembly stage in the P&R process. Block level designers, however, often do not have visibility into areas outside the blocks they have designed and, therefore, cannot easily control the timing of these parts. Consequently, delays attributed to the inter-block paths can often cause the overall timing of the chip to exceed budget. As used herein, inter-block paths (also referred to as boundary paths) are paths that extend across the boundaries of individual blocks (e.g., path 122 of FIG. 1A), and intra-block paths refer to paths that lie entirely within individual blocks (e.g., path 124 of FIG. 1A). At 184, timing analysis and circuit modifications are performed based on a selected portion of the hierarchical data to achieve inter-block timing closure. In some embodiments, inter-block timing closure is achieved based on inter-block paths by applying timing analysis and circuit adjustments on selected portions of inter-block netlist, routing, and/or RC data. Inter-block timing closure is achieved iteratively in some embodiments, and the details of which are described below.

The modifications to the inter-block paths may affect the timing of intra-block paths. Thus, at 186, intra-block timing closure is achieved by performing timing analysis and modifications on the block level data, while accounting for previously made modifications to the selected portions of data. Intra-block timing closure is achieved iteratively in some embodiments, and the details of which are described below.

In some embodiments, steps in the P&R process are carried out by the same top level design process executing on the system, and no additional exporting/importing of data is required between analysis and modification stages. Since the modifications are made by the top level design process directly, no ECO (Engineering Change Order) to the block designer is required and the turn-around time between iterations is greatly reduced.

FIG. 2 is a flowchart illustrating an embodiment of an in-hierarchy place and route process for achieving inter-block timing closure. Process 200 may be performed on a computer system or any other appropriate device and can be used to implement 184 of process 180.

Assuming that circuit data in a hierarchical circuit design has already been accessed, at 204, a portion of the data is selected for timing analysis.

In some embodiments, the selected data includes all of the top level block data and selected portions of the lower level block data. Various portions of the circuit are assigned respective desired timing constraints (also referred to as timing budgets). Timing analysis is performed to determine whether the circuit portions achieve the timing constraints. During a typical design process, the timing constraints within individual circuit component blocks are usually met during block design stages prior to the final assembly stage in the P&R process. Block level designers, however, often do not have visibility into areas outside the blocks they have designed, and therefore cannot easily control the timing budget of these parts. Consequently, delays attributed to the boundary path can often cause the overall timing of the chip to exceed budget. Thus, in some embodiments, boundary netlist data is selected and placed in the top level container to be used by the top level process, and the timing analysis is focused on these regions instead of the entire chip to achieve greater computational efficiency. An example of how to select the portion for timing analysis is described in greater detail below in connection with FIGS. 3A-3B.

In some embodiments, the selected portion of data is stored in more expensive low latency memory (such as random access memory (RAM)) for the analysis, and the rest of the data, which is not used for the analysis, is swapped into higher latency memory (such as virtual memory or disk memory).

At 206, timing analysis is performed on the selected data. Here, the timing analysis is based on the netlist corresponding to the selected portion. Static Timing Analysis (STA), RC analysis, and/or any other appropriate timing analysis techniques may be employed.

At 208, the timing analysis result is used to determine whether the selected portion of the hierarchical data meets the desired timing constraint (also referred to as top-level SDC). If so, inter-block timing closure is achieved for this portion. If, however, the desired timing constraint is not met, at 210, circuit optimization is performed on the selected portion and the selected portion is modified by the top level design process as a result of the optimization. A number of standard optimization techniques can be used where the selected circuit portion of the circuit and the corresponding timing constraint are entered as inputs, and modifications to the inputted circuit that would satisfy the timing constraints are generated as outputs. The optimization can result in a variety of modifications (also referred to as logical fixes) for adjusting timing. For example, buffers can be added and gate size can be changed to improve timing. A subsequent P&R fixing step will modify each block level layout to realize those logical fixes physically, according to the design rules.

After the selected portion has been modified, control is returned to 206 and timing analysis is performed again on the modified selected portion. The analysis result is once again compared with the desired timing constraint at 208, and further optimization and modification are performed at 210 as needed. 206-210 may be iterated several times until inter-block timing closure is achieved.

FIGS. 3A-3B are block diagrams of an example circuit design that is processed using a P&R process similar to 200 of FIG. 2. The example assumes that the intra-block timing closure within blocks 302 and 304 have already been achieved, but whether the inter-block timing closure has been achieved is yet to be determined.

In the example shown in FIG. 3A, the boundary net between flip-flops A and D affects inter-block timing. The result of the timing analysis indicates that the inter-block timing constraint has not been met. Thus, top level optimization is performed on the A-D boundary path, and logical fixes are made to the circuitry and are shown in FIG. 3B. Specifically, the size of gate 306 is enlarged, and buffers 308 and 310 are added.

The logical fixes can change the routing pattern and RC tree of the circuit, and consequently change the timing delay. For example, in FIG. 3B, the additions of buffers 308 and 310 break up the circuit paths and, therefore, change the routing pattern, the topology of the RC tree, as well as wire delay. Thus, in some embodiments, RC analysis is also performed to estimate the impact of the modification on routing and to ensure that RC changes due to the routing changes would not cause timing constraints to be exceeded.

FIG. 4 is a flowchart of an embodiment of an RC analysis process. In some embodiments, process 400 is used as a part of the timing analysis to achieve timing closure. For example, process 400 may be incorporated into 206-210 of process 200 described above, or 608-610 of process 600 described below.

Assuming that hierarchical data has already been accessed, at 404, hierarchical RC information is obtained while maintaining the hierarchical structure of the hierarchical data. In other words, block boundaries are maintained, and hierarchical RC data corresponding to the top level block and lower level blocks remains in the blocks' respective containers. Specifically, boundary RC information based on RC trees on boundary paths between blocks and RC trees on boundary paths within blocks is obtained. Referring to FIG. 3A for an example, the RC tree based on path B-C between blocks 302 and 304 is obtained from the container for top level block 305, and RC trees based on paths A-B and C-D are obtained from containers for lower level blocks 302 and 304, respectively.

At 406, the RC information on boundary paths between blocks and within blocks is combined to generate boundary RC information. In the example of FIG. 3A, the RC tree between path B-C and the RC trees between paths A-B and C-D are combined to generate the boundary RC between A-D.

At 408, RC analysis is performed using the boundary RC information.

At 410, the timing delay resulting from the RC analysis is compared with the desired delay. If the computed delay is less than the desired delay, then the previously made changes for closing inter-block timing have not adversely affected the overall RC delay. RC timing is therefore closed. If, however, the computed delay exceeds the desired delay, further optimization and adjustments to the circuits are made at 414. In some embodiments, process 400 is repeated to make further optimization and netlist changes, until both the timing budget specification and the RC delay are satisfied.

In this case, RC trees that lie entirely within the block and do not cross block boundaries are not used. Since such data amounts to 80% of the overall RC data in some cases, omitting purely intra-block RC information during the analysis greatly reduces the amount of memory required for the analysis. In some embodiments, only the boundary paths with modified netlist that would result in changes to the RC tree are selected for analysis and modification, thus further reducing the amount of data required.

Changes made to the boundary paths for closing inter-block timing can also affect the timing of other intra-block paths, causing additional processing to be required. FIGS. 5A-5B are block diagrams illustrating an example circuit design in which intra-block circuits are affected by modifications made to the boundary circuits. FIG. 5A is similar to FIG. 3A except that in addition to the boundary paths, it also illustrates intra-block paths such as E-F in block 302 and G-H in block 304. Although the inter-block paths and the intra-block paths do not have direct electrical connection to each other, fixes to an inter-block path or a boundary path can change the nearby intra-block paths through coupling capacitances, thus changing the timing of these paths. For example, as shown in FIG. 5B, when an additional buffer 310 is added, intra-block path E-F is affected; when the size for gate 306 is adjusted, intra-block path G-H is affected.

If there is intra-block timing violation in a block, intra-block fixes are made so that modified intra-block paths in the block meet the timing constraints and inter-block paths in proximity to the block preserve their timing. For example, gate 314 on path E-F is resized and an additional buffer 316 is added to path G-H to fix the intra-block timing violations to blocks 302 and 304, respectively. Timing analysis and modifications may be reiterated in some embodiments to achieve timing closure.

FIG. 6 is a flowchart illustrating an embodiment of a process for achieving intra-block timing closure. Process 600 may be performed after inter-block timing closure has been achieved.

At 602, timing analysis is performed for a block. During the analysis, the boundary and inter-block paths are visible and their effects on intra-block timing are accounted for. Referring to FIG. 5A for an example, when block 302 is analyzed, boundary path A-D is visible and inputted to the analysis function, thus the effects of the boundary path on intra-block path E-F's timing is taken into account during the analysis. Similarly, when block 304 is analyzed, A-D is visible, and its effect on intra-block path G-H is accounted for.

Returning to FIG. 6, at 604, the result of the timing analysis is compared with the intra-block timing constraint for the block. If the result meets the intra-block timing constraint, in other words, the fixes made to achieve inter-block timing closure also achieve intra-block timing closure, then no further modification to the block is required and existing modifications to the block are committed. In various implementations, the intra-block timing constraints may come from block level data and/or the top-level SDC file. If the blocks are processed serially and there is another block to be processed, control is transferred to 602 to process the next block. If the process is repeated in parallel for the blocks or if all other blocks have already been processed, the process completes.

If, however, the result does not meet the intra-block timing constraint, at 606, intra-block optimization is performed to find potential intra-block fixes that will meet the constraint. Again, the boundary paths are visible and accounted for during the optimization process to ensure that the intra-block optimization does not introduce further timing violations to the boundary paths. In other words, the process ensures that the intra-block fixes would not cause disturbances to the boundary paths. Specifically, inter-block timing analysis is performed at 608. The analysis takes into account the potential intra-block fixes and their effects on the timing of the boundary paths. The intra-block fixes and the boundary paths are input into the timing analysis function. The inter-block timing analysis result is compared with the circuit's inter-block timing constraint at 610. If the inter-block timing constraint is met, the potential fixes do not disturb inter-block timing and therefore are accepted at 612. The process completes or moves on to process the next block. If, however, the inter-block timing constraint is not met, the potential fixes are rejected, and control is transferred to 606 to perform intra-block optimization again to find new potential fixes. 606-610 are repeated until an acceptable fix is found.

Modifying a hierarchical circuit design to achieve timing closure has been disclosed. By maintaining the hierarchical data structure and using selective portions of data for processing, greater computational efficiency is achieved. By using a unified process that accesses and modifies data that has a consistent format throughout, manual intervention is avoided and turn-around time is improved.

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.

Claims

1. A method of modifying a hierarchical circuit design, comprising:

accessing hierarchical circuit data in the hierarchical circuit design;

performing timing analysis using one or more processors, on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved;

in the event that inter-block timing closure is not achieved, performing a first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data to achieve inter-block timing closure;

performing timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes to determine whether intra-block timing closure is achieved; and

in the event that intra-block timing closure is not achieved on the modified hierarchical circuit data, performing a second set of one or more fixes to logic, component size, or both on the modified hierarchical circuit data to achieve intra-block timing closure.

2. The method of claim 1, wherein the method is performed with a top level design process.

3. The method of claim 1, wherein the selected portion of the hierarchical circuit data includes boundary path data.

4. The method of claim 1, wherein the selected portion of the hierarchical circuit data includes a selected portion of top-level block data and a selected portion of lower-level block data.

5. The method of claim 1, wherein the selected portion of the hierarchical circuit data includes netlist data.

6. The method of claim 1, wherein performing the first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data includes modifying a netlist associated with the selected portion of the hierarchical circuit data.

7. The method of claim 1, wherein the timing analysis on the selected portion of the hierarchical circuit data determines whether the selected portion of the hierarchical circuit data meets a timing constraint.

8. The method of claim 7, wherein the selected portion of the hierarchical circuit data is modified to meet the timing constraint.

9. The method of claim 1, wherein the selected portion of the hierarchical circuit data includes RC data.

10. The method of claim 1, wherein the selected portion of the hierarchical circuit data includes RC data, and performing the timing analysis includes combining intra-block RC data and between-block RC data to form boundary RC data.

11. The method of claim 1, wherein:

the selected portion of the hierarchical circuit data includes boundary path data; and

performing timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes includes analyzing effects of a modification to the boundary path data on an intra-block path.

12. The method of claim 11, further comprising determining whether a result of the timing analysis meets an intra-block timing constraint.

13. The method of claim 12, in the event that the intra-block timing constraint is not met, the method further comprising performing intra-block optimization to find a potential intra-block fix, wherein the optimization accounts for the boundary path data.

14. The method of claim 13, further comprising performing inter-block timing analysis that takes into account the potential intra-block fix and its effect on the boundary path data.

15. The method of claim 14, further comprising determining whether the inter-block timing analysis result meets an inter-block timing constraint.

16. The method of claim 15, further comprising:

in the event that the inter-block timing constraint is met, accepting the intra-block fix; and

in the event that the inter-block timing constraint is not met, repeating intra-block optimization to find another potential intra-block fix.

17. The method of claim 1, wherein the selected portion of the hierarchical circuit data is stored in low latency memory, and at least some of the hierarchical circuit data that is not selected is swapped into higher latency memory.

18. A system for modifying a hierarchical circuit design, comprising:

a processor configured to execute instructions to:

access hierarchical circuit data in the hierarchical circuit design;

perform timing analysis on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved;

in the event that inter-block timing closure is not achieved, perform a first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data to achieve inter-block timing closure;

perform timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes to determine whether intra-block timing closure is achieved; and

in the event that intra-block timing closure is not achieved on the modified hierarchical circuit data, perform a second set of one or more fixes to logic, component size, or both on the modified hierarchical circuit data to achieve intra-block timing closure; and

a memory coupled to the processor and configured to provide the processor with the instructions.

19. The system of claim 18, wherein the selected portion of the hierarchical circuit data includes boundary path data.

20. A computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions, which when executed by a computer, modifies a hierarchical circuit design, the computer instructions comprising:

accessing hierarchical circuit data in the hierarchical circuit design;

performing timing analysis on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved;

in the event that inter-block timing closure is not achieved, performing a first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data to achieve inter-block timing closure;

performing timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes to determine whether intra-block timing closure is achieved; and

in the event that intra-block timing closure is not achieved on the modified hierarchical circuit data, performing a second set of one or more fixes to logic, component size, or both on the modified hierarchical circuit data to achieve intra-block timing closure.

21. The system of claim 18, wherein the processor is configured to execute the instructions in a top-level design process.

22. The system of claim 18, wherein the selected portion of the hierarchical circuit data includes a selected portion of top-level block data and a selected portion of lower-level block data.

23. The system of claim 18, wherein the selected portion of the hierarchical circuit data includes netlist data.

24. The system of claim 18, wherein to perform the first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data includes to modify a netlist associated with the selected portion of the hierarchical circuit data.

25. The system of claim 18, wherein the timing analysis on the selected portion of the hierarchical circuit data determines whether the selected portion of the hierarchical circuit data meets a timing constraint.

26. The system of claim 25, wherein the selected portion of the hierarchical circuit data is modified to meet the timing constraint.

27. The system of claim 18, wherein the selected portion of the hierarchical circuit data includes RC data.

28. The system of claim 18, wherein the selected portion of the hierarchical circuit data includes RC data, and to perform the timing analysis includes to combine intra-block RC data and between-block RC data to form boundary RC data.

29. The system of claim 18, wherein:

the selected portion of the hierarchical circuit data includes boundary path data; and

to perform timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes includes to analyze effects of a modification to the boundary path data on an intra-block path.

30. The system of claim 29, wherein the processor is further configured to determine whether a result of the timing analysis meets an intra-block timing constraint.

31. The system of claim 30, in the event that the intra-block timing constraint is not met, the processor is further configured to perform intra-block optimization to find a potential intra-block fix, wherein the optimization accounts for the boundary path data.

32. The system of claim 31, wherein the processor is further configured to perform inter-block timing analysis that takes into account the potential intra-block fix and its effect on the boundary path data.

33. The system of claim 32, wherein the processor is further configured to determine whether the inter-block timing analysis result meets an inter-block timing constraint.

34. The system of claim 33, wherein the processor is further configured to:

in the event that the inter-block timing constraint is met, accept the intra-block fix; and

in the event that the inter-block timing constraint is not met, repeat intra-block optimization to find another potential intra-block fix.

35. The system of claim 18, wherein the selected portion of the hierarchical circuit data is stored in low latency memory, and at least some of the hierarchical circuit data that is not selected is swapped into higher latency memory.

36. The computer program product of claim 20, wherein the computer instructions are executed in a top level design process.

37. The computer program product of claim 20, wherein the selected portion of the hierarchical circuit data includes boundary path data.

38. The computer program product of claim 20, wherein the selected portion of the hierarchical circuit data includes a selected portion of top-level block data and a selected portion of lower-level block data.

39. The computer program product of claim 20, wherein the selected portion of the hierarchical circuit data includes netlist data.

40. The computer program product of claim 20, wherein performing the first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data includes modifying a netlist associated with the selected portion of the hierarchical circuit data.

41. The computer program product of claim 20, wherein the timing analysis on the selected portion of the hierarchical circuit data determines whether the selected portion of the hierarchical circuit data meets a timing constraint.

42. The computer program product of claim 41, wherein the selected portion of the hierarchical circuit data is modified to meet the timing constraint.

43. The computer program product of claim 20, wherein the selected portion of the hierarchical circuit data includes RC data.

44. The computer program product of claim 20, wherein the selected portion of the hierarchical circuit data includes RC data, and performing the timing analysis includes combining intra-block RC data and between-block RC data to form boundary RC data.

45. The computer program product of claim 20, wherein:

the selected portion of the hierarchical circuit data includes boundary path data; and

performing timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes includes analyzing effects of a modification to the boundary path data on an intra-block path.

46. The computer program product of claim 45, further comprising computer instructions for determining whether a result of the timing analysis meets an intra-block timing constraint.

47. The computer program product of claim 46, in the event that the intra-block timing constraint is not met, the computer program product further comprising computer instructions for performing intra-block optimization to find a potential intra-block fix, wherein the optimization accounts for the boundary path data.

48. The computer program product of claim 47, further comprising computer instructions for performing inter-block timing analysis that takes into account the potential intra-block fix and its effect on the boundary path data.

49. The computer program product of claim 48, further comprising computer instructions for determining whether the inter-block timing analysis result meets an inter-block timing constraint.

50. The computer program product of claim 49, further comprising computer instructions for:

in the event that the inter-block timing constraint is met, accepting the intra-block fix; and

in the event that the inter-block timing constraint is not met, repeating intra-block optimization to find another potential intra-block fix.

51. The computer program product of claim 20, wherein the selected portion of the hierarchical circuit data is stored in low latency memory, and at least some of the hierarchical circuit data that is not selected is swapped into higher latency memory.