Provided is, among other things, an apparatus that includes an input line for accepting an input signal that is continuous in time and continuously variable. Multiple processing branches are coupled to the input line, each including: (a) an analog bandpass filter, (b) a sampling/quantization circuit coupled to an output of the analog bandpass filter, and (c) a digital bandpass filter coupled to an output of the sampling/quantization circuit. An adder is coupled to outputs of the processing branches. The digital bandpass filters in different ones of the processing branches have frequency response bandwidths that are centered at different frequencies, and the analog bandpass filters in different ones of the processing branches have frequency responses with bandwidths that are at least 25% greater than the frequency response bandwidths of the digital bandpass filters in their respective processing branches.
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1. An apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, comprising:
an input line for accepting an input signal that is continuous in time and continuously variable;
a plurality of processing branches coupled to the input line, each of said processing branches including: (a) an analog bandpass filter, (b) a sampling/quantization circuit coupled to an output of the analog bandpass filter, and (c) a digital bandpass filter coupled to an output of the sampling/quantization circuit; and
an adder coupled to outputs of the plurality of processing branches,
wherein the digital bandpass filters in different ones of the plurality of processing branches have frequency response bandwidths that are centered at different frequencies, and
wherein the analog bandpass filters in different ones of the plurality of processing branches have frequency responses with bandwidths that are at least 25% greater than the frequency response bandwidths of the digital bandpass filters in their respective processing branches.
19. An apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, comprising:
an input line for accepting an input signal that is continuous in time and continuously variable;
a plurality of processing branches coupled to the input line, each of said processing branches including: (a) a sampling/quantization circuit, and (b) a digital bandpass filter coupled to an output of the sampling/quantization circuit;
a plurality of first adders, each combining outputs of at least two of the processing branches;
a plurality of resampling interpolators, each coupled to an output of one of the first adders; and
a second adder coupled to outputs of the plurality of resampling interpolators,
wherein the digital bandpass filters in different ones of the plurality of processing branches have frequency responses that are centered at different frequencies,
wherein a rate at which at least one of the sampling/quantization circuits operates is different than an overall output data rate of said apparatus, and
wherein each of the resampling interpolators converts a first signal sample rate used by the sampling/quantization circuits in at least one of its corresponding processing branches to a second signal sample rate that is different than the first signal sample rate.
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This application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/549,739 (the '739 Application), filed on Oct. 20, 2011; U.S. Provisional Patent Application Ser. No. 61/554,918 (the '918 Application), filed on Nov. 2, 2011; U.S. Provisional Patent Application Ser. No. 61/536,003 (the '003 Application), filed on Sep. 18, 2011, and titled “Method and Apparatus for Reducing Frequency Drift”; and U.S. Provisional Patent Application Ser. No. 61/501,284, filed on Jun. 27, 2011, and titled “Sampling/Quantization Converters”. The foregoing applications are incorporated by reference herein as though set forth herein in full.
The present invention pertains to systems, methods and techniques for reducing errors caused by sampling uncertainty in converting continuous-time continuously variable signals into a sampled, quantized signals. It is particularly applicable to very high sample-rate data converters that quantize high-frequency input signals with high precision.
Many applications in modern electronics require that continuous-time signals be converted to discrete signals for processing using digital computers and signal processors. Conventionally, this transformation is made using a method similar to converter circuit 5, illustrated in
In general, the precision of an analog-to-digital converter (ADC) is less than log2(Q) because of impairments such as sampling uncertainty, or timing jitter, that degrade the accuracy of the sampling/quantization operation and reduce the quality of the conversion process. Although one source of sampling uncertainty is the inability of sample-and-hold circuit 10 to consistently capture signals on the transitions (i.e., rising and falling edges) of sample clock 12, a primary source of sampling jitter/uncertainty in conventional ADCs tends to be the sample clock source itself. The sample clock is produced by a circuit, often called an oscillator, which conventionally includes a network that is resonant at a particular frequency (i.e., a resonator).
To illustrate the effects of sampling jitter on an ADC, it is informative to consider first the case of a narrowband (sinusoidal) input signal, such as x(t)=Am·sin(ωmt+φm), with arbitrary amplitude (Am), arbitrary phase (φm), and angular frequency ωm<½·fCLK. Assuming infinite resolution (i.e., number of rounding levels Q→∞), the discrete-time output of the converter is given by
ŷk(n)=Am sin(ωmT·n+φm+ωm·φ),
where the sampling interval T=1/fCLK and φ is a white, Gaussian noise sequence produced by sampling jitter (uncertainty) having power σφ2 and power spectral density N0 (i.e., N0=σφ2/½·fCLK)). For the case where |φ|<<1, which is typical for high-precision clock sources, it is relatively straightforward for those skilled in the art to show that
ŷn(n)≈Am·sin(ωmT·n+φm+Am·cos(ωmT·n+φm)·(ωm·φ),
where the first term in the above equation is the sampled input signal and the second term is noise introduced by sampling jitter. The power in the noise term increases with the square of the input angular frequency ωm according to PNoise=½·Am2·σφ2·ωm2, and this noise adds directly to the converter output to degrade conversion accuracy. Specifically, the effective resolution (i.e., ENOB) of a data converter degrades by 0.5 bits for every factor of two increase in output noise.
The jitter analysis above can be extended to the case of a broadband input signal by considering that any real, bandlimited signal can be approximated by a finite sum of sinusoids via a Fourier series. In analyzing the effects of sampling jitter, therefore, it is convenient to represent a broadband input signal (x), with bandwidth fB, as the sum of K sinusoids having arbitrary amplitude and arbitrary phase, where
amplitude values Ak are uniformly distributed over the interval [−1, 1], phase values φk are uniformly distributed over the interval (−π, +π, and angular frequency values ωk are uniformly distributed over the interval [0, 2π·fB] (i.e., ω0=0 and ωK-1=2π·fB). Again assuming infinite resolution (i.e., number of rounding levels Q→∞), the discrete-time output of the converter is given by
where the second term, which is the output noise introduced by sampling jitter, has
power
As K→∞ the power in the noise term converges to
where σS2 is the input signal power. Therefore, the extent to which sampling jitter degrades conversion accuracy is proportional to the square of the input signal bandwidth fB.
As a result of the above analysis, the present inventor has indentified a need for minimizing the effects of sampling jitter in data converter circuits, particularly those that are required to process input signals with high-frequency content (i.e., large ωk), or wide bandwidth (i.e., large fB). To overcome the processing speed limitations of electronic circuits, high-frequency converters conventionally employ an arrangement where multiple, distinct converters are operated in parallel (i.e., parallel processing). Conventional parallel processing arrangements include time-interleaving (time-slicing) converters and frequency-interleaving (frequency-slicing) converters. For interleaving in time, a high-speed sample clock is decomposed into lower-speed sample clocks at different phases. Each converter in the time-interleaving array is clocked with a different clock phase, such that the conversion operation is distributed in time across multiple converters (i.e., polyphase decomposition). While converter #1 is processing the first sample, converter #2 is processing the next sample, and so on.
For interleaving in frequency, the total bandwidth of the continuous-time signal is uniformly decomposed (i.e., divided) into multiple, narrowband segments (i.e., sub-bands). Each parallel processing branch converts one narrowband segment, and all the converter processing branches operate from a single, common sampling clock. According to one representative implementation of a frequency-interleaving ADC 30A, shown in
Frequency-interleaving converter circuit 30A, illustrated in
A variation on the conventional hybrid filter bank (HFB) converter is the multiband delta-sigma (MBΔΣ) converter circuit 30C, shown in
Although, conventionally, frequency-interleaving converters are considered to be less sensitive to timing jitter than time-interleaving converters, as a result of downconversion to baseband and use of a common sampling clock (Ding 2003), timing jitter is a problem for any converter that processes high-frequency input signals. Conventional methods for reducing timing jitter generally attempt to attenuate the short-term jitter (i.e., white phase noise) of the sampling clock source, ignoring longer-term jitter and drift. See Smilkstein, T., “Jitter Reduction on High-Speed Clock Signals” (PhD Thesis), University of California, Berkeley, 2007. These conventional methods typically involve improving the stability of the clock oscillator itself, for example using high-precision atomic or quartz resonators, or involve use of phase-locked loop (PLL) techniques (Smilkstein, 2007) to slave the frequency of a relatively stable oscillator (i.e., atomic or quartz) to the average frequency of a relatively unstable or noise-corrupted clock source.
Circuit 50, illustrated in
The jitter transfer function of circuit 50 is the frequency response from the output 53 of noisy oscillator 52, to the output 61 of the PLL. For a phase detector 56 with gain KD, a controlled oscillator 60 with gain KV, and a loop filter 58 with second-order, lag-lead response
the jitter transfer function, HJTF, has a lowpass response given by
where the PLL natural frequency ωn=√{square root over (KD·KV/α)} and the PLL damping factor
For reference, the jitter transfer function for PLL circuit 50 is plotted in
The conventional jitter attenuation methods, based on PLLs with high-stability controlled oscillators, can be useful for reducing the high-frequency jitter (i.e., short-term jitter) of a noise-corrupted clock source, as illustrated by the exemplary jitter transfer function in
The present inventor has discovered improved approaches to reducing errors caused by timing uncertainty in circuits that convert linear (analog) signals into discrete (digital) signals. For example, rather than reduce sampling jitter at the clock source, apparatuses and methods according to the preferred embodiments of the present invention reduce the level of output noise introduced by sampling jitter, effectively making the converter circuits less sensitive to errors from sampling uncertainty. In particular, compared to conventional means, the jitter-mitigation approaches of the preferred embodiments of the present invention have at least two distinct advantages, namely: 1) the improved approaches are effective at mitigating performance degradation due to low-frequency jitter (e.g., drift and wander), as well as high-frequency jitter; and 2) the improved approaches do not require high-stability clock sources (e.g., oscillators with high-precision resonators) with outputs that tune over a wide frequency range, which are impractical in many applications, such as those employing integrated-circuit fabrication.
Thus, one specific embodiment of the invention is directed to an apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal. The apparatus includes: an input line for accepting an input signal that is continuous in time and continuously variable; a plurality of processing branches coupled to the input line; and an adder coupled to outputs of the plurality of processing branches. Each of the processing branches includes: (a) an analog bandpass filter, (b) a sampling/quantization circuit coupled to an output of the analog bandpass filter, and (c) a digital bandpass filter coupled to an output of the sampling/quantization circuit. The digital bandpass filters in different ones of the plurality of processing branches have frequency response bandwidths that are centered at different frequencies, and the analog bandpass filters in different ones of the plurality of processing branches have frequency responses with bandwidths that are at least 25% greater than the frequency response bandwidths of the digital bandpass filters in their respective processing branches.
Preferably, the bandwidth of the digital filter determines the portion (i.e., sub-band) of the input signal spectrum that is converted by the associated processing branch, with the bandwidth of each digital filter being selected to produce minimal spectral overlap with the digital bandpass filters of the other processing branches. Unlike conventional HFB frequency-interleaving converters, the bandwidth of each analog bandpass filter preferably spans multiple converter sub-bands (or at least significantly more than one sub-band), with the bandwidth of each analog filter preferably being intentionally selected to produce appreciable spectral overlap with the analog bandpass filters of the other processing branches, so that the analog bandpass filters do not perform a frequency decomposition function. Compared to conventional converters, the foregoing converter generally can reduce the amount of output noise that is introduced by timing uncertainty, particularly for narrowband input signals having high-frequency content, using standard analog filter responses.
A second specific embodiment of the invention is directed to an apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal. The apparatus includes: an input line for accepting an input signal that is continuous in time and continuously variable; a plurality of processing branches coupled to the input line; a plurality of first adders, each combining outputs of at least two of the processing branches; a plurality of resampling interpolators, each coupled to an output of one of the first adders; and a second adder coupled to outputs of the plurality of resampling interpolators. Each of the processing branches includes: (a) a sampling/quantization circuit; and (b) a digital bandpass filter coupled to an output of the sampling/quantization circuit. The digital bandpass filters in different ones of the plurality of processing branches have frequency responses that are centered at different frequencies, and the rate at which at least one of the sampling/quantization circuits operates is different than an overall output data rate of said apparatus. Each of the resampling interpolators converts a first signal sample rate used by the sampling/quantization circuits in at least one of its corresponding processing branches to a second signal sample rate that is different than the first signal sample rate.
The foregoing structure permits decoupling of the sample-rate clock source from the conversion-rate clock source. Decoupling the sample-rate and conversion-rate clock sources enables a wide range of conversion rates to be supported using: (1) a high-precision, fixed-frequency clock source for sampling; or (2) a sample-rate clock source with an output frequency that is tunable over a limited range. The bandwidth of the digital filter again preferably determines the portion (i.e., sub-band) of the input signal spectrum that is converted by the associated processing branch, with the bandwidth of each digital filter preferably being selected to produce minimal spectral overlap with the digital bandpass filters of the other processing branches. The resampling interpolator converts a signal at its input, which has been sampled at a rate preferably determined by a precision clock source (i.e., the sample-rate frequency of the converter), to a signal at its output that has been sampled at a rate preferably determined by an independent data clock source (i.e., the conversion-rate frequency of the converter). Resampling in the digital domain allows the conversion-rate frequency of the converter to be independent of the sample-rate frequency of the converter.
Variations on the foregoing embodiment include a means for correcting errors caused by timing jitter. The preferred apparatus includes a sampling error detector having an output coupled to at least one of the resampling interpolators. The sampling error detector preferably outputs a control signal that: (1) tracks the frequency fluctuations at the output of sampling clock source, and (2) provides the resampling interpolator with information needed to resample the digital bandpass filter output in a manner that corrects for errors due to sampling uncertainty. More preferably, the output of the sampling error detector is a function of (e.g., proportional to) a difference between a rate at which at least one of the sampling/quantization circuits operates and a desired rate.
The foregoing summary is intended merely to provide a brief description of certain aspects of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.
In the following disclosure, the invention is described with reference to the attached drawings. However, it should be understood that the drawings merely depict certain representative and/or exemplary embodiments and features of the present invention and are not intended to limit the scope of the invention in any manner. The following is a brief description of each of the attached drawings.
The present disclosure is related in part to the disclosures set forth in U.S. Provisional Patent Application Ser. No. 61/501,284 (the '284 Application), filed on Jun. 27, 2011; U.S. Provisional Patent Application Ser. No. 61/439,733, filed on Feb. 4, 2011; U.S. patent application Ser. No. 12/985,238, filed on May 1, 2011; and U.S. patent application Ser. No. 12/824,171, filed on Jun. 26, 2010, all by the present inventor, and all titled “Sampling/Quantization Converters”. The foregoing applications are incorporated by reference herein as though set forth herein in full.
A preferred converter, which according to the present invention incorporates methods for reducing conversion errors caused by sampling uncertainty/jitter, is sometimes is referred to herein as being jitter-tolerant. A jitter-tolerant converter, according the preferred embodiments of the present invention, employs parallel processing with frequency-decomposition (i.e., slicing), and therefore shares some structural similarities with conventional frequency-interleaving converters, such as the FTC, HFB, and MBΔΣ converters described above. However, a jitter-tolerant converter according to the preferred embodiments of the present invention incorporates one or more distinct technological innovations to provide implementation and/or performance advantages compared to conventional approaches, such as: (1) conversion errors due to sampling uncertainty are reduced because the converter input signal is bandlimited by analog (i.e., continuous-time) filters prior to sampling and quantization (e.g., compared to MBΔΣ); (2) the complexity of the analog input filters is reduced because the bandwidth of the filters is appreciably wider than the portion of the input signal spectrum that is converted by the associated processing branch (e.g., compared to FTH and HFB); (3) conversion accuracy is relatively insensitive to the analog input filter responses because the passbands associated with the analog input filters of the various processing branches can be set to overlap significantly and arbitrarily (e.g., compared to FTH and HFB), allowing use of analog filters with standard frequency responses (e.g., Butterworth, Chebychev, Bessel or elliptic); (4) high-precision, fixed-frequency sample clock sources can be employed because resampling in the digital domain allows the converter conversion-rate frequency (i.e., the output data rate) to be independent of the converter sample-rate frequency (e.g., compared to FTH, HFB, and MBΔΣ); and (5) higher levels of sampling uncertainty can be tolerated because errors introduced by sampling uncertainty are corrected by resampling in the digital domain (e.g., compared to FTH, HFB, and MBΔΣ). At least some of such approaches can in some respects be thought of as using a unique and novel combination of several conventional techniques—frequency interleaving, digital resampling (interpolation), and bandpass filtering. As discussed in more detail below, the use of such approaches often can overcome the problems associated with sampling uncertainty in converters that process high-frequency input signals.
Simplified block diagrams of converters 100, 150, and 200 according to certain preferred embodiments of the present invention are illustrated in
In any event, in the present embodiments each such branch (e.g., branch 110, 120, 160, 170 or 180) primarily processes a different frequency band, and includes: (1) a sampling/quantization circuit (e.g., circuit 113 or 123); and (2) a digital reconstruction bandpass filter (e.g., bandpass filter 115 or 125). In addition, each of converters 100, 150, and 200 also includes at least one of: (1) an analog input (bandpass) filter; (2) a resampling interpolator; and (3) a sampling error detector. The digital reconstruction filter (e.g., bandpass filter 115 or 125) performs a frequency-decomposition function, such that the center frequency and bandwidth of each digital filter determines which portion of the input signal spectrum (i.e., sub-band) is converted by its associated processing branch (e.g., branch 110, 120, 160, 170 or 180). Therefore, the center frequency of the digital bandpass filter is preferably aligned with the center of the sub-band to be retrieved from the respective processing branch. Preferably, the passband of each digital bandpass filter does not significantly overlap with the passband of any of the other digital bandpass filters. More preferably: (1) the center frequency of each digital bandpass filter is equal to the center frequency of the desired sub-band; and (2) the passbands of the various digital bandpass filters overlap in a precisely minimal manner to form, what is referred to in the prior art as, a near-perfect, signal-reconstruction filter bank.
In the preferred embodiments of the present invention, the digital bandpass filters form a near-perfect, signal-reconstruction filter bank so that the signal reconstruction process introduces negligible amplitude and group delay distortion at the converter output. Specifically, minimum amplitude and group delay distortion occurs when the overall digital filter bank response is all-pass. The overall response of the digital filters is all-pass when, for gk(n) being the impulse response of the digital bandpass filter in the kth processing branch,
where a and b are constants, such that
over the converter passband (i.e.
where fS is the converter sample frequency). Furthermore, the bandwidths of the digital reconstruction filters in all of the processing branches are equal in the preferred embodiments, such that the converter sub-bands are uniformly spaced across the Nyquist bandwidth ΩB of the converter. Therefore, for a signal-reconstruction filter bank comprised of M filters, each digital filter preferably has a noise bandwidth of
where N is the excess-rate oversampling ratio of the converter given by
However, in alternative embodiments the converter sub-bands are non-uniformly spaced and the noise bandwidths of the digital reconstruction filters in each of the processing branches are not equal.
Embodiments Employing an Analog Input (Bandpass) Filter
A first representative embodiment of the present invention is the jitter-tolerant converter circuit 100, illustrated in
It should be noted that since the bandwidth of the analog filter exceeds the bandwidth of the digital frequency-decomposition filter, the sample-rate frequency of the sampling/quantization circuits (e.g., circuits 113 and 123) in the preferred embodiments is greater than twice the bandwidth of the sub-band intended to be converted by a given processing branch (i.e., the sampling/quantization circuits oversample the signal at their inputs). Therefore, the analog bandpass filters do not perform a conventional anti-aliasing function (i.e., the analog filters do not perform the same anti-aliasing function as in FTH converters, where processing branch inputs are bandlimited to the bandwidth of the associated sub-band). It should be noted further that, due to overlapping bandwidths, the analog bandpass filters in the preferred embodiments do not perform a conventional frequency-decomposition (i.e., signal analysis) function in the sense that the bandwidths of the analog filters (e.g., filters 112 and 122) do not define the converter sub-bands, as in FTH and HFB converters. Instead an appreciably wider (preferably by a factor of 1.25, 1.5, 2, 2.5 or more) analog filter bandwidth, relative to the bandwidth of the digital filters (e.g., filters 115 and 125), ensures that: (1) the interaction between the analog bandpass filters and the digital bandpass filters is weak; and (2) the near-perfect signal reconstruction (i.e., signal synthesis) and frequency-decomposition (i.e., signal analysis) properties of the digital filter bank are not significantly affected by the presence of the analog input filters. Therefore, since the analog input filters are not integral to the frequency-decomposition function, the analog filters preferably have standard responses, such as Butterworth, Chebychev, Bessel or elliptic responses, that can be realized via passive means (e.g., LC lattice, coupled resonator, distributed element, etc.) or active means (e.g., Sallen-Key, cascaded integrator, voltage-controlled voltage-source, etc.). To minimize potential degradation to the signal reconstruction process performed by the digital bandpass filters, the analog bandpass filters in each of the processing branches preferably have matched insertion loss and matched propagation delay over the portion of the analog filter passband that coincides with the total passband of each converter sub-band. Insertion loss and propagation delay matching can be realized using conventional attenuators and delay elements, respectively.
Although as described above, the analog input filters do not perform conventional anti-aliasing or frequency-decomposition functions in the preferred embodiments of the present invention, the analog input filters (e.g., filters 112 and 122) enable the representative converter circuit 100, shown in
where Hk(jω) corresponds to the frequency response of the analog input filter with impulse response hk(t), and ωk is the center frequency of the kth processing branch such that ωk+1−ωk−1>>BN. Although “brick wall” filters of this type are not physically realizable, a description of the circuit in this context is sufficient to allow those skilled in the art to comprehend the operation of circuit 100 with standard filter responses. Assuming infinite converter resolution (i.e., number of rounding levels Q→∞) and a sinusoidal input signal x(t)=Am·sin(ωmt+φm), with arbitrary amplitude Am, arbitrary phase φm, and arbitrary angular frequency ωm, the output of each analog input filter yk is
The sampled sequence at the output of each converter ŷk is given by
where the sampling interval T=1/fS and φ is a white, Gaussian noise sequence produced by sampling jitter (uncertainty) having power σφ2 and power spectral density N0 (i.e., N0=σφ2/ΩB). The output samples z of the converter are
where the “*” operator represents linear convolution according to u(t)*v(t)=∫u(t−τ)·v(τ)dτ. For the case where |φ|<<1, z(n)=Am·sin(ωmT·n+φm)+[Am·cos(ωmT·n+φm)·(ωm·φ)]*gm(n), resulting in an overall noise power at the converter output equal to
which is a factor of 1/M times lower than the noise level at the output of a conventional converter that does not employ interleaving in frequency with analog bandpass filtering. In general, the lower output noise level improves converter resolution by 10·log10(1/M)/6 bits for a sinusoidal input.
For a jitter-tolerant converter according to the representative embodiment of circuit 100, sampling time uncertainty generally introduces less noise into the converter output by an amount that depends on both the bandwidth (ΩS) of the input signal and the noise bandwidth B′N of the analog input filters. It can be shown that for ΩS<B′N, the noise power caused by timing jitter is reduced by a factor of ΩB/B′N at the converter output, compared to a conventional converter that does not combine interleaving in frequency with analog bandpass filtering. Conversely, for ΩS≈ΩB (i.e., the input signal occupies nearly the entire Nyquist bandwidth of the converter), the converter output noise caused by sampling jitter is reduced by a negligible amount. For example, representing a broadband input signal as the sum of M sinusoids, such that
results in analog input filter outputs of
and sampled output sequences ŷk given by
ŷk(n)=Ak sin(ΩkT·n+φn+ωk·φ).
For |φ|<<1, the output samples z of the converter are
and the output noise power is
which is the same as that for a conventional converter. Compared to a conventional converter without frequency interleaving and analog bandpass filtering, therefore, circuit 100 exhibits better jitter tolerance for narrowband input signals, and comparable jitter tolerance for wideband input signals.
As shown in
Embodiments Employing at Least One Resampling Interpolator
A second representative embodiment of a jitter-tolerant converter, according to the present invention, is circuit 150 illustrated in
The sample-rate clock sources (e.g., 111A, 121A and 131A) are preferably precision, fixed-frequency oscillators, having a design that emphasizes stable, low jitter operation over the capability for tuning over a wide range of output frequencies. More preferably, each such sample-rate clock source is the low jitter oscillator circuit described in the '003 Application. The digital bandpass filter in each processing branch operates at the sample-rate frequency for the corresponding processing branch, which preferably is greater than or equal to the conversion-rate frequency (i.e., the frequency of data clock input 103) of the converter. In the representative embodiment of circuit 150, the resampling interpolators 119A and 139A preferably “resample” their corresponding input signals 118 (i.e., the combined output of adder 105) and 138 (the output of single bandpass filter 135), respectively, to compensate for the difference between the corresponding sample-rate frequency or frequencies (fS) and the desired conversion-rate frequency (fCLK). In other representative embodiments, however, the resampling interpolator(s) also compensate for the effects of sampling errors, approximating a condition of perfect sampling (as discussed in more detail in the Embodiments Also Employing At Least One Sampling Error Detector section below).
In addition to providing a frequency-decomposition function, the digital bandpass filters in the preferred embodiments perform a bandlimiting function that is integral to the resampling operation. For sufficient bandlimiting, the relationship between a sampled output value at one sample-time instant and a sampled output value at an offset sample-time instant (i.e., offset between sample-time interval 1/fS and conversion-time interval 1/fCLK) is well approximated, over a sample-time interval, by a linear or parabolic function. Specifically, the accuracy of the parabolic approximation depends on: (1) the total number of processing branches M; (2) the excess-rate oversampling ratio N (defined above); and (3) the number of processing branches Kj associated with the jth resampling interpolator (i.e., the jth resampling interpolator is coupled to the combined output of Kj of the M processing branches). More specifically, for a combined digital filter output with noise bandwidth Kj·BN≈ΩB·Kj/(N·M), the accuracy of the parabolic approximation improves logarithmically according to the ratio Kj/(N·M), such that for every factor of two decrease in the ratio Kj/(N·M), the accuracy (ε) of the approximation improves by a factor of about 4, or
In the preferred embodiments, digital resampling is based on a parabolic interpolation with a ratio
accuracy of at least 0.5% (i.e., 7.5 effective bits). More preferably, digital resampling is based on a parabolic interpolation with a ratio
to ensure a resampling accuracy of better than 0.1% (i.e., 10 effective bits). In alternate embodiments, however, digital resampling can be based on linear or nonlinear (e.g., sinusoidal or cubic spline) interpolation between sampled output values, and a different Kj/(N·M) ratio.
An exemplary resampling interpolator 119A or 139A, according to the preferred embodiments of the present invention, is circuit 400A shown in
In general, the operation of preferred accumulator 415 is somewhat similar to that of a conventional numerically-controlled oscillator (NCO). Referring to circuit 400A, accumulator output 490 (i.e., interpolant Δn) is the modulo-sum of input 475, such that accumulator output 490 increments (or decrements) by an amount equal to the value of input 475, until a terminal value is reached. When a terminal value is reached, accumulator output 490 overflows (i.e., wraps) to a value equal to the difference between the resultant accumulated output value and the terminal value. Preferably, the terminal value of accumulator 415 is unity (i.e., terminal value equals 1), and the value (df) at accumulator input 475 is determined by the ratio of sample-rate frequency fS to desired conversion-rate frequency fCLK, according to the equation:
In the preferred embodiments, the ratio fS/fCLK is rational, a condition that occurs when fS and fCLK are multiples of a common reference frequency fREF, such that for integers a, b, c, and d:
In general, the above condition is not difficult to achieve using conventional frequency synthesis methods (e.g., direct-digital synthesis or factional-N PLL synthesis) and ensures that there is a finite-precision value df for which FIFO 405 does not overflow (or underflow). For the specific case where fS/fCLK= 5/4, and therefore df=¼, the first seven values at output 490 (i.e., interpolant Δn) of accumulator 415 are 0, ¼, ½, ¾, 0, 0, and ¼. In this particular example, accumulator output 490 transitions from a value of ¾ to a value of 0 when the accumulated result reaches the terminal value of 1, and the duplicate value of 0 results from accumulator overflow signal 460 that disables accumulation for a single cycle (i.e., via multiplexer 430).
The output 490 (i.e., interpolant Δn) of accumulator 415 determines the amount by which the value (i.e., magnitude) of data inputs 402 are adjusted to reflect a different sample time. In the preferred embodiments, this magnitude adjustment is based on digital interpolation using a second-order, polynomial (i.e., parabolic) curve fit, that in a least-squares sense, minimizes the error between the data samples and the fitted second-order polynomial. Such second-order interpolation is realized using interpolation filter 401, that for input value y and output value z, performs the function
where Δn is the curve-fit interpolant (i.e., an independent, control variable that specifies the offset between a given sample-time instant and a desired sample-time instant). With respect to the above equation, negative interpolant values advance the sample-time instant (i.e., shift sampling to an earlier point in time) and positive interpolant values retard the sample-time instant (i.e., shift sampling to a later point in time). In alternate embodiments, however, the relationship between interpolant polarity and sample-time shift could be the opposite. It should be noted that since
the fitted curve error is zero (i.e., zi=yi) for an interpolant specifying a sample-time offset that coincides with an actual sample-time instant (e.g., Δ=0 and Δ=+1). In alternative embodiments of the invention, particularly converter applications where high-resolution performance is not critical (i.e., <<10-bit conversion accuracy), interpolation can be first-order, such that
zn=yn·(1+Δn)−yn-1·Δn.
For either first-order or second-order interpolation, the curve-fit interpolant Δn is time-varying, and preferably: (1) is generated using an accumulator 415 based on an input value 475 (i.e., as described above); and (2) accounts for differences in sample-rate frequency fS and conversion-rate frequency fCLK (i.e., via manual frequency control signal 480).
In the preferred embodiments, the ratio of sample-rate frequency to conversion-rate frequency (i.e., the ratio fS(fCLK) is rational. In alternate embodiments, however, the ratio fS/fCLK is irrational and resampling interpolator circuit 400B, illustrated in
Since data samples (i.e., input signal 402) are clocked into digital interpolation filter 401 at rate fS (i.e., via optional latch 412 in
Embodiments Also Employing at Least One Sampling Error Detector
A third representative embodiment of a jitter-tolerant converter, according to the present invention, is circuit 200 illustrated in
In the preferred embodiments, the sampling error detector 117 compares the output frequency (i.e., actual frequency) of the sample clock source 111B to a desired frequency (i.e., reference frequency), and produces an error signal 112 that is proportional to the difference between the actual frequency and the desired frequency. In the present embodiment, the error signal 112 is coupled to resampling interpolator 119B, along with the combined (i.e., via adder 105) output 108 of digital bandpass filters 115 and 125. The combined output 108 of these digital bandpass filters typically has been corrupted by sample-time uncertainty (jitter), and consequently, the resampling interpolator 119B does not directly pass on the jitter-corrupted data samples from the output of adder 105. Instead the resampling interpolator outputs, at a rate determined by data clock 103, an estimate of what would have been correct data samples (i.e., in the absence of sampling uncertainty) based on the error signal from the sampling error detector. In the representative embodiment of circuit 200, therefore, the resampling interpolator serves two purposes: (1) it compensates for the effects of sampling errors in order to approximate a condition of perfect sampling; and (2) it compensates for the difference between the actual instantaneous sample-rate frequency and the desired conversion-rate frequency. In conjunction, the sampling error detector circuit 117 and the resampling interpolator circuit 119B form a feed-forward control system for mitigating conversion errors due to sample-time jitter. As indicated, the entire subcircuit 201 can be substantially replicated any number of times, with each subcircuit including any number of processing branches and with the different subcircuits potentially using oscillators that operate at different frequencies, and the outputs of all such subcircuits are coupled into adder 106 in order to produce the final output signal 102.
The preferred sampling error detector 117, e.g., for use in representative circuit 200 shown in
and the corresponding output y of lowpass filter 508 is equal to
Thus, the signal level y at the output of frequency-discriminator circuit 500B is approximately proportional to the input frequency f0, with a constant of proportionality equal to 2πT. Preferred sampling error detector circuit 500A has some similarities to the conventional frequency-discriminator circuit 500B, but instead of producing an output level that is proportional to the input frequency, the present sampling error detector produces an output level that is proportional to the difference (Δf) between a desired frequency f0 (determined by the amount of constant time delay provided by delay element 502A) and the actual frequency at the detector's input. In addition, because the sample error detector 500A preferably employs an edge-triggered phase-frequency detector 505A, comparable in operation to a conventional MC100EP40/140 from ON Semiconductor, the preferred sampling error detector of the present invention needs only a single delay element (e.g., circuit 502A in
Referring to circuit 500A in
Referring back to representative circuit 200 in
In the preferred embodiments, the resampling interpolator circuit 119B in
δ=k·(fS−f0).
For resampling at the desired rate f0, the automatic frequency control value AFC that is applied to the NCO 415 preferably is
In circuit 400C, the scaling term 1/(k·f0) is applied using multiplier 425, and the AFC value is combined with the MFC value using adder 426.
Digital Bandpass (Reconstruction) Filter Considerations
The primary considerations for the digital bandpass filters (e.g., filters 115, 125, and 135) according to the preferred embodiments of the present invention are: (1) design complexity (preferably expressed in terms of required multiplications and additions), (2) frequency response (particularly stopband attenuation), (3) amplitude and phase distortion, and (4) latency. The best converter-resolution and jitter-tolerance performance is obtained for digital bandpass filters having frequency responses that exhibit high stopband attenuation, which generally increases with increasing filter order. In addition, it is preferable for the digital bandpass filter responses to have suitable (e.g., perfect or near-perfect) signal-reconstruction properties to prevent conversion errors due to amplitude and phase distortion. Filter (i.e., amplitude and phase) distortion is a particularly important consideration because, unlike noise from quantization and jitter, filter distortion levels do not improve as filter order increases or as the number of parallel-processing branches M increases. Therefore, filter distortion prevents converter resolution from improving with increasing filter order or with increasing M. Also, although stopband attenuation generally increases with filter order, increases in filter order result in greater processing latency, especially for transversal, finite-impulse-response (FIR) filters. Digital bandpass filters with low latency are preferred to support applications where latency can be a concern, such as those involving control systems and servo mechanisms. For these reasons, the jitter-tolerant converter preferably employs bandpass moving-average (BMA) filters, which can result in: (1) high levels of stopband attenuation (i.e., attenuation of noise from quantization and jitter), (2) insignificant amplitude and phase distortion (i.e., near-perfect signal reconstruction), and (3) significantly lower complexity than other approaches.
For high-resolution converter applications (e.g., requiring up to 10 bits of conversion accuracy), the present inventor has discovered that conventional, transversal window filters (e.g., Blackman-Harris, Hann or Kaiser window filters) have suitable stopband attenuation and signal-reconstruction properties for two-sided bandwidths of ΩB/(N·M) and impulse-response lengths of 4·N·M, or less, where M is the number of processing branches and N is the excess-rate oversampling ratio
However, the present inventor has also discovered that recursive window filters are a preferable alternative to conventional, transversal FIR filter banks, because recursive window filters exhibit equivalent properties to transversal window filters, but typically can be implemented more efficiently, i.e., with fewer adds (adders or addition operations) and multiplies (multipliers or multiplication operations). For example, consider a lowpass prototype (i.e., zero-frequency-centered) filter with impulse response
where a0=0.35875, a1=0.48829, a2=0.14128, a3=0.01168, and L=4·(N·M−1). This filter response, which is defined in the prior art as a Blackman-Harris window filter response, realizes signal-to-distortion power ratios (SDR) of greater than 84 dB (i.e., 14-bit resolution). As significantly, this filter has a recursive transfer function equal to
which requires only 10 multiply operations for lowpass filtering, regardless of the filter impulse response length L. Additional multiplication operations are required for transforming the lowpass prototype response to a bandpass response, using downconversion followed by upconversion, but the recursive window filters still represent a considerable complexity savings over the transversal FIR approaches used in conventional filter banks. However, the present inventor has discovered that when recursive window filters of this form are implemented using high-frequency, parallel-processing methods, such as polyphase decomposition, the complexity costs associated with coefficient dynamic range expansion can exceed any complexity savings afforded by the recursive structure.
Bandpass moving-average (BMA) filters are used in the preferred embodiments of the invention, instead of conventional transversal window filters or recursive window filters, because BMA filters feature high stopband attenuation and negligible amplitude and phase distortion, in conjunction with low complexity. A block diagram of an exemplary BMA filter 300 is given in
The BMA equalizer, shown as a complex, single-tap filter 367 in
The moving-average prototype filters 368 utilized in the bandpass moving-average (BMA) filters preferably have the general transfer function
where filter parameters R, Pi and pi are integers, and the exponent −2·N·M/Pi is also an integer. This moving-average prototype filter has a one-sided, 3 dB bandwidth
where fS is the filter sample-rate frequency (i.e., the converter sample-rate frequency), M is the number of processing branches, and N is the converter excess-rate oversampling ratio defined above. Therefore, the one-sided bandwidth of the moving-average prototype filter is inversely proportional to N, and for M filters (i.e., M processing branches), the overall, two-sided bandwidth of the composite BMA filter bank is fS/N for Pi=1. The center frequency of each BMA filter is determined directly by the period of the sine and cosine sequences used for quadrature downconversion, and preferably is set to coincide with the center of the sub-band intended to be converted by the corresponding processing branch.
The complexity of the moving-average filter prototype increases as the number of cascaded stages S increases, and therefore, S which is given by
is preferably small, e.g., S≦3. The stopband attenuation of the BMA filter bank increases with increasing prototype filter impulse response length, L, given by
The amplitude and phase distortion introduced by the BMA filter bank is minimized (i.e., maximum SDR) for prototype filter impulse responses of length L≦4·N·M−1, where as before, M is the number of processing branches and N is the converter excess-rate oversampling ratio. Thus, for maximum converter resolution, the prototype filter parameters R, Pi and pi preferably result in a prototype filter of length L=4·N·M−1, or as close to that as possible. However, stopband attenuation is not a one-to-one function of L. Specifically, some L-length prototype moving-average filters realize greater stopband attenuation than other L-length prototype moving-average filters. More preferably, therefore, the three BMA prototype filter parameters are optimized, for example using trial-and-error or a conventional constrained optimization method, such that both signal-to-distortion ratio (SDR) and stopband attenuation meet the minimum levels needed to achieve a specified converter resolution (e.g., combined SDR and stopband attenuation preferably exceeding ˜60 dB for 10-bit resolution)
Besides exhibiting near-perfect reconstruction properties and realizing high levels of stopband attenuation, cascaded moving-average prototype filters can be very low in complexity because they require no multiplication operations. For example, the 3-stage (i.e., S=3) prototype filter transfer function given by
requires only 6 additions, independent of filter length (L=4·N˜M−2), plus 4·M+3 registers. With these moving-average prototype filters, the only multiplication operations required are those necessary for transforming lowpass responses to bandpass responses. Bandpass transformation based on quadrature downconversion and upconversion, as shown in
xn=−2 cos(ω0)·xn-1+xn-2
yn=−sin(ω0)·xn-1−2 cos(ω0)·yn-1+yn-2.
Although bandpass moving-average (BMA) filters based on cascaded moving-average filter prototypes, such as filter 368 described above, generally are preferred because such structures provide a substantial savings in computational complexity, particularly for large M (i.e., M≧8), the conventional, transversal FIR filter bank and transversal window filter approaches can provide equal or less complexity for small M.
System Environment
Generally speaking, except where clearly indicated otherwise, all of the systems, methods, functionality and techniques described herein can be practiced with the use of one or more programmable general-purpose computing devices. Such devices typically will include, for example, at least some of the following components interconnected with each other, e.g., via a common bus: one or more central processing units (CPUs); read-only memory (ROM); random access memory (RAM); input/output software and circuitry for interfacing with other devices (e.g., using a hardwired connection, such as a serial port, a parallel port, a USB connection or a FireWire connection, or using a wireless protocol, such as Bluetooth or a 802.11 protocol); software and circuitry for connecting to one or more networks, e.g., using a hardwired connection such as an Ethernet card or a wireless protocol, such as code division multiple access (CDMA), global system for mobile communications (GSM), Bluetooth, a 802.11 protocol, or any other cellular-based or non-cellular-based system, which networks, in turn, in many embodiments of the invention, connect to the Internet or to any other networks; a display (such as a cathode ray tube display, a liquid crystal display, an organic light-emitting display, a polymeric light-emitting display or any other thin-film display); other output devices (such as one or more speakers, a headphone set and a printer); one or more input devices (such as a mouse, touchpad, tablet, touch-sensitive display or other pointing device, a keyboard, a keypad, a microphone and a scanner); a mass storage unit (such as a hard disk drive or a solid-state drive); a real-time clock; a removable storage read/write device (such as for reading from and writing to RAM, a magnetic disk, a magnetic tape, an opto-magnetic disk, an optical disk, or the like); and a modem (e.g., for sending faxes or for connecting to the Internet or to any other computer network via a dial-up connection). In operation, the process steps to implement the above methods and functionality, to the extent performed by such a general-purpose computer, typically initially are stored in mass storage (e.g., a hard disk or solid-state drive), are downloaded into RAM and then are executed by the CPU out of RAM. However, in some cases the process steps initially are stored in RAM or ROM.
Suitable general-purpose programmable devices for use in implementing the present invention may be obtained from various vendors. In the various embodiments, different types of devices are used depending upon the size and complexity of the tasks. Such devices can include, e.g., mainframe computers, multiprocessor computers, workstations, personal (e.g., desktop, laptop, tablet or slate) computers and/or even smaller computers, such as PDAs, wireless telephones or any other programmable appliance or device, whether stand-alone, hard-wired into a network or wirelessly connected to a network.
In addition, although general-purpose programmable devices have been described above, in alternate embodiments one or more special-purpose processors or computers instead (or in addition) are used. In general, it should be noted that, except as expressly noted otherwise, any of the functionality described above can be implemented by a general-purpose processor executing software and/or firmware, by dedicated (e.g., logic-based) hardware, or any combination of these, with the particular implementation being selected based on known engineering tradeoffs. More specifically, where any process and/or functionality described above is implemented in a fixed, predetermined and/or logical manner, it can be accomplished by a processor executing programming (e.g., software or firmware), an appropriate arrangement of logic components (hardware), or any combination of the two, as will be readily appreciated by those skilled in the art. In other words, it is well-understood how to convert logical and/or arithmetic operations into instructions for performing such operations within a processor and/or into logic gate configurations for performing such operations; in fact, compilers typically are available for both kinds of conversions.
It should be understood that the present invention also relates to machine-readable tangible (or non-transitory) media on which are stored software or firmware program instructions (i.e., computer-executable process instructions) for performing the methods and functionality of this invention. Such media include, by way of example, magnetic disks, magnetic tape, optically readable media such as CDs and DVDs, or semiconductor memory such as PCMCIA cards, various types of memory cards, USB memory devices, solid-state drives, etc. In each case, the medium may take the form of a portable item such as a miniature disk drive or a small disk, diskette, cassette, cartridge, card, stick etc., or it may take the form of a relatively larger or less-mobile item such as a hard disk drive, ROM or RAM provided in a computer or other device. As used herein, unless clearly noted otherwise, references to computer-executable process steps stored on a computer-readable or machine-readable medium are intended to encompass situations in which such process steps are stored on a single medium, as well as situations in which such process steps are stored across multiple media.
The foregoing description primarily emphasizes electronic computers and devices. However, it should be understood that any other computing or other type of device instead may be used, such as a device utilizing any combination of electronic, optical, biological and chemical processing that is capable of performing basic logical and/or arithmetic operations.
In addition, where the present disclosure refers to a processor, computer, server device, computer-readable medium or other storage device, client device, or any other kind of device, such references should be understood as encompassing the use of plural such processors, computers, server devices, computer-readable media or other storage devices, client devices, or any other devices, except to the extent clearly indicated otherwise. For instance, a server generally can be implemented using a single device or a cluster of server devices (either local or geographically dispersed), e.g., with appropriate load balancing.
Additional Considerations.
To improve overall conversion accuracy, the present invention can incorporate any combination of: (1) analog input filters to reduce the level of output noise introduced by sampling uncertainty; (2) resampling interpolators to compensate for the sample-time offsets introduced by sampling uncertainty; and (3) precision, fixed-frequency oscillators to reduce the fluctuations in sample-rate frequency that produce sampling uncertainty. An exemplary jitter-tolerant converter that incorporates all three of the above components, according to a representative embodiment of the invention, is circuit 250 illustrated in
Furthermore, to simplify the distribution of a continuous-time input signal to the various processing branches of a converter according to the representative embodiments of the invention, the analog input filters may be grouped in combinations of two (i.e., conventional diplexers), three (i.e., conventional triplexers), or more. Exemplary circuit 600, illustrated in
As used herein, the term “coupled”, or any other form of the word, is intended to mean either directly connected or connected through one or more other processing blocks, e.g., for the purpose of preprocessing.
In the event of any conflict or inconsistency between the disclosure explicitly set forth herein or in the attached drawings, on the one hand, and any materials incorporated by reference herein, on the other, the present disclosure shall take precedence. In the event of any conflict or inconsistency between the disclosures of any applications or patents incorporated by reference herein, the more recently filed disclosure shall take precedence.
Several different embodiments of the present invention are described above, with each such embodiment described as including certain features. However, it is intended that the features described in connection with the discussion of any single embodiment are not limited to that embodiment but may be included and/or arranged in various combinations in any of the other embodiments as well, as will be understood by those skilled in the art.
Similarly, in the discussion above, functionality sometimes is ascribed to a particular module or component. However, functionality generally may be redistributed as desired among any different modules or components, in some cases completely obviating the need for a particular component or module and/or requiring the addition of new components or modules. The precise distribution of functionality preferably is made according to known engineering tradeoffs, with reference to the specific embodiment of the invention, as will be understood by those skilled in the art.
Thus, although the present invention has been described in detail with regard to the exemplary embodiments thereof and accompanying drawings, it should be apparent to those skilled in the art that various adaptations and modifications of the present invention may be accomplished without departing from the spirit and the scope of the invention. Accordingly, the invention is not limited to the precise embodiments shown in the drawings and described above. Rather, it is intended that all such variations not departing from the spirit of the invention be considered as within the scope thereof as limited solely by the claims appended hereto.
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