A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit.
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1. A method for manufacturing a multi-layer PCB, comprising:
forming a first conductive pattern layer and a second conductive pattern layer on upper and lower surfaces of a first insulating layer, respectively;
forming a first hole for receiving a first integrated circuit in the first insulating layer by removing the first conductive pattern layer of a predetermined area;
arranging the first integrated circuit in the first hole so that a lower surface of the first integrated circuit makes direct contact with the second conductive pattern layer without an insulating layer therebetween;
stacking a second insulating layer and a third conductive pattern layer on the first conductive pattern layer and an upper surface of the first integrated circuit;
attaching an adhesive tape on the second conductive pattern layer of a predetermined area for receiving a second integrated circuit;
stacking a third insulating layer and a fourth conductive pattern layer on the second conductive pattern layer including the adhesive tape;
cutting the fourth conductive pattern layer and the third insulating layer along a rim of the adhesive tape;
forming a second hole for receiving the second integrated circuit in the third insulating layer by taking off the adhesive tape so that the third insulating layer and the fourth conductive pattern layer, which are disposed at the upper part of the adhesive tape, are simultaneously removed;
arranging the second integrated circuit in the second hole in such a manner that a lower surface of the second integrated circuit makes direct contact with the second conductive pattern layer without an insulating layer therebetween;
stacking a fourth insulating layer and a fifth conductive pattern layer on the fourth conductive pattern layer and an upper surface of the second integrated circuit; and
forming a plurality of contact-holes in the second insulating layer and the fourth insulating layer so as to allow inter-layer electric connection.
3. The method as claimed in
4. The method as claimed in
stacking a fifth insulating layer, a sixth insulating layer, a sixth conductive pattern layer, and a seventh conductive pattern layer, respectively, on a lower part of the second insulating layer and an upper part of the fourth insulating layer; and
forming a plurality of contact-holes in the fifth insulating layer and the sixth insulating layer so as to allow inter-layer electric connection.
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This application claims the benefit of the earlier filing date, pursuant to 35 USC 119(a), to that patent application entitled “PCB Having Embedded IC And Method For Manufacturing The Same,” filed in the Korean Intellectual Property Office on May 4, 2007 and assigned Serial No. 2007-43755, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a multi-layer printed circuit board (multi-layer PCB), and more particularly to a PCB having an embedded integrated circuit (IC) and method for manufacturing the same.
2. Description of the Related Art
A printed circuit board (PCB) has been employed in various electric appliances. Particularly, a multi-layer PCB having a structure including insulating layers and conductive patterns layer repeatedly and alternately stacked on each other has been applied to electric appliances of super-slimness/super-small size, such as a portable terminal, a desktop computer, etc.
As shown in
However, the conventional multi-layer PCB has only one embedded integrated circuit, and cannot have a plurality of embedded integrated circuits.
However, the conventional multi-layer PCB as shown in
However, the conventional multi-layer PCB as shown in
The present invention provides a PCB having an embedded integrated circuit, which can realize size-reduction as well as slimness of the PCB when more than two integrated circuits are embedded therein.
Also, the present invention provides a PCB having an embedded integrated circuit, which can realize size-reduction as well as slimness of the PCB when more than two integrated circuits are embedded therein.
In accordance with an aspect of the present invention, a multi-layer PCB includes: a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-holes formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit. The multi-layer PCB further includes a conductive pattern layer disposed between a lower surface of the first integrated circuit and a lower surface of the second integrated circuit. The first insulating layer is a core insulating layer.
In accordance with another aspect of the present invention, a method of manufacturing a multi-layer PCB, includes forming a first conductive pattern layer and a second conductive pattern layer on upper and lower surfaces of a first insulating layer, respectively, forming a first hole for receiving a first integrated circuit in the first insulating layer by removing the first conductive pattern layer of a predetermined area for receiving the first integrated circuit and the first insulating layer; arranging the first integrated circuit in the first hole in such a manner that a lower surface of the first integrated circuit makes contact with the second conductive pattern layer; stacking a second insulating layer and a third conductive pattern layer on the first conductive pattern layer and an upper surface of the first integrated circuit; attaching an adhesive tape on the second conductive pattern layer of a predetermined area for receiving a second integrated circuit; stacking a third insulating layer and a fourth conductive pattern layer on the second conductive pattern layer including the adhesive tape; cutting the fourth conductive pattern layer and the third insulating layer along a rim of the adhesive tape; forming a second hole for receiving the second integrated circuit in the third insulating layer by removing the adhesive tape, the third insulating layer formed on the adhesive tape, and the fourth conductive pattern layer; arranging the second integrated circuit in the second hole in such a manner that a lower surface of the second integrated circuit makes contact with the second conductive pattern layer; stacking a fourth insulating layer and a fifth conductive pattern layer on the fourth conductive pattern layer and an upper surface of the second integrated circuit; and forming a plurality of contact-holes in the second insulating layer and the fourth insulating layer so as to allow inter-layer electric connection.
The core insulating layer may be material of FR4, and the second to fourth insulating layers may be made from an ajinomoto build-up film (ABF).
The method of manufacturing a multi-layer PCB further includes: stacking a fifth insulating layer, a sixth insulating layer, a sixth conductive pattern layer, and a seventh conductive pattern layer on a lower part of the second insulating layer and an upper part of the fourth insulating layer; and forming a plurality of contact-holes in the fifth insulating layer and the sixth insulating layer so as to allow inter-layer electric connection.
In accordance with another aspect of the present invention, a method of manufacturing a multi-layer PCB includes the steps of: forming a first conductive pattern layer on an upper surface of a first insulating layer, and then forming a first hole for receiving a first integrated circuit on the first insulating layer by removing the first conductive pattern layer of a predetermined area for receiving the first integrated circuit and the first insulating layer; attaching a first adhesive tape having a size equal to a size of a predetermined area for receiving a second integrated circuit on a lower surface of the first insulating layer so as to block off the first hole; arranging the first integrated circuit in the first hole in such a manner that a lower surface of the first integrated circuit is attached to the first adhesive tape; stacking a second insulating layer and a third conductive pattern layer on the first conductive pattern layer and an upper surface of the first integrated circuit; stacking a third insulating layer and a third conductive pattern layer on the second conductive pattern layer including the first adhesive tape; cutting the third conductive pattern layer and the second insulating layer along a rim of the first adhesive tape; forming a second hole for receiving the second integrated circuit in the third insulating layer by removing the first adhesive tape, the third insulating layer formed on the first adhesive tape, and the third conductive pattern layer; arranging the second integrated circuit in the second hole in such a manner that a lower surface of the second integrated circuit makes contact with a lower surface of the first integrated circuit; stacking a fourth insulating layer and a fourth conductive pattern layer on the third conductive pattern layer and an upper surface of the second integrated circuit; and forming a plurality of contact-holes in the second insulating layer and the fourth insulating layer so as to allow inter-layer electric connection.
The method of manufacturing a multi-layer PCB further includes: stacking a fifth insulating layer, a sixth insulating layer, a fifth conductive pattern layer, and a sixth conductive pattern layer on a lower part of the second insulating layer and an upper part of the fourth insulating layer; and forming a plurality of contact-holes in the fifth insulating layer and the sixth insulating layer so as to allow inter-layer electric connection.
The above and other aspects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
Exemplary embodiments of the present invention are now described with reference to the accompanying drawings. For the purposes of clarity and simplicity, a detailed description of known functions and configurations incorporated herein will be omitted as it may make the subject matter of the present invention rather unclear.
Referring to
The integrated circuits 110 and 120 have a plurality of connection bumps 111 and 121 for electric connection to external devices and insulating layers 112 and 122 formed on an upper surface thereof. The integrated circuits 110 and 120 are stacked while having a conductive pattern layer 141 formed between them. At this time, the integrated circuits 110 and 120 are arranged in such a manner that rear surfaces (the other surfaces) of the respective integrated circuits face each other.
In the multi-layer PCB 100 according to the present embodiment, two insulating layers 130 and 132, which have embedded integrated circuits 110 and 120, respectively, are stacked adjacently to each other while having a conductive pattern layer 141 disposed between them. Therefore, the multi-layer PCB 100 can have a smaller thickness in comparison with a structure including two core insulating layers stacked while having a conventional conductive layer disposed between them.
The third insulating layer 132 can be formed through a typical lamination process, for example, through deposition of an insulating layer made from an ajinomoto build-up film (ABF). The third conductive pattern layer 142 is coated by a copper foil, and then can be patterned through a typical photolithography process, similar to the first and second conductive pattern layers 140 and 141.
Referring to
The integrated circuits 210 and 220 have a plurality of connection bumps 211 and 221 for electric connection to external devices and insulating layers 212 and 222, which are formed on an upper surface thereof. The integrated circuits 210 and 220 are stacked in such a manner that rear surfaces (surfaces of the other side) of the respective integrated circuits make contact with each other.
In the multi-layer PCB 200 according to the present embodiment, two integrated circuits 210 and 220 are stacked in such a manner that their rear surfaces make contact with each other so that they are arranged in an insulating mono-layer (referred to as an insulating mono-layer because a conductive pattern layer isn't interposed between the insulating layers 230 and 232 and two insulating layers make contact with each other). Therefore, the multi-layer PCB 200 has a smaller thickness in comparison with a conventional structure including an integrated circuit arranged in two core insulating layers and an insulating layer interposed between the two layers.
While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the number of embedded integrated circuits, the number or material of insulating layers and conductive pattern layers can be changed as necessary. Accordingly, the scope of the invention is not to be limited by the above-described embodiments but by the claims and the equivalents thereof.
As described above, in the multi-layer PCB according to an embodiment of the present invention, because two insulating layers having an embedded integrated circuit, are stacked adjacently to each other while having a conductive pattern layer disposed between them, the multi-layer PCB can be a smaller thickness thereof in comparison with a conventional structure including two core insulating layers stacked while having a conductive layer disposed between them.
Moreover, in the multi-layer PCB according to another embodiment of the present invention, because two integrated circuits are stacked in such a manner that respective rear surfaces thereof make contact with each other so as to be arranged in an insulating mono-layer, it can be possible to further reduce the thickness of the multi-layer PCB in comparison with a conventional structure where an integrated circuit is arranged in two core insulating layers, and then an insulating layer is interposed between them
Furthermore, in a method for manufacturing a multi-layer PCB according to the present invention, an easily attachable or detachable adhesive tape is attached on the lower part of a predetermined area for receiving an integrated circuit, an insulating layer and a conductive pattern layer are formed thereon, and then the insulating layer formed on the adhesive tape and the conductive pattern layer are removed through a lift-off process. Therefore, a hole for receiving an integrated circuit can be easily formed.
Choi, Youn-Ho, Seo, Ho-Seong, Cho, Shi-yun
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