In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted.
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1. A method comprising:
performing timing analysis on a circuit including a standard cell using timing parameters that include a margin budgeted for a voltage drop in the cell;
extracting, on a computer, parasitic impedances for power and ground connections in the cell;
characterizing, on the computer, the cell with the parasitic impedances;
comparing, on the computer, timing of the cell with the parasitic impedances to timing of the cell without the parasitic impedances; and
identifying, on the computer, the cell for power and ground connection refinement responsive to detecting timing differences that exceed a threshold in the comparing, and wherein the threshold is based on an amount of timing impact budgeted as the margin for the voltage drop in the cell.
5. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed:
determine one or more first timing parameters for a cell, including effects of parasitic impedances on a power supply grid within the cell;
determine one or more second timing parameters for the cell, excluding effects of parasitic impedances on the power supply grid;
compare the one or more first timing parameters to the one or more second timing parameters;
perform timing analysis on a circuit including the cell using third timing parameters that include a margin for a voltage drop in the cell; and
determine whether or not the cell requires refinement responsive to a result of the compare, wherein the cell requires refinement if a difference between at least one of the first timing parameters and a corresponding one of the second timing parameters exceeds the margin in a corresponding one of the third timing parameters that is budgeted for the voltage drop in the cell.
19. A non-transitory computer accessible storage medium storing:
a first cell model corresponding to a first cell, the first cell model excluding power parasitic impedances;
a second cell model corresponding to the first cell, the second cell model including power parasitic impedances extracted from a layout of the first cell;
a plurality of instructions which, when executed:
determine a first delay through the first cell responsive to the first cell model;
determine a second delay through the first cell responsive to the second cell model;
determine that the second delay exceeds the first delay by an amount that is greater than a second amount budgeted for an effect of the power parasitic impedances, wherein the second amount is applied to a third delay used for timing analysis of a circuit that includes the first cell; and
identify the first cell for modification of a power grid associated with the first cell responsive to determining that the second delay exceeds the first delay by the amount that is greater than the second amount.
13. A computer system comprising:
at least one processor configured to execute instructions; and
a non-transitory computer accessible storage medium coupled to the at least one processor, the computer accessible medium storing:
a characterization tool;
an extraction tool; and
a program which, when executed by the at least one processor:
invokes the characterization tool to characterize a plurality of cells with an ideal power supply;
invokes the extraction tool to extract power parasitic impedances from the plurality of cells;
invokes the characterization tool to characterize a plurality of cells including the power parasitic impedances; and
identifies which of the plurality of cells are to be refined responsive to differences in one or more timing parameters generated by the characterization tool using the ideal power supply and with the power parasitic impedances, wherein which of the plurality of cells are to be refined are those for which the differences in the one or more timing parameters exceed a predetermined margin used for timing impacts of a voltage drop in the cell, wherein the predetermined margin is applied to second timing parameters used for performing timing analysis on a circuit that includes the cell.
17. A method comprising:
simulating, on a computer, a first model of a circuit, wherein the first model includes parasitic impedances on signal connections and an ideal power supply;
determining, on the computer, a first set of delays through the circuit responsive to simulating the first model;
extracting, on the computer, power parasitic impedances;
simulating, on the computer, a second model of the circuit, wherein the second model includes the power parasitic impedances and connections to ideal power supplies at points on a power grid corresponding to the circuit at which the circuit is coupled to a global power supply grid of an integrated circuit;
determining, on the computer, a second set of delays through the circuit responsive to simulating the second model;
comparing, on the computer, the first set of delays and the second set of delays; and
identifying the circuit for additional design work responsive to the comparing wherein the identifying is performed responsive to a difference between a first delay in the first set and the second set exceeding a threshold, and wherein the threshold is based on a margin added to the delay for voltage drop on the power supply grid, wherein the margin is applied to a third set of delays used for timing analysis of another circuit that includes the circuit.
2. The method as recited in
extracting parasitic impedances for signal connections within the cell; and
characterizing the cell without the parasitic impedances on the power and ground connections but with the parasitic impedances on the signal connections to determine timing of the cell without the parasitic impedances on the power and ground connections.
3. The method as recited in
modifying a design of the cell; and
repeating the extracting, the characterizing, and the comparing on the modified design.
4. The method as recited in
6. The non-transitory computer accessible storage medium as recited in
7. The non-transitory computer accessible storage medium as recited in
8. The non-transitory computer accessible storage medium as recited in
9. The non-transitory computer accessible storage medium as recited in
10. The non-transitory computer accessible storage medium as recited in
11. The non-transitory computer accessible storage medium as recited in
characterize the cell over a plurality of circuit simulations of the cell with the parasitic impedances, the plurality of simulations applying a set of stimulus vectors to the cell and varying conditions of the cell.
12. The non-transitory computer accessible storage medium as recited in
14. The computer system as recited in
15. The computer system as recited in
16. The computer system as recited in
18. The method as recited in
20. The non-transitory computer accessible storage medium as recited in
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1. Field of the Invention
This invention is related to the field of timing methodologies for integrated circuit development and, more particularly, to measuring IR drop on power supply interconnect.
2. Description of the Related Art
The design of an integrated circuit, from concept to “tape out” (i.e. the transmission of the data describing the integrated circuit to the fabrication foundry), is a complex series of parallel, interdependent processes such as logic design, circuit design, synthesis, timing analysis, place and route, verification, etc. To successfully fabricate an integrated circuit that performs as specified, all of the various processes must be completed as accurately as possible.
Many integrated circuit design methodologies rely on synthesis using “standard cell” circuits for significant portions of the design. A standard cell may be a predesigned circuit (including layout and interconnection of the transistors used to form the circuit). The standard cell may be instantiated in the integrated circuit and connected to other instantiations of standard cells to implement a block described in a hardware design language (HDL). The same standard cell may be instantiated as many times as desired to realize various functionality in the blocks that form an integrated circuit. Standard cells may be more briefly referred to herein as “cells.” Typically, a library of standard cells are designed and provided for synthesis. The library can include a variety of logic gates and somewhat more complex functions that are expected to occur frequently in the design. Multiple cells may be defined for a given function, with each cell having a different drive strength. The multiple cells provide the ability to trade off size for speed in the synthesis step.
One of the challenges with standard cells is the correct determination of delay in the cells under various operating conditions. The delays are used for timing analysis, and thus must be as accurate as possible (and conservative where accuracy might be questionable). For example, a maximum delay parameter for a standard cell must be at least as large as the actual delay of the corresponding circuitry after fabrication (or larger). If the maximum delay parameter were shorter than the actual delay, the block would appear to meet timing during the design but would fail to operate properly when fabricated.
One of the factors that affect the timing of standard cells is the amount of voltage drop on power and ground connections in the cell. The voltage drop is the result of resistance in power/ground network and the combined current of all transistors in the cell drawing current on the grid at any particular time. Accordingly, the drop is often referred to as the IR drop (current (I) multiplied by resistance (R)). To ensure IR drop is within the allocated IR budget for timing analysis, industry standard IR analysis tools are often used. For standard cells, static peak IR flow is used. Static peak IR flow assumes the worst case scenario of all transistors in the entire cell being turned on at the same time. This approach is too pessimistic in many cells. For example, in complex or multiple stage cells, static peak IR flow is overly pessimistic because timing differences between stages are not taken into account. In another example, if transistors within the cell are separated by inverting logic, the transistors and nets separated by inverting stages are mutually exclusive.
In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances (e.g. parasitic resistance and parasitic capacitance), extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted.
The following detailed description makes reference to the accompanying drawings, which are now briefly described.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to.
Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph six interpretation for that unit/circuit/component.
Overview of Standard Cell Circuits
Turning now to
As shown in
Similarly, the power supply interconnect (e.g. wires 14 in
The output of the inverter formed by the transistors T1 and T2 (i.e. the node to which the drains of the transistors T1 and T2 are connected) is coupled to the gate terminals of the transistors T3 and T4. Accordingly, the interconnect between the transistors T1-T4 may be part of the local interconnect within the cell 10. The interconnection between the transistors T1-T4 may be implemented, e.g., at the poly layer, the metal 1 layer, the metal 2 layer, or any combination thereof. Another input (not shown in
Various resistors and capacitors shown in
The parasitic impedances illustrated in
Ideal voltage sources 44 are shown in
An ideal voltage source may be a voltage source that has zero impedance and infinite current capability, in one embodiment. While actual voltage sources cannot achieve the ideal, various design techniques may be used to reduce source impedances and increase current capabilities to levels that approximate the ideal for the loads that are experienced in a given circuit.
It is noted that, while the parasitic capacitances are illustrated in
As mentioned above,
IR Drop Methodology
The effects of IR drop on the timing of the cell 10 may be measured using simulations of the models illustrated in
From the results of the simulations, the characterization tool may establish various timing parameters for the cell 10. The timing parameters may include, for example, delay parameters describing the delay from a transition on each input to a corresponding transition on the output. The delay parameters may include intrinsic delay, as well as additional delay dependent on the slew rate of the input signal. There may be minimum delay (MinDelay) and maximum delay (MaxDelay) parameters for the cell 10 as a whole and/or for each input to each output. The MinDelay may be the shortest delay for a given input to the output over all the characterization simulations. Similarly, the MaxDelay may be the longest delay for the given input to the output over all the characterization simulations.
To measure the effect of IR drop on the cell 10, the characterization results of the cell 10 from
If the difference in timing parameters is large enough, the IR drop may be having too much of an effect on the performance of the cell 10 and it may be desirable to expend additional design effort on the design of the cell 10 to improve performance.
Specifically, the supply grids may be modified to reduce parasitic effects (e.g. widening wires, inserting more connections to the global supply grids, etc.). In one embodiment, a margin may be added to the power-parasitic-free delays to account for IR drop effects. That is, the margin may represent the amount of timing variation budgeted for IR drop effects due to the power parasitics. The modified delays including the margin may be used in timing analysis, for example. If the difference in a given timing parameter is larger than the margin, then the difference may be viewed as “large enough” to identify the cell for improvement/refinement. Other embodiments may implement other thresholds for when a cell's IR drop is large enough (e.g. a percentage of the supply voltage, a maximum absolute value of the drop, a minimum supply voltage, etc.).
The cell 10 as illustrated in
By using characterizations of the cell 10 with and without the power parasitics, the effect of the power parasitics on circuit performance may be isolated and captured. Furthermore, the characterization is performed by simulation of the circuits, and thus the effect of the IR drop caused by the circuit parasitics may be more accurately captured as the difference between each timing parameter generated in the characterization that excludes the power parasitics and the corresponding timing parameter generated in the characterization that includes the power parasitics. As noted above, because the characterizations are exhaustive, each timing path may be evaluated for IR drop effects.
The IR drop measurement tool may characterize the cell 10 without the power parasitics (block 60). Particularly, in one embodiment, the IR drop measurement tool may invoke the characterization tool to characterize the cell, using a model that excludes the power parasitics (e.g.
The IR drop measurement tool may extract the parasitic impedances on the power supply grids (power and ground, or VDD and VSS) (block 62). Particularly, in one embodiment, the IR drop measurement tool may invoke the extraction tool to extract the power parasitics for the cell from the layout of the cell. The IR drop measurement tool may create a new cell model based on the cell model without the power parasitics, inserting the power parasitics and connecting ideal voltage supplies at the points at which the power and ground grids connect to the respective global grids (e.g. at the vias 20, 22, 24, 26, 28, 30, 32, and 34 in
The IR drop measurement tool may characterize the cell 10 with the power parasitics (block 66). Particularly, in one embodiment, the IR drop measurement tool may invoke the characterization tool to characterize the cell, using a model that includes the power parasitics (e.g.
The IR drop measurement tool may compare the set of timing parameters (i.e. comparing each timing parameter in one set with the corresponding timing parameter in the other set, such as MaxDelay compared to MaxDelay, MinDelay compared to MinDelay, etc.) (block 68). The comparison may include, e.g., subtracting the timing parameter from one set from the corresponding timing parameter from the other set to find a difference. If any of the timing parameters have a difference that exceeds a threshold (e.g. the margin for IR drop) (decision block 70, “yes” leg), the IR drop measurement tool may identify the cell as requiring improvement (block 72). The designer may refine the cell, attempting to improve the power/ground grids. The process of extracting the power parasitics, creating the new cell model including the power parasitics, characterizing the new cell model, and comparing timing parameters may be repeated on the refined design (blocks 62, 64, 66, 68, and 70). The process may be repeated until the timing parameters of the cell with power parasitics has timing parameters that do not differ from the timing parameters of the cell without power parasitics by more than the threshold.
It is noted that the threshold may be different for each timing parameter, in some embodiments. Other embodiments may use the same threshold, or subsets of timing parameters may have the same threshold. The threshold may be measured in any desired fashion (e.g. a specified amount of delay, a percentage of the delays, etc.). Generally, a tool as used above may be a program, which may include a set of instructions which, when executed on a computer, implement the operation described for the tool.
Computer Accessible Storage Medium and System
Turning now to
The computer accessible storage medium 200 in
The processor 212 is configured to execute instructions, including the instructions in the software described herein such as the tools 202, 204, and 206. In various embodiments, the processor 212 may implement any desired instruction set (e.g. Intel Architecture-32 (IA-32, also known as x86), IA-32 with 64 bit extensions, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). In some embodiments, the computer system 210 may include more than one processor.
The processor 212 may be coupled to the memory 214 and the peripheral devices 216 in any desired fashion. For example, in some embodiments, the processor 212 may be coupled to the memory 214 and/or the peripheral devices 216 via various interconnect. Alternatively or in addition, one or more bridge chips may be used to coupled the processor 212, the memory 214, and the peripheral devices 216.
The memory 214 may comprise any type of memory system. For example, the memory 214 may comprise DRAM, and more particularly double data rate (DDR) SDRAM, RDRAM, etc. A memory controller may be included to interface to the memory 214, and/or the processor 212 may include a memory controller. The memory 214 may store the instructions to be executed by the processor 212 during use, data to be operated upon by the processor 212 during use, etc.
Peripheral devices 216 may represent any sort of hardware devices that may be included in the computer system 210 or coupled thereto (e.g. storage devices, optionally including a computer accessible storage medium 200, other input/output (I/O) devices such as video hardware, audio hardware, user interface devices, networking hardware, etc.).
Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Klass, Edgardo F., Mehta, Anup S., Lau, Betty Y.
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