A charge pump circuit is disclosed. The charge pump circuit comprises a transfer capacitor receiving a first clock phase and a driving capacitor receiving a second clock phase, the second clock phase opposite to the first clock phase. The circuit includes a first switch coupling an input node to the transfer capacitor. The first switch being controlled by the driving capacitor. The circuit further includes a second switch coupling the input node to the driving capacitor. The second switch being controlled by the transfer capacitor. The circuit also includes a third switch coupling the transfer capacitor to an output node. The third switch being controlled by the driving capacitor. The third switch operating in phase opposition to the first switch. The circuit finally includes a charge storage capacitor coupled to the output node.
|
1. A charge pump circuit, comprising:
a transfer capacitor receiving a first clock phase;
a driving capacitor receiving a second clock phase, the second clock phase opposite to the first clock phase;
a first switch coupling an input node to the transfer capacitor, the first switch controlled by the driving capacitor;
a second switch coupling the input node to the driving capacitor, the second switch controlled by the transfer capacitor;
a third switch coupling the transfer capacitor to an output node, the third switch controlled by the driving capacitor, the third switch operating in phase opposition to the first switch;
a first diode coupled to the driving capacitor and the output node, the first diode clamping a voltage of the driving capacitor to the output node, thereby preventing the first, second and third switches from experiencing voltages in excess of their required voltage rating during discharge; and
a charge storage capacitor coupled to the output node, wherein during steady state operation the first diode conducts no current and is in an off state.
4. A charge pump system, comprising:
a plurality of charge pump stages coupled together;
wherein each of the stages comprises a transfer capacitor receiving a first clock phase; a driving capacitor receiving a second clock phase, the second clock phase opposite to the first clock phase; a first switch coupling an input node to the transfer capacitor, the first switch controlled by the driving capacitor; a second switch coupling the input node to the driving capacitor, the second switch controlled by the transfer capacitor; a third switch coupling the transfer capacitor to an output node, the third switch controlled by the driving capacitor, the third switch operating in phase opposition to the first switch; a first diode coupled to the driving capacitor and the output node, the first diode clamping a voltage of the driving capacitor to the output node, thereby preventing the first, second and third switches from experiencing voltages in excess of their required voltage rating during discharge; and a charge storage capacitor coupled to the output node, wherein during steady state operation the first diode conducts no current and is in an off state.
8. A mems system comprising:
a mems device; and
a charge pump coupled to the mems device, the charge pump comprising a plurality of stages, wherein each of the stages comprises a transfer capacitor receiving one of a first or second clock phase; a driving capacitor receiving the other of a first or second clock phase, the second clock phase opposite to the first clock phase; a first switch coupling an input node to the transfer capacitor, the first switch controlled by the driving capacitor; a second switch coupling the input node to the driving capacitor, the second switch controlled by the transfer capacitor; a third switch coupling the transfer capacitor to an output node, the third switch controlled by the driving capacitor, the third switch operating in phase opposition to the first switch; a first diode coupled to the driving capacitor and the output node, the first diode clamping a voltage of the driving capacitor to the output node, thereby preventing the first, second and third switches from experiencing voltages in excess of their required voltage rating during discharge; and a charge storage capacitor coupled to the output node; wherein during steady state operation the first diode conducts no current and is in an off state.
2. The charge pump circuit of
3. The charge pump circuit of
5. The charge pump system of
6. The charge pump system of
7. The charge pump system of
9. The mems system of
10. The mems system of
11. The mems system of
12. The mems system of
|
This application is related to U.S. patent application Ser. No. 13/071,374, filed on Mar. 24, 2011, entitled “HIGH-VOLTAGE MEMS APPARATUS AND METHOD”, which is incorporated herein by reference.
The present invention relates generally to integrated circuits and more particularly to the generation of boosted voltages using a charge pump circuit.
Many electronic systems rely on the use of boosted voltages in excess of a given supply voltage. For example, micro-electromechanical systems (MEMS) may use boosted voltage to bias a proof mass to improve the sensitivity of a MEMS sensor. In some cases, a boosted voltage may be used to supply a high-voltage driver to allow for application of increased electrostatic force to actuate a MEMS device.
A class of voltage boosters known as charge pumps provides elevated voltage depositing charge onto storage capacitors arranged in a sequential chain of individual pumping stages. Voltage is boosted to increasing levels along the chain, and voltages well in excess of the input supply can be produced. Desirable characteristics of charge pumps include low parasitics, high pumping efficiency and low ripple. It is also desirable to be able to generate large voltages without exceeding the breakdown voltage of the devices used in the charge pump chain. For compatibility with low-cost manufacturing processes, it is sometimes desirable to have charge pumps in which devices with comparatively low breakdown voltages may nonetheless be used in the individual pumping stages to produce very large output voltages. For example, in some situations it may be desirable to produce a bias voltage in excess of 20V using devices rated to only 2V. In such cases, a large number of stages may be employed to achieve the required voltage boosting ratio. Thus, to further minimize cost, it is desirable to minimize the number of components required for the individual charge pump stages.
Thus, there is a need for charge pumps providing high efficiency and low ripple in a manner compatible with the use of relatively low breakdown voltage components wherein the number of components required for each pumping stage is minimized. The present invention addresses such a need.
A charge pump circuit is disclosed. The charge pump circuit comprises a transfer capacitor receiving a first clock phase and a driving capacitor receiving a second clock phase, the second clock phase opposite to the first clock phase. The circuit includes a first switch coupling an input node to the transfer capacitor. The first switch being controlled by the driving capacitor. The circuit further includes a second switch coupling the input node to the driving capacitor. The second switch being controlled by the transfer capacitor. The circuit also includes a third switch coupling the transfer capacitor to an output node. The third switch being controlled by the driving capacitor. The third switch operating in phase opposition to the first switch. The circuit finally includes a charge storage capacitor coupled to the output node.
The present invention relates generally to generating boosted voltages using a charge pump. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
An exemplary charge pump 100 known in the art is illustrated in
The exemplary prior-art charge pump 100 of
The discussion of the embodiments of
Multiple stages according to the present invention may be cascaded to produce higher output voltages. An embodiment of the present invention shown in
A charge pump comprising a cascade of multiple stages as shown in
For testing the drive current capability of the charge pump, a cascoded arrangement of NMOS devices 620-624 is provided to convey a programmable test current supplied by current source 641 to the VBIAS node at the output of the cascade of N stages 601-604. The NMOS devices 621-624 sit within corresponding high-voltage isolation regions 631-634. By these means, the charge pump system may be tested without the need to directly observe the high voltage bias node.
It should be noted that none of the transistors used in the N-stages 601-604 or the controller circuitry 661 or the cascoded NMOS devices 620-624 are required to tolerate high voltages. The transistors used in the N-stages 601-604 are only required to tolerate terminal voltages as high as VDD. The high-voltage bias, VBIAS, is coupled to the controller through attenuator 671 so that the reduced attenuator output voltage is also within the voltage rating of the transistors used in controller 661. High-voltage isolation regions 611-614 and 631-634 ensure that parasitic diode breakdown to the common substrate 681 is also avoided. Advantageously, by these means a high-voltage bias for the MEMS device is provisioned without the need to employ transistors with a high voltage rating.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Shaeffer, Derek, Cagdaser, Baris
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
6091594, | Feb 18 1998 | NXP B V | Protection circuits and methods of protecting a semiconductor device |
6091657, | Jan 20 1999 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Integrated circuit having protection of low voltage devices |
6912082, | Mar 11 2004 | Palo Alto Research Center Incorporated | Integrated driver electronics for MEMS device using high voltage thin film transistors |
7176732, | Aug 28 2003 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM IMEC VZW , A BELGIUM CORPORATION | Device and method for increasing the operating range of an electrical circuit |
7382176, | Jan 17 2003 | TPO Hong Kong Holding Limited | Charge pump circuit |
7466189, | Feb 15 2006 | Renesas Electronics Corporation | Semiconductor integrated circuit |
7548365, | Jun 06 2007 | Texas Instruments Incorporated | Semiconductor device and method comprising a high voltage reset driver and an isolated memory array |
7656221, | Aug 28 2006 | Kabushiki Kaisha Toshiba | Booster circuit and voltage supply circuit |
20110018616, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 11 2013 | Invensense, Inc. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Date | Maintenance Schedule |
Aug 05 2017 | 4 years fee payment window open |
Feb 05 2018 | 6 months grace period start (w surcharge) |
Aug 05 2018 | patent expiry (for year 4) |
Aug 05 2020 | 2 years to revive unintentionally abandoned end. (for year 4) |
Aug 05 2021 | 8 years fee payment window open |
Feb 05 2022 | 6 months grace period start (w surcharge) |
Aug 05 2022 | patent expiry (for year 8) |
Aug 05 2024 | 2 years to revive unintentionally abandoned end. (for year 8) |
Aug 05 2025 | 12 years fee payment window open |
Feb 05 2026 | 6 months grace period start (w surcharge) |
Aug 05 2026 | patent expiry (for year 12) |
Aug 05 2028 | 2 years to revive unintentionally abandoned end. (for year 12) |