A method of decoding an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.
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10. A decoder circuit for decoding an encoded signal, comprising:
means for creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ; and
means for sampling the encoded signal using the decoding signal and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling.
1. A method of decoding an encoded signal, comprising:
receiving the encoded signal;
creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ;
sampling the encoded signal using the decoding signal; and
determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling.
21. An rfid tag including a decoder circuit for decoding an encoded signal, the decoder circuit comprising:
means for creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ; and
means for sampling the encoded signal using the decoding signal and determining a value of a plurality of decoded bits represented by the encoded signal based on the sampling.
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This application claims priority under 35 U.S.C. §119(e) from provisional U.S. patent application No. 61/522,072, filed Aug. 10, 2011, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention pertains to data encoding schemes, and, in particular, to a data encoding scheme and associated decoding method and device that does not employ a digital clock or system clock signal. The present invention also pertains to a counter-less shift register that may be employed in connection with the data encoding scheme of the present invention.
2. Description of the Related Art
In a wireless serial data transmission system, a data stream in the form of a series of binary symbols (e.g., 1s and 0s) is typically transmitted from a transmitter device to a receiver device by: (i) encoding the data stream and thereby generating an encoded data signal (by converting the series of binary symbols to an analog form according to an encoding scheme), (ii) transmitting the encoded data signal, from the transmitter device to the receiver using an appropriate modulation technique, (iii) receiving and demodulating the transmitted signal at the receiver device in order to obtain the original encoded data signal, and (iv) decoding the encoded data signal in the receiver device to extract/obtain the original data stream (the series of binary symbols) from the encoded signal. In current data transmission methods, the receiving device extracts/obtains the original data stream from the encoded signal using an explicit clock signal that is common to the transmitter device and the receiver device. The explicit clock signal is either separately generated using additional clock circuitry provided as part of the receiver device or extracted from the transmitted data.
For example, one type of prior art encoding technique is known as pulse width coding (PWC) or poise interval encoding (PIE). In PWC and PIE, each bit of data/binary symbol (e.g., each 1 and 0) is represented by an energy pulse having a certain duration. For instance, a 1 may be represented by a pulse having a width equal to 5 clock pulses and a 0 may be represented by a pulse having a width equal to 3 clock pulses. Thus, determining the number of clock pulses within each received, energy pulse enables that energy pulse to be decoded as either a binary 1 or a binary 0.
As another example, in Manchester encoding, the clock signal is provided within the code itself, allowing the clock to be extracted at the receiving end by sampling the received signal and counting the number of samples within each symbol received. This means that there must be a clock present at the receiver device that provides a sampling signal at a higher bit rate than the incoming data stream, which in turn leads to a high power requirement at the receiver device.
Power consumption is a major concern in many electronic systems. For example, power consumption is a major concern in UHF passive RFID tag systems, wherein the operating range of such systems mainly depends on the power consumption of the RFID tags. Many current UHF passive RFID tag systems employ PIE, wherein the tag includes a PIE decoder module. The PIE decoder module in known to consume a significant amount of power due to the fact, as described above, it uses a high frequency oscillator to determine the width of each portion of the encoded signal, in order to distinguish a 1 bit from a 0 bit.
There is thus a need for an encoding scheme and associated decoder module that eliminates the use of a high power consuming clock (e.g., a high frequency clock), thereby lower power consumption at the receiving end.
In one embodiment, a method of decoding an encoded signal is provided that includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling.
In another embodiment, a decoder circuit for decoding an encoded signal is provided that includes means for creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ, and means for sampling the encoded signal using the decoding signal and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling.
In still another embodiment, a method of encoding a data signal including a plurality of first symbols and a plurality of second symbols is provided that includes creating an encoded signal based on the data signal, wherein in the encoded signal each of the first symbols is represented by a first square wave having a first period Po and a first duty cycle Do and each of the second symbols is represented by a second square wave having a second period P1 and a second duty cycle D1, and wherein D1>Do and P1≧Po.
In yet another embodiment, a method of operating a shift register having n sequentially arranged storage positions comprising a first position, a last position and one or more intermediate positions between the first position and the last position is provided, wherein a bit array stored by the shift register will shift by one position each time that at new bit is loaded into the first position. The method includes causing the shift register to be in an initialization state wherein a first binary symbol is stored in the first position and a second binary symbol different than the first binary symbol is stored in each of the one or more intermediate positions and the last position, and determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.
These and other objects, features, and characteristics of the present invention, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the invention.
As used herein, the singular form of “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. As used herein, the statement that two or more parts or components are “coupled” shall mean that the parts are joined or operate together either directly or indirectly, i.e., through one or more intermediate parts or components, so long as a link occurs. As used herein, “directly coupled” means that two elements are directly in contact with each other. As used herein, “fixedly coupled” or “fixed” means that two components are coupled so as to move as one while maintaining a constant orientation relative to each other.
As used herein, the word “unitary” means a component is created as a single piece or unit. That is, a component that includes pieces that are created separately and then coupled together as a unit is not a “unitary” component or body. As employed herein, the statement that two or more parts or components “engage” one another shall mean that the parts exert a force against one another either directly or through one or more intermediate parts or components. As employed herein, the term “number” shall mean one or an integer greater than one (i.e., a plurality).
Directional phrases used herein, such as, for example and without limitation, top, bottom, left, right, upper, lower, front, back, and derivatives thereof, relate to the orientation of the elements shown in the drawings and are not limiting upon the claims unless expressly recited therein.
In one aspect, the present invention provides a low-power pulse width coding scheme and associated decoding method, and apparatus wherein a decoding mechanism is created from the encoded signal and is used to decode the encoded signal. This enables the decoding to be performed without the need for a high frequency clock signal, and thus reduces the power consumption of the decoder unit, in particular, as described in detail below, the decoding mechanism is created from the encoded signal by creating a decoding signal by delaying the encoded signal, preferably using only passive components in the form of a delay line or buffer or similar element. That decoding signal is then used to sample the encoded signal in order to decode the encoded signal. Thus, the low-power pulse width coding scheme of the present invention is an auto correlating scheme that reduces power consumption wherein the original encoded signal provides the decoding mechanism for the scheme.
The pulse width coding scheme of the present invention will now be described with reference to
In addition, according to an aspect of the pulse width coding scheme of the present invention. D0<<D1 and P0≦P1. In other words, the duty cycle D1 must be at least a predetermined amount greater than the duty cycle D0, and the period P1 must be greater than or equal to the period P0. The predetermined amount by which D1 must be greater than D0 will be determined based on the delay value (Δ) of the embedded buffer element in the design as in
In order to decode an encoded signal that was encoded using the scheme just described, a decoding signal is created by delaying the encoded signal by a time Δ, and the encoded signal is sampled using the decoding signal. In particular, as shown in
The present inventors implemented and tested an embodiment of the present invention (including an embodiment of decoder circuit 5) wherein P0=P1=25 μs, D0=0.4 ns, D1=20 μs, and Δ=0.5 ns. The present inventors also compared the performance of that embodiment to a conventional clocked PIE decoder. Post layout power simulation results were obtained using Cadence Encounter using 45 nm PTM library for 1.1 V VDD on Linux Platform. The post layout switching power consumption of the tested embodiment of the present invention was found to be 8.6 nW as compared to 2234 nW for the conventional clocked PIE decoder. Thus, the switching power consumption of the conventional clocked PIE decoder is about 260 times greater than the decoder of the present invention.
Referring to
In shift register 25, each storage position 30 may be implemented in the form of a suitable flip0flop, such that shift, register 25 comprises a cascade/chain of flip-flops in which the output of each flip-flop is connected to the data input of the next flip-flop in the chain. This will result in a circuit that shifts by one position the bit array stored in it each time that a new bit is loaded into the first position.
In addition, according to an aspect of the present embodiment, shift register 25 is provided with a unique reset/initialization condition, shown in
According to a further embodiment, counter-less shift register 25 may be used to store variable length data, i.e., data words having different lengths (e.g., different operations may be performed based on data length). For example, and without limitation, counter-less shift register 25 may be used to store data words having lengths n−1 (6 bits in the present example; data word “D5D4D3D2D1D0”) and n−2 (5 bits in the present example; data word “D4D3D2D1D0”). This is illustrated in
Thus, in the embodiment shown in
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” or “including” does not exclude the presence of elements or steps other than those listed in a claim. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. In any device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain elements are recited in mutually different dependent claims does not indicate that these elements cannot be used in combination.
Although the invention has been described in detail for the purpose of illustration based on what is currently considered to be the most practical and preferred embodiments, it is to be understood that such detail is solely for that purpose and that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover modifications and equivalent arrangements that are within the spirit and scope of the appended claims. For example, it is to be understood that the present invention contemplates that, to the extent possible, one or more features of any embodiment can be combined with one or more features of any other embodiment.
Mickle, Marlin H., Sai, Vyasa, Ogirala, Ajay
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