A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.
|
1. A device comprising:
a wiring board comprising a core layer and a wiring layer formed on the core layer;
a protective layer formed contacting the wiring layer and the core layer;
an element mounted on the wiring board over a portion of the wiring layer and over a portion of the protective layer so that the element is in vertical registration over the portion of the wiring layer and over the portion of the protective layer;
a pair of spacer members intervening between the portion of the wiring layer of the wiring board and the element to form a space therebetween and to support opposite ends of the element with the portion of the protective layer being located between the pair of spacer members; and
an encapsulation body filling the space and encapsulating the element on the wiring board,
wherein each of the pair of spacer members is located between a lower surface of the element and an upper surface of the portion of the protective layer.
9. A semiconductor device comprising:
a wiring board including an upper surface and a plurality of connection pads formed on the upper surface;
a passive element mounted over the upper surface of the wiring board via a pair of insulation spacer members supporting opposite ends of the passive element to form a space between the wiring board and the passive element and between the pair of insulation spacer members, and that is electrically connected to at least an associated one of the connection pads;
a semiconductor chip mounted over the upper surface of the wiring board, that is electrically connected to the associated one of the connection pads;
an encapsulating body formed on the upper surface of the wiring board to cover the passive element and the semiconductor chip, the space being filled with the encapsulating body; and
a solder member at each of the opposite ends of the passive element, such that each solder member electrically connects the passive element to the connection pads of the wiring board and completely covers the insulation spacer member.
14. A semiconductor device comprising:
a wiring board including an upper surface and a plurality of connection pads formed on the upper surface;
a protective layer formed contacting the contact pads and the upper surface of the wiring board;
a first pair of insulation spacer members provided on the wiring board;
a second pair of insulation spacer members provided on the wiring board, the second pair of insulation spacer members being substantially parallel to the first pair of insulation spacer members;
a first passive element bridged between the first pair of insulation spacer members to form a first space between the wiring board and the first passive element, the first passive element being electrically connected to the connection pads of the wiring board;
a second passive element bridged between the second pair of insulation spacer members to form a second space between the wiring board and the second passive element, the second passive element being electrically connected to the connection pads of the wiring board, and being substantially parallel to the first passive element; and
an encapsulating body formed on the wiring board to cover the first passive element, the second passive element, the first pair of insulation spacer members and the second pair of insulation spacer members, the first space and the second space being filled with the encapsulating body,
wherein, each of the first and second passive elements is in vertical registration over respective portions of the protective layer.
2. A device according to
further comprising a solder member which electrically couples the element to the wiring board and covers the spacer member, and
wherein the spacer member comprises a wire bump.
3. A device according to
further comprising a solder member which electrically couples the element to the wiring board and covers, at least partially, the spacer member, and
wherein the spacer member comprises an insulation support member.
4. A device according to
wherein the spacer member comprises an insulation support member.
5. A device according to
6. A device according to
8. A device according to
10. The semiconductor device according to
wherein the passive element and the semiconductor chip are in vertical registration over portions of the protective layer.
11. The semiconductor device according to
wherein each insulation spacer member is located between a lower surface of the passive element and an upper surface of the protective layer.
12. The semiconductor device according to
13. The semiconductor device according to
15. The semiconductor device according to
16. The semiconductor device according to
further comprising solder members which electrically couple each of the first and second passive elements to respective connection pads, each solder member at least partly covering a corresponding one of the insulation spacer members.
17. The semiconductor device according to
wherein each of the insulation spacer members are located between a lower surface of a corresponding one of the first and second passive elements and an upper surface of a corresponding one of the portions of the protective layer.
|
This application is based upon and claims the benefit of priority from Japanese patent application No. 2010-165000, filed on Jul. 22, 2010, the disclosure of which is incorporated herein in its entirety by reference.
This invention relates to a semiconductor device and a manufacturing method of the same.
The semiconductor device has an encapsulating body which covers a semiconductor chip mounted on a wiring board in order to protect the semiconductor chip.
There is a method called a mold array process (MAP) method as one of methods for encapsulating a semiconductor chip with encapsulation resin. According to the MAP method, encapsulation is executed collectively for a plurality of product formation areas arranged on a mother wiring board. After that, the mother wiring board is diced or cut into individual products along with an encapsulation body. Such a technique is disclosed in, for example, Japanese Laid Open Patent Publication No. 2001-044324 or No. 2001-044229.
In recent years, requirements to materialize SIP (System In Package) of semiconductor devices are increasing as size and thickness of electronic equipment is reduced. To meet such requirements, studies have been carried out for a semiconductor device including both of a semiconductor chip and a passive element in a package thereof. When the MAP method is employed to encapsulate a semiconductor device including both of a semiconductor chip and a passive element, the passive element is encapsulated with encapsulation body together with the semiconductor chip.
In the meantime, the passive element is coupled to a wiring line formed on a wiring board by solder. The solder is melted in a reflow process to couple the passive element to the wiring line. At this time, the passive element goes down toward the wiring board due to surface tension of the solder and weight of the passive element. As a result, a distance between the passive element and the wiring board becomes small, for example, to about 20 μm or less. Into such a small distance, it is hard for encapsulation resin to flow. Consequently, it is impossible to fill a space between the passive element and the wiring board with the encapsulation resin. Thus, voids are caused at the vicinity of the passive element in the encapsulation body. There is a possibility that these voids leads degradation of reliability of the semiconductor device.
This invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part.
In one embodiment, a device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the electronic element to form a space therebetween, and an encapsulation body filling the space and encapsulating the electronic element on the wiring board.
In another embodiment, a semiconductor device includes: a wiring board including an upper surface and a plurality of connection pads formed on the upper surface; a passive element mounted over the upper surface of the wiring board via a spacer member to form a space between the wiring board and the passive element, and that is electrically connected to at least an associated one of the connection pads; a semiconductor chip mounted over the upper surface of the wiring board, that is electrically connected to the associated one of the connection pads; an encapsulating body formed on the upper surface of the wiring board to cover the passive element and the semiconductor chip, the space being filled with the encapsulating body.
In still another embodiment, a semiconductor device includes: a wiring board including an upper surface and a plurality of connection pads formed on the upper surface; a first pair of spacer members provided on the wiring board; a second pair of spacer members provided on the wiring board, the second pair of spacer members being substantially parallel to the first pair of spacer members; a first passive element bridged between the first pair of spacer members to form a first space between the wiring board and the first passive element, the first passive element being electrically connected to the connection pads of the wiring board; a second passive element bridged between the second pair of spacer members to form a second space between the wiring board and the second passive element, the second passive element being electrically connected to the connection pads of the wiring board, and being substantially parallel to the first passive element; and an encapsulating body formed on the wiring board to cover the first passive element, the second passive element, the first pair of spacer members and the second pair of spacer members, the first and second space being filled with the encapsulating body.
The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
In
The wiring board 11 is a glassy epoxy substrate with a rectangular shape, for example. The wiring board 11 may have a core layer 111, wiring layers 112 and 113 provided on both sides of the core layer 111, and first protecting layers (or solder resists) 114 and 115 covering the first and the second surfaces of the wiring board 11. On a first (or upper) surface of the core layer 111, a plurality of connection pads 116 are provided to couple the passive elements 12 and the semiconductor chip 13 to wires of the wiring layer 112. On a second (or lower) surface of the core layer 111, a plurality of lands 117 are provided to couple the solder balls 16 mounted thereon to wires of the wiring layer 113. Through the core layer 111, vias 118 are provided to couple the wires of the wiring layer 112 on the first surface of the core layer 111 to the wires of the wring layer 113 on the second surface of the core layer 112.
The passive element 12 is a resistor, a capacitor, an inductor or the like. The passive element 12 has electrodes 121 and 122 at both ends thereof. The electrodes 121 and 122 are connected and fixed to the connection pads 116 of the wiring board 11 with the solder 15.
The wire bumps 14 are formed by means of a wire bonding machine (not shown), for example. The wire bumps 14 are provided on the connection pads 116, which are connected to the electrodes 121 and 122 of the passive element 12, and covered with the solder 15. A metal, such as Au or Cu, having a higher melting point than that of the solder 15 is used for material of the wire bumps 14 so that the wire bumps 14 do not melt in a reflow process for melting the solder 15. When the higher melting point metal is used for the material of the wire bumps 14, the wire bumps 14 do not melt even if the solder 15 melts. As a result, a distance between the passive element 12 and the wiring board 11 can be kept at the predetermined distance or more. That is, it is possible to keep a required height of a space between the passive element 12 and the wiring board 11 due to intervention of the wire bumps 14. A plurality of wire bumps 14 may be provided on each connection pad 116 to prevent the passive element 12 from tilting when the solder 15 melts. The predetermined distance is set so that molten resin used in the encapsulation process can flow easily into the space between the passive element 12 and the wiring board 11. Hence, the predetermined distance may vary according to the encapsulation process condition. Preferably, the predetermined distance, which is a distance between a surface of the first protect layer 114 and a surface of the passive element 12 facing to the first protect layer 114, is set to 20 μm or more.
The semiconductor chip 13 includes one or more semiconductor elements. The semiconductor chip 13 is fixed to the first surface of the wiring substrate 11 by means of the adhesive 16 in what is called faceup state. The adhesive 16 may be a die attach film (DAF) or insulation paste. The semiconductor chip 13 has electrode pads (not shown) that are electrically coupled to the connection pads 116 of the wiring substrate 11 by means of the bonding wires 17. As material of the bonding wires 17, Au or Cu is usable.
The encapsulation body 18 is made of insulation resin, e.g. epoxy resin. The encapsulation body 18 may be formed collectively by means of the MAP method for a plurality of products each of which is the semiconductor device 10. The encapsulation body 18 formed collectively is cut to divide the products into each one.
In the semiconductor device 10 according to the first embodiment, the wire bumps 14 keep the distance between the passive element 12 and the wiring board 11 higher than the predetermined distance. Accordingly, it is easy to remove residual of flux in a cleaning process after the reflow process for the solder 15. Moreover, it is easy to fill the encapsulation resin into the space between the passive element 12 and the wiring board 11 and it is possible to prevent or suppress occurrence of voids in the encapsulating process. Thus, reliability of the semiconductor device 10 is improved. In addition, because the passive element is protected by the encapsulation body 18, the reliability of the semiconductor device 10 is further improved. With this structure, in which the passive element is encapsulated together with the semiconductor chip, it is possible to implement a semiconductor device, such as a system in package (SIP), having a higher function.
Next, the description will be made about a manufacturing method of the semiconductor device 10 illustrated in
As illustrated in
In each of the product formation portions 23, wiring patterns (or wiring layers 112 and 113) are formed and their surfaces are covered with protect layers 114 and 115 (see
Referring to
First, as illustrated in
Next, as illustrated in
The passive elements 12 are mounted on the mother wiring board 20 so that the electrodes 121 and 122 of the passive elements 12 are positioned on the solder paste 33. Then, the solder paste 33 is heated to a predetermined temperature and molten in the reflow process. The molten solder paste forms fillets 35 (to be solder 15) as illustrated in
Then, flux cleaning is executed to remove the residual of the flux. Because the spaces are secured between the passive elements 12 and the mother wiring board 20, the result of the flux cleaning is good.
Next, as illustrated in
After that, the encapsulation body 18 is formed on the surface of the mother wiring board 20 by means of collective molding. Hereafter, referring to
A transfer molding apparatus may be used as a molding apparatus to form the encapsulation body 18. As illustrated in
Next, as illustrated in
Next, as illustrated in
In the cavity 53, the molten resin 60 flows straight on the whole. Because the passive elements 12 are arranged to have the longitudinal direction perpendicular to the sheet surface of
Next, as illustrated in
If any voids are in the encapsulation body 18, there is a possibility that reflow heating for mounting the solder balls 19 causes cracks due to the voids. According to the first embodiment, it is possible to prevent or suppress the occurrence of cracks because occurrence of the voids is prevented or suppressed as mentioned above. Therefore, it is possible to manufacture efficiently the semiconductor device including a semiconductor chip and a passive element(s) and having high reliability.
Next, as illustrated in
Next, referring to
The semiconductor device 80 of
The first protective layer 114 is formed on the first surface of the wiring board 11 except for predetermined areas. The predetermined areas includes an area facing to the passive element 12 in addition to the areas for the connection pads 116. It is desirable that the opening of the first protective layer 114 facing to the passive element 12 has a width (in a direction perpendicular to the sheet surface of
According to the second embodiment, the distance between the passive element 12 and the wiring board 11 is large in comparison with that of the semiconductor device 10 of the first embodiment. Consequently, occurrence of voids is further prevented or suppressed. In addition, even if the height of the wire bumps 14 is smaller than that of the semiconductor device 10 of the first embodiment, the distance between the passive element 12 and the wiring board 11 can be equal to that of the first embodiment. Therefore, it is possible to reduce the thickness of the semiconductor device.
Next, referring to
The semiconductor device 90 of
The second protective layers 91 are formed on the first protective layer to face parts of the passive element 12. The second protective layers 91 may be composed by the same material as the first protective layer 114. Alternatively, the second protective layers 91 may be different from the first protective layer 114 in material. At any rate, the second protective layers 91 only have to serve as the insulation support members. The second protective layers 91 may be formed along edges of the opening of the first protective layer 114 to widen the opening of the space formed between the passive element 12 and the wiring board 11 as large as possible. In such a case, the second protective layers 91 are adjacent to the solder 15 which is to be formed later.
According to the third embodiment, voids are prevented from being generated like the case of the semiconductor device 10 of the first embodiment. Because the semiconductor device 90 manufactured using the wiring board 11 on which the second protective layers 91 are previously formed as the spacer members, a step for securing the space between the passive element 12 and the wiring board 11 is unnecessary in an assembling process. In other words, it is possible to manufacture the semiconductor device having the predetermined distance or more between the passive element 12 and the wiring board 11 without addition of a new step to a related assembling process.
Although the invention has been described above in connection with several preferred embodiments thereof, it is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. For example, though the wire bumps 14 and the second protective layers 91 are illustrated as the spacer members in the embodiments mentioned above, insulation support members 101 may be provided on the connection pads 116 as illustrated in
Moreover, though the embodiments illustrate the semiconductor devices each of which has one semiconductor chip and two passive elements, the present invention is applicable to various semiconductor devices regardless of the number of components, such as semiconductor chips, passive elements and so on, included therein.
Furthermore, though the above mentioned embodiments illustrate the semiconductor devices of a ball grid array (BGA) type each of which has solder balls as the external terminals, the present invention is applicable to semiconductor devices of other types, such as a land grid array type having no solder ball or so.
Still furthermore, though the above mentioned embodiments illustrate the glassy epoxy substrate as the wiring board, another substrate, such as a flexible substrate including a polyimide base substance, a multilayer substrate or the like, is useable as the wiring board.
The whole or part of the exemplary embodiments disclosed above can be described as, but not limited to, the following supplementary notes.
(Supplementary Note 1) A method of manufacturing a device comprising:
providing a spacer member on a wiring board;
providing a solder member on the wiring board;
mounting an element on the wiring board by intervention of the spacer member to form a space between the element and the wiring board and to be electrically coupled to the wiring board via the solder member; and
encapsulating the element with an encapsulation body on the wiring board to fill the space.
(Supplementary Note 2) A method according to Supplementary Note 1, further comprising dicing the wiring board after the encapsulating, wherein
the wiring board comprises a plurality of product formation areas arranged on the wiring board, and
the product formation areas are individually separated by the dicing.
(Supplementary Note 3) A method according to Supplementary Note 1, wherein the spacer member comprises a wire bump.
(Supplementary Note 4) A method according to Supplementary Note 3, wherein the solder member covers the wire bump.
(Supplementary Note 5) A method according to Supplementary Note 3, further comprising removing a part of a protective layer formed on the wiring board before the providing the spacer member, the part of the protective layer including an area facing to the element.
(Supplementary Note 6) A method according to Supplementary Note 1, wherein the spacer member comprises an insulation support member.
(Supplementary Note 7) A method according to Supplementary Note 6, wherein the solder member covers the insulation support member.
(Supplementary Note 8) A method according to Supplementary Note 16, wherein the solder member is adjacent to the insulation support member.
(Supplementary Note 9) A method according to 1, further comprising mounting a semiconductor chip on the wiring board before the encapsulating.
(Supplementary Note 10) A method according to Supplementary Note 1, further comprising mounting a solder ball on a surface of the wiring board that is different from a surface on which the element is mounted.
(Supplementary Note 11) A method according to Supplementary Note 1, wherein the element is distant from the wiring board by 20 μm or more.
(Supplementary Note 12) A method according to Supplementary Note 1, wherein the encapsulating is executed by transfer molding.
(Supplementary Note 13) A device according to Supplementary Note 12, wherein the element is located along a direction intersecting with a filling direction of the encapsulating body.
Patent | Priority | Assignee | Title |
10117335, | May 25 2017 | Mitsubishi Electric Corporation | Power module |
11729915, | Mar 22 2022 | TACTOTEK OY | Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure |
Patent | Priority | Assignee | Title |
3303393, | |||
5764486, | Oct 10 1996 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Cost effective structure and method for interconnecting a flip chip with a substrate |
6492737, | Aug 31 2000 | Renesas Electronics Corporation | Electronic device and a method of manufacturing the same |
6610934, | May 31 2001 | Hitachi, Ltd. | Semiconductor module and method of making the device |
6791178, | Nov 30 2001 | Hitachi, Ltd. | Multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices |
20040125579, | |||
20040166608, | |||
20040262033, | |||
20050006442, | |||
20050051358, | |||
20050167815, | |||
20050253231, | |||
20060014055, | |||
20100314745, | |||
JP2000332394, | |||
JP2001044229, | |||
JP2001044324, | |||
JP2002359341, | |||
JP20046705, | |||
JP2005347476, | |||
JP62144393, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jun 28 2011 | HOSOKAWA, KOJI | Elpida Memory, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 026583 | /0921 | |
Jul 12 2011 | PS4 Luxco S.A.R.L. | (assignment on the face of the patent) | / | |||
Jul 26 2013 | PS4 LUXCO S A R L | ELPIDA MEMORY INC | SECURITY AGREEMENT | 032414 | /0261 | |
Jul 26 2013 | Elpida Memory, Inc | PS4 LUXCO S A R L | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032900 | /0568 | |
Aug 29 2013 | PS4 LUXCO S A R L | PS5 LUXCO S A R L | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 039818 | /0506 | |
Nov 12 2013 | PS5 LUXCO S A R L | LONGITUDE SEMICONDUCTOR S A R L | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 039793 | /0880 | |
Jul 31 2018 | LONGITUDE SEMICONDUCTOR S A R L | Longitude Licensing Limited | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 046865 | /0667 |
Date | Maintenance Fee Events |
Jul 29 2015 | ASPN: Payor Number Assigned. |
Apr 19 2018 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Apr 20 2022 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Date | Maintenance Schedule |
Oct 28 2017 | 4 years fee payment window open |
Apr 28 2018 | 6 months grace period start (w surcharge) |
Oct 28 2018 | patent expiry (for year 4) |
Oct 28 2020 | 2 years to revive unintentionally abandoned end. (for year 4) |
Oct 28 2021 | 8 years fee payment window open |
Apr 28 2022 | 6 months grace period start (w surcharge) |
Oct 28 2022 | patent expiry (for year 8) |
Oct 28 2024 | 2 years to revive unintentionally abandoned end. (for year 8) |
Oct 28 2025 | 12 years fee payment window open |
Apr 28 2026 | 6 months grace period start (w surcharge) |
Oct 28 2026 | patent expiry (for year 12) |
Oct 28 2028 | 2 years to revive unintentionally abandoned end. (for year 12) |