The present disclosure discloses methods and circuits to reduce power consumption of switching circuits comprising two or more units by applying charge sharing/reuse of capacitive loads between the units. The units are stacked in a way that, if an output potential of a unit is to be lowered and an output potential of a neighboring unit is to be lifted, a charge of the unit to be lowered is reused by transferring it to the unit to be lifted depending on input signals of the units. In case of input signals having an arbitrary relationship a storage unit is placed at a junction of two neighboring units to store the charge temporarily until a neighboring unit is to be lifted.
|
1. A method to reduce the power consumption of switching circuits by applying charge sharing/reuse on capacitive loads, the method comprising the steps of:
(1) providing a switching or logic circuitry comprising two or more units, wherein each unit has an output capacitive means; and
(2) stacking the units of the circuitry in a way that, if an output potential of an unit is to be lowered and an output potential of a neighboring unit is to be lifted, a charge of the unit to be lowered the charge flowing out of the output node of this unit is either used right away to lift the output node of a lower unit, or flows into a storage element for subsequent use, depending on input signals of the units.
13. A switching circuit configured to charge sharing/reuse of capacitive loads configured to lower signal range, comprising:
two or more switching circuit units stacked upon each other wherein each unit comprises:
two ports for input signals wherein each port is associated to a transistor,
two transistors, wherein each transistor has a gate connected to the associated port; and
an output capacitive means to store a charge depending upon a level of the input signals;
wherein the units are stacked in a way that, if an output potential of an unit is to be lowered the charge flowing out of the output node of this unit is either used right away to lift the output node of a lower unit, or flows into a storage element for subsequent use, depending on input signals of the units.
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
10. The method of
11. The method of
12. The method of
15. The switching circuit of
18. The switching circuit of
one or two generic device networks implemented for each stage of the circuit adapted each to providing a positive and/or a negative reference voltage for each stage of the circuit while the reference voltages allow a signal range of each stage of the circuit below the supply range of the circuit, wherein the reference voltages are constant and independent of currents flowing through the one or two generic device networks of each stage;
a DC biasing network biasing active devices of the circuit comprising biasing voltage sources providing biasing voltages as required and resistors providing impedances for biasing as required; and
an AC coupling network of capacitive means to couple AC signals of a stage to a neighboring stage;
wherein the DC biasing network and the AC coupling network are enabled to allow a signal range which may be lower than threshold voltages of the active devices of the circuit.
19. The switching circuit of
20. The switching circuit of
|
This application is related to the following Ser. No. 13/853,305, filing date Mar. 29, 2013 and is assigned to the same assignee. The content of this application is hereby incorporated by reference in their entirety.
The present document relates to electronic circuits. In particular, the present document relates to electronic circuits for signals whose information content lies in their frequency and whose characteristics have to be transferred to predominantly capacitive loads
There is a plethora of logic circuit families, CMOS logic families being the most prominent ones which are used to design digital circuitry (sequential/combinational) or to realize a digital buffer in the form of chain of inverters. The drawback of these families is the fixed value of the power gain, dictated by load and frequency. This is because in such arrangements, the voltage swing both at the input as well as at the output is fixed, non-scalable and equal to the full supply headroom. This is explained further by taking the simplest circuit in the digital world—the CMOS inverter which is also the basic building block of a digital buffer (attractive solution at lower technology nodes, because of speed and lower device parasitics).
A chain of inverters is usually used to drive large capacitive load (interconnections/logic) for the propagation of digital signals. A unit cell i.e. the CMOS inverter is shown in
Dynamic power in the form of charging and discharging of the load capacitor, CL dominates the overall power consumption (See Equation 1).
Pdyn=CL×V2swing×fop (1).
The voltage at the output Vswing swings from 0 to VDD, CL is a capacitive load and fop is the frequency of operation.
According to Equation (1), for a given load the dynamic power is a fixed number and cannot be optimized.
A principal object of the present disclosure is to achieve a degree of freedom in the determination of power gain in switching circuits.
A further principal object of the disclosure is to reduce the power consumption of switching circuits which is primarily dominated by the dynamic power given by Equation (1), by applying charge sharing/reuse for capacitive loads.
A further object of the disclosure is to realize a full family of logic circuits based on supply reduction and AC coupling concepts.
A further object of the disclosure is to realize amplifiers/attenuators, both digitally and analogically controlled, based on progression/modulation in the supply range from stage to stage.
In accordance with the objects of this disclosure a method to reduce the power consumption of switching circuits by applying charge sharing/reuse for capacitive loads has been achieved. The method disclosed comprises the steps of: (1) providing a switching or logic circuitry comprising two or more units, wherein each unit has an output capacitive means, and (2) stacking the units of the circuitry in a way that, if an output potential of an unit is to be lowered, the charge flowing out of the output node of this unit is either used right away to lift the output node of a lower unit, or flows into a storage element for subsequent use, depending on input signals of the units . . . .
In accordance with the objects of this disclosure a switching circuit configured to charge sharing/reuse of capacitive loads configured to lower signal range has been achieved. The switching circuit disclosed firstly comprises: two or more switching circuit units stacked upon each other wherein each unit comprises: two ports for input signals wherein each port is associated to a transistor, two transistors, wherein each transistor has a gate connected to the associated port, and an output capacitive means to store a charge depending upon a level of the input signals, wherein the units are stacked in a way that, if an output potential of an unit is to be lowered, the charge flowing out of the output node is either used right away to lift the output node of a lower unit, or flows into a storage element for subsequent use, depending on input signals of the units.
The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein
Methods and circuits to reduce power consumption of switching circuits by applying sharing/reuse for capacitive loads are disclosed.
A method of charge reuse disclosed achieves n-fold power saving, where n is the number of elements able to share the charge. The stacked unit cells or units are in the form as disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013. Key elements of the present disclosure briefly highlighted in the points below:
1. Stacking of Networks
The stacking of networks is performed of the form as disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013. The concept of stacking is illustrated in
Comparing the power needed to drive two loads of CL 22 and 23 each, the two-stacked topology requires Pdyn-bias/2 where Pdyn-bias is the total power consumed by the two non-stacked units to drive the loads individually. The power can be further reduced by stacking more units and reutilizing the charge again and again. Generalizing, to drive N×CL capacitive loads, Pstacked=Pdyn-bias/N where N is the number of units stacked and Pdyn-bias is the power needed to drive N×CL capacitive loads with N non stacked units. The number of units being stacked depends on the supply voltage and The PMOS/NMOS combinations, which is described in the next section.
Furthermore it should be noted that a stack of a number of “vertically” stacked units, as shown e.g. in
2. Adding a Storage Element Between Stacked Units
The concept of stacked units described above may be extended to signals in an arbitrary relationship (not necessarily differential or in quadrature) by placing a storage unit, e.g. a capacitor, at the junction of the two units as shown in
The above concept is not limited to inverters as drivers. As pointed out above items, the units can assume any format as disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013.
As disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013, the signal range of the units may be lowered below supply range by adding at least one generic device network to each unit, each generic device network comprising a voltage source. One generic device network may be connected to supply voltage in order to generate a positive reference voltage, which is lower than supply voltage and another generic device network may be connected to ground to generate a lower reference voltage that is higher than ground voltage. It should be noted that the voltages generated by voltage sources of the generic device networks are constant and independent of the currents flowing through them. Furthermore, as described in the Ser. No. 13/853,305, filing date Mar. 29, 2013, the signal range is decoupled from biasing voltages by providing a DC biasing network comprising biasing voltage sources providing biasing voltages as required and corresponding resistors providing impedances required and AC signal coupling of active devices of the circuit is provided by a capacitive network. The biasing of the active devices may also be used to achieve voltage swings below threshold voltages.
As also described in the Ser. No. 13/853,305, filing date Mar. 29, 2013, Pull-up networks (PU) and Pull-down (PD) networks are deployed. A Pull-Up network (PU) network is a combination of devices able to tie the output of a stage to an upper reference voltage and accordingly a Pull-Down network (PD) network is just a combination of devices able to tie the output of the stage to a lower reference voltage. Pull-Up really means “pull output to supply” and Pull-Down really means “pull output to ground”. However, in the circuits of the present disclosure “supply” and “ground” are not those of the system, but especially created ones using the voltage sources of the generic devices network generating the upper reference voltage and the lower reference voltage.
In regard of stacking the case of stacking, the concept as disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013 has been extended. With reference to
The operation principles of the key items described above are outlined here accompanied by some examples. As disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013, flexibility over the output swing of the switching unit can be achieved by applying an external bias. This enables stacking units on top of another.
Current Reuse/Stacking
The key element of the disclosure is best explained by referring to the simplest circuit possible, a CMOS inverter. With reference to the standard embodiment of this circuit shown in
When the NMOS transistor 42 of the upper unit is conducting, the PMOS transistor 43 of the bottom unit is also conducting (as the input signals are complimentary), thus creating an electrical path for the charge to flow into the bottom load 41. Hence the same power is required to drive twice the load in the case of a two-stacked configuration.
As stated before, the concept can be extended beyond differential signals by using a storage unit.
For the time interval t1, the charge from the load 40 of the top unit is stored in the storage capacitor 50 as the PMOS transistor 43 of the bottom unit is still not conducting. During the time interval t2, the PMOS 43 becomes conductive and allows the charge stored in the storage capacitor 50 between the two units to flow to the bottom load 41. The same will hold true for two signals with any phase relation as long as the storage unit 50 is there.
The concepts outlined above were described with inverters as example. They can be extended to any general pull-up and pull-down network combination as explained and defined in as disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013, As an example,
It can be seen that the NAND/NOR gates are arranged in a CMOS fashion with the external bias to boost its overdrive. With the help of the storage unit 60 and 61 at the junctions, these circuits enable charge reuse, thus saving power.
The concept of charge sharing is not limited to CMOS and stacking of units up to 2 levels. Any other semiconductor technology having three terminal devices in which a voltage between a controlling terminal and a reference allows/block charge flow from the other terminal to the reference terminal could be applied with the present disclosure.
The present disclosure can be extended beyond CMOS and stacking of 2 levels, based on the supply and transistor arrangement. The power may be reduced N times by stacking N units, as the charge is reutilized N times. The higher the supply and lower the threshold voltage Vth of a transistor (determined by the technology node), the more units can be stacked. The latter, that is the arrangement of the transistors, is explained by again taking the simple circuit of an inverter and can be extended to other switching circuits in a similar fashion. In
For example, in a 55 nm technology node a maximum of 8 drivers can be stacked today given VDD is 1.2 V, a peak differential swing of 150 mV at the output, threshold voltage Vth of approximate 400 mV and an input swing of 400 mV. It is shown in
A first step 90 depicts a provision of a switching or logic circuitry comprising two or more units, wherein each unit has an output capacitive means. The next step 91 shows stacking the units of the circuitry in a way that, if an output potential of an unit is to be lowered the charge flowing out of the output node of this unit is either used right away to lift the output node of a lower unit, or flows into a storage element for subsequent use, depending on input signals of the units.
It should be noted that, as disclosed in the Ser. No. 13/853,305, filing date Mar. 29, 2013, the switching circuits described in the present disclosure may be a base of a full family of logic circuits. This family may include combinational and sequential, i.e. including memory elements.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Patent | Priority | Assignee | Title |
10559419, | May 18 2018 | DIALOG SEMICONDUCTOR B V | Inductor arrangement |
11223335, | Jun 02 2017 | Board of Regents, The University of Texas System | Inverter stacking amplifier |
11799563, | Mar 24 2020 | IMEC VZW; Katholieke Universiteit Leuven, KU LEUVEN R&D | Method of generating ultrasound and ultrasound generator |
9252651, | Jun 29 2011 | OMNIVISION TDDI ONTARIO LIMITED PARTNERSHIP | High voltage driver using medium voltage devices |
Patent | Priority | Assignee | Title |
5859548, | Jul 31 1996 | LG Semicon Co., Ltd. | Charge recycling differential logic (CRDL) circuit and devices using the same |
5867040, | Jun 15 1995 | Kabushiki Kaisha Toshiba | Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor |
6009021, | Dec 25 1996 | Sharp Kabushiki Kaisha | MOS logic circuit with hold operation |
6559681, | Jul 11 2000 | PICONETICS INTELLECTUAL PROPERTY TRUST | Resonant logic and the implementation of low power digital integrated circuits |
7463073, | Nov 21 2005 | Samsung Electronics Co., Ltd. | Output driver |
8054111, | Dec 13 2004 | SEMICONDUCTOR ENERGY LABORATORY CO , LTD | Semiconductor device and electronic appliance using the same |
20020140458, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 15 2013 | ANCIS, MICHELE | DIALOG SEMICONDUCTOR B V | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 030472 | /0168 | |
Mar 15 2013 | TODI, RAHUL | DIALOG SEMICONDUCTOR B V | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 030472 | /0168 | |
Mar 29 2013 | Dialog Semiconductor GmbH | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
May 01 2018 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Apr 25 2022 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Date | Maintenance Schedule |
Nov 11 2017 | 4 years fee payment window open |
May 11 2018 | 6 months grace period start (w surcharge) |
Nov 11 2018 | patent expiry (for year 4) |
Nov 11 2020 | 2 years to revive unintentionally abandoned end. (for year 4) |
Nov 11 2021 | 8 years fee payment window open |
May 11 2022 | 6 months grace period start (w surcharge) |
Nov 11 2022 | patent expiry (for year 8) |
Nov 11 2024 | 2 years to revive unintentionally abandoned end. (for year 8) |
Nov 11 2025 | 12 years fee payment window open |
May 11 2026 | 6 months grace period start (w surcharge) |
Nov 11 2026 | patent expiry (for year 12) |
Nov 11 2028 | 2 years to revive unintentionally abandoned end. (for year 12) |