In some embodiments, a mass storage system may include a mass storage device having a plurality of memory channels, and a controller coupled to the mass storage device, wherein the controller is configured to control access to the mass storage device. For example, the controller may include code to determine a first vertical redirect budget for a first memory channel of the plurality of memory channels, revector defects in the first memory channel vertically within the first memory channel until the first vertical redirect budget is exceeded, and revector defects in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the first vertical redirect budget is exceeded. Other embodiments are disclosed and claimed.
|
11. A method of utilizing a mass storage device having a plurality of memory channels, comprising:
performing an evaluation of current defects from the plurality of memory channels to determine a first vertical redirect budget based on an average number of defects per memory channel;
automatically setting the first vertical redirect budget using the evaluation, wherein the first vertical redirect budget indicates a maximum amount of vertical revectors that are allowed for a first memory channel of the plurality of memory channels;
revectoring defective blocks in the first memory channel vertically within the first memory channel until the automatically set first vertical redirect budget is exceeded; and
revectoring defective blocks in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the automatically set first vertical redirect budget is exceeded, wherein defective blocks of at least one memory channel of the plurality of memory channels are revectored vertically within the at least one memory channel based on the average, and wherein defective blocks of at least one other memory channel of the plurality of memory channels are revectored horizontally outside of the at least one other memory channel based on the average.
1. A mass storage system, comprising:
a mass storage device having a plurality of memory channels;
a controller coupled to the mass storage device, wherein the controller is configured to control access to the mass storage device, and wherein the controller includes code to:
perform an evaluation of current defects from the plurality of memory channels to determine a first vertical redirect budget based on an average number of defects per memory channel;
automatically set the first vertical redirect budget using the evaluation, wherein the first vertical redirect budget is to indicate a maximum amount of vertical revectors that are allowed for a first memory channel of the plurality of memory channels;
revector defective blocks in the first memory channel vertically within the first memory channel until the automatically set first vertical redirect budget is exceeded; and
revector defective blocks in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the automatically set first vertical redirect budget is exceeded, wherein defective blocks of at least one memory channel of the plurality of memory channels are revectored vertically within the at least one memory channel based on the average, and wherein defective blocks of at least one other memory channel of the plurality of memory channels are revectored horizontally outside of the at least one other memory channel based on the average.
6. A processor-based system, comprising:
a processor;
a system memory coupled to the processor;
a mass storage device having a plurality of memory channels; and
code stored on the processor-based system to cause the processor-based system to utilize the mass storage device, wherein the code is configured to cause the processor-based system to:
perform an evaluation of current defects from the plurality of memory channels to determine a first vertical redirect budget based on an average number of defects per memory channel;
automatically set the first vertical redirect budget using the evaluation, wherein the first vertical redirect budget is to indicate a maximum amount of vertical revectors that are allowed for a first memory channel of the plurality of memory channels;
revector defective blocks in the first memory channel vertically within the first memory channel until the automatically set first vertical redirect budget is exceeded; and
revector defective blocks in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the automatically set first vertical redirect budget is exceeded, wherein defective blocks of at least one memory channel of the plurality of memory channels are revectored vertically within the at least one memory channel based on the average, and wherein defective blocks of at least one other memory channel of the plurality of memory channels are revectored horizontally outside of the at least one other memory channel based on the average.
2. The mass storage system of
3. The mass storage system of
4. The mass storage system of
determine the first vertical redirect budget further based on a number of all known defects from the plurality of memory channels, wherein the automatically set first vertical redirect budget is allowed to be used in its entirety to revector defective blocks.
5. The mass storage system of
automatically set a second vertical redirect budget using the evaluation, wherein the second vertical redirect budget is to indicate a maximum amount of vertical revectors that are allowed for a second memory channel of the plurality of memory channels;
revector defective blocks in the second memory channel vertically within the second memory channel until the automatically set second vertical redirect budget is exceeded; and
revector defective blocks in the second memory channel horizontally outside of the second memory channel within another memory channel of the plurality of memory channels after the automatically set second vertical redirect budget is exceeded.
7. The processor-based system of
8. The processor-based system of
a controller to provide a serial advanced technology attachment (SATA) compatible interface to the solid state drive.
9. The processor-based system of
determine the first vertical redirect budget further based on a number of all known defects from the plurality of memory channels, wherein the automatically set first vertical redirect budget is allowed to be used in its entirety to revector defective blocks.
10. The processor-based system of
automatically set a second vertical redirect budget using the evaluation, wherein the second vertical redirect budget is to indicate a maximum amount of vertical revectors that are allowed for a second memory channel of the plurality of memory channels;
revector defective blocks in the second memory channel vertically within the second memory channel until the automatically set second vertical redirect budget is exceeded; and
revector defective blocks in the second memory channel horizontally outside of the second memory channel within another memory channel of the plurality of memory channels after the automatically set second vertical redirect budget is exceeded.
13. The method of
providing a serial advanced technology attachment (SATA) compatible interface to the solid state drive.
14. The method of
determining the first vertical redirect budget further based on a number of all known defects from the plurality of memory channels, wherein the automatically set first vertical redirect budget is allowed to be used in its entirety to revector defective blocks.
15. The method of
automatically setting a second vertical redirect budget using the evaluation, wherein the second vertical redirect budget indicates a maximum amount of vertical revectors that are allowed for a second memory channel of the plurality of memory channels;
revectoring defective blocks in the second memory channel vertically within the second memory channel until the automatically set second vertical redirect budget is exceeded; and
revectoring defective blocks in the second memory channel horizontally outside of the second memory channel within another memory channel of the plurality of memory channels after the automatically set second vertical redirect budget is exceeded.
16. The mass storage system of
|
The invention relates to mass storage devices. More particularly, some embodiments of the invention relate to an apparatus and method for defect revectoring in a multi-channel mass storage device in an electronic system such as a processor-based system.
Many electronic systems benefit from the use of mass storage devices. In some electronic systems, driver software may be provided to utilize mass storage devices. Some electronic systems may utilize a solid state drive (SSD) as a mass storage device.
Various features of the invention will be apparent from the following description of preferred embodiments as illustrated in the accompanying drawings, in which like reference numerals generally refer to the same parts throughout the drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the invention.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of the invention. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the invention may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
With reference to
In some embodiments of the invention, the controller 14 may further include code to determine the first vertical redirect budget based on a number of all known defects from the plurality of memory channels. For example, the controller 14 may further include code to determine the first vertical redirect budget based on an average number of defects per memory channel. In some embodiments of the invention, the controller 14 may further include code to determine a second vertical redirect budget for a second memory channel of the plurality of memory channels, revector defects in the second memory channel vertically within the second memory channel until the second vertical redirect budget is exceeded, and revector defects in the second memory channel horizontally outside of the second memory channel within another memory channel of the plurality of memory channels after the second vertical redirect budget is exceeded. For example, the first and second vertical budgets may be the same for the first and second memory channels. For example, a single vertical budget may be determined and applied to each memory channel.
With reference to
The processor-based system 20 may further include code stored on the processor-based system 20 to cause the processor-based system to utilize the mass storage device 23. For example, the code may be stored on the mass storage device 23, the system memory 22, or another memory or storage device coupled to the processor-based system 20. For example, the code may be stored as part of a basic input/output system (BIOS) 27 coupled to the ICH 26.
In some embodiments of the processor-based system 20, the code stored on the processor-based system 20 may be configured to cause the processor-based system 20 to determine a first vertical redirect budget for a first memory channel of the plurality of memory channels, revector defects in the first memory channel vertically within the first memory channel until the first vertical redirect budget is exceeded, and revector defects in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the first vertical redirect budget is exceeded.
For example, in some embodiments of the processor-based system 20, the code may be further configured to cause the processor-based system 20 to determine the first vertical redirect budget based on a number of all known defects from the plurality of memory channels. For example, the code may be further configured to cause the processor-based system 20 to determine the first vertical redirect budget based on an average number of defects per memory channel. In some embodiments of the processor-based system 20, the code may be further configured to cause the processor-based system to determine a second vertical redirect budget for a second memory channel of the plurality of memory channels, revector defects in the second memory channel vertically within the second memory channel until the second vertical redirect budget is exceeded, and revector defects in the second memory channel horizontally outside of the second memory channel within another memory channel of the plurality of memory channels after the second vertical redirect budget is exceeded.
For example, in some embodiments of the processor-based system 20, all or a portion of the code may be implemented by or executed by a controller 31 which may be integrated with the mass storage device 23. Alternatively, with reference to
With reference to
In some embodiments of the invention, determining the first vertical redirect budget for the first memory channel of the plurality of memory channels may include determining the first vertical redirect budget based on a number of all known defects from the plurality of memory channels (e.g. at block 45). In some embodiments of the invention, determining the first vertical redirect budget for the first memory channel of the plurality of memory channels may include determining the first vertical redirect budget based on an average number of defects per memory channel (e.g. at block 46).
With reference to
Advantageously, some embodiments of the invention may improve defect revectoring in a multi-channel mass storage device. For example, some embodiments of the invention may simultaneously improve two metrics, performance and capacity, in a defect management scheme for a multi-channel mass storage device. For example, all defects in need of revector may be accumulated and thereafter an average revectors per channel may be calculated. The calculated average revectors per channel may be the budget for vertical redirects for each of the channels.
For a particular channel, defects may be revectored as vertical until the number of defects for that particular channel exceeds the budget. After the number of defects for that particular channel exceeds the budget, horizontal redirects may be used for further defects in that particular channel. In practice, some embodiments of the invention may results in a relatively high usage of vertical revectors. If there is a particular memory channel (e.g. a NAND flash memory device) with a high number of defects it will increase the average such that the other memory channels get most or all of their defects as vertical. But the problematic memory channel may get relatively more horizontal revectors (e.g. mostly horizontal revectors depending on the number of defects and the number of channels). Advantageously, some implementations of a defect management policy in accordance with the invention improved sequential bandwidth in a solid state drive by about 20%.
With reference to
With reference to
Those skilled in the art will appreciate that, given the benefit of the present description, a numerous variety of other circuits and combinations of hardware and/or software may be configured to implement various methods, circuits, and systems in accordance with the embodiments described herein and other embodiments of the invention. The examples of
The foregoing and other aspects of the invention are achieved individually and in combination. The invention should not be construed as requiring two or more of such aspects unless expressly required by a particular claim. Moreover, while the invention has been described in connection with what is presently considered to be the preferred examples, it is to be understood that the invention is not limited to the disclosed examples, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and the scope of the invention.
McVay, Jeffrey, Vogan, Andrew Wayne
Patent | Priority | Assignee | Title |
10340024, | Sep 26 2017 | SK HYNIX NAND PRODUCT SOLUTIONS CORP | Solid state drive physical block revectoring to improve cluster failure rates |
Patent | Priority | Assignee | Title |
5469390, | Sep 16 1993 | Renesas Electronics Corporation | Semiconductor memory system with the function of the replacement to the other chips |
6188618, | Apr 23 1998 | Kabushiki Kaisha Toshiba | Semiconductor device with flexible redundancy system |
20050204187, | |||
20070143536, | |||
20080320214, | |||
20090044078, | |||
20090089508, | |||
20100085825, | |||
20100169743, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Apr 06 2009 | Intel Corporation | (assignment on the face of the patent) | / | |||
May 28 2009 | MCVAY, JEFFREY | Intel Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 025863 | /0428 | |
Jun 16 2009 | VOGAN, ANDREW WAYNE | Intel Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 025863 | /0428 | |
Dec 29 2021 | Intel Corporation | SK HYNIX NAND PRODUCT SOLUTIONS CORP | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 062437 | /0255 |
Date | Maintenance Fee Events |
Nov 28 2014 | ASPN: Payor Number Assigned. |
Jun 14 2018 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
May 19 2022 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Date | Maintenance Schedule |
Dec 30 2017 | 4 years fee payment window open |
Jun 30 2018 | 6 months grace period start (w surcharge) |
Dec 30 2018 | patent expiry (for year 4) |
Dec 30 2020 | 2 years to revive unintentionally abandoned end. (for year 4) |
Dec 30 2021 | 8 years fee payment window open |
Jun 30 2022 | 6 months grace period start (w surcharge) |
Dec 30 2022 | patent expiry (for year 8) |
Dec 30 2024 | 2 years to revive unintentionally abandoned end. (for year 8) |
Dec 30 2025 | 12 years fee payment window open |
Jun 30 2026 | 6 months grace period start (w surcharge) |
Dec 30 2026 | patent expiry (for year 12) |
Dec 30 2028 | 2 years to revive unintentionally abandoned end. (for year 12) |