A solid-state imaging apparatus includes a pixel array in which a plurality of pixels are arranged, wherein the pixel array has a region formed from one of an electrical conductor and a semiconductor to which a fixed electric potential is supplied, each pixel includes a photoelectric converter, a charge-voltage converter which converts charges generated by the photoelectric converter into a voltage, and an amplification unit which amplifies a signal generated by the charge-voltage converter by a positive gain and outputs the amplified signal to an output line, and the output line comprising a shielding portion arranged to shield at least part of the charge-voltage converter with respect to the region.
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1. A solid-state imaging apparatus comprising a pixel array in which a plurality of pixels are arranged, wherein the pixel array includes a region to which a fixed electrical potential is supplied and which consists of an electrical conductor,
wherein each of the plurality of pixels includes a photoelectric converter arranged in a semiconductor substrate, a charge-voltage converter which converts charges generated by the photoelectric converter into a voltage, a transfer unit which transfers the charges generated by the photoelectric converter to the charge-voltage converter, and an amplification unit which amplifies, by a positive gain, a signal generated by the charge-voltage converter and outputs the amplified signal to an output node,
wherein part of a first conductive member that forms the output node is arranged, in a direction perpendicular to a surface of the pixel array, between at least part of the region and at least part of the charge-voltage converter,
wherein the charge-voltage converter includes:
an impurity region arranged in the semiconductor substrate,
a second conductive pattern arranged in a first wiring layer, and
a contact plug which connects the impurity region and the second conductive pattern,
wherein the first conductive member includes:
a third conductive pattern arranged in the first wiring layer and including a portion parallel to at least part of the second conductive pattern,
a fourth conductive pattern arranged in a second wiring layer above the first wiring layer, and
a via plug which connects the third conductive pattern and the fourth conductive pattern,
wherein the electrical conductor includes a fifth conductive pattern arranged in a third wiring layer above the second wiring layer, and
wherein the fourth conductive pattern is arranged between at least part of the second conductive pattern and at least part of the fifth conductive pattern.
2. The apparatus according to
a scintillator which converts radiation into visible light,
wherein the pixel array is arranged to photoelectrically convert the visible light, and
wherein the apparatus is formed as a radiation imaging apparatus.
3. A solid-state imaging apparatus according to
4. The apparatus according to
5. The apparatus according to
6. The apparatus according to
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1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and an imaging system.
2. Description of the Related Art
In a solid-state imaging apparatus, charges generated by a photoelectric converter are converted into a voltage by a charge-voltage converter such as a floating diffusion. Let Q be the charges, V be the voltage, and C be the capacity of the charge-voltage converter. Since V=Q/C, the sensitivity can be improved by reducing the capacity of the charge-voltage converter.
Japanese Patent Laid-Open No. 7-58308 discloses a solid-state imaging apparatus including a light receiving unit 1, a storage unit 2, a horizontal transfer unit 3, a floating diffusion 23, an output amplifier 27, and a buffer amplifier 31. The light receiving unit 1 includes a plurality of shift registers that are continuous in the vertical direction. The storage unit 2 includes a plurality of shift registers following those of the light receiving unit 1 and stores information charges corresponding to one screen. The horizontal transfer unit 3 receives, for each horizontal line, the information charges of one screen stored in the storage unit 2 and outputs them sequentially. The floating diffusion 23 temporarily stores the information charges output from the horizontal transfer unit 3. The floating diffusion 23 is connected to the input terminal of the output amplifier 27 via an aluminum wiring 26. The output amplifier 27 is formed from a two-stage source follower circuit. The output terminal of the output amplifier 27 is connected to the input terminal of the buffer amplifier 31. The signal output from the buffer amplifier 31 has the same phase as that of the potential variation that occurs in the floating diffusion 23, and is applied to an aluminum wiring 30 serving as a light shielding film that covers the floating diffusion 23. Hence, even when the aluminum wirings 26 and 30 oppose on both sides of an insulating film 29, the actual capacity between them is sufficiently small so as to suppress the increase in the capacity of the floating diffusion 23.
However, the invention described in Japanese Patent Laid-Open No. 7-58308 only aims at the final output portion of a CCD solid-state image sensor without considering the capacity of the charge-voltage converter of each pixel in a pixel array. Additionally, in the related-art invention, the output signal of the buffer amplifier is merely applied to the aluminum wiring to suppress the increase in the capacity of the floating diffusion caused by the aluminum wiring serving as a light shielding film that shields the floating diffusion from light. That is, in the related-art invention, the output signal of the buffer amplifier is not applied to the aluminum wiring arranged between an electrical conductor and the charge-voltage converter to suppress the increase in the capacity of the charge-voltage converter caused by the electrical conductor maintained at a fixed electric potential.
The present invention provides an advantageous technique of reducing the actual capacity of the charge-voltage converter of each pixel in a pixel array.
The first aspect of the present invention provides a solid-state imaging apparatus including a pixel array in which a plurality of pixels are arranged, the pixel array comprising a region formed from one of an electrical conductor and a semiconductor to which a fixed electric potential is supplied, each pixel comprising a photoelectric converter, a charge-voltage converter which converts charges generated by the photoelectric converter into a voltage, and an amplification unit which amplifies a signal generated by the charge-voltage converter by a positive gain and outputs the amplified signal to an output line; and the output line comprising a shielding portion arranged to shield at least part of the charge-voltage converter with respect to the region.
The second aspect of the present invention provides a solid-state imaging apparatus including a pixel array in which a plurality of pixels are arranged, the pixel array comprising a region formed from one of an electrical conductor and a semiconductor to which a fixed electric potential is supplied; and each pixel comprising a photoelectric converter, a charge-voltage converter which converts charges generated by the photoelectric converter into a voltage, and an amplification unit which amplifies a signal generated by the charge-voltage converter by a positive gain and outputs the amplified signal to an output node; wherein part of a first conductive pattern that forms the output node is arranged between at least part of the region and at least part of the charge-voltage converter.
The third aspect of the present invention provides an imaging system comprising a solid-state imaging apparatus as defined in the first or second aspect, and a processor which processes a signal output from the solid-state imaging apparatus.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
The schematic arrangement of a solid-state imaging apparatus 100 according to an embodiment of the present invention will be described with reference to
The solid-state imaging apparatus 100 may serve as an apparatus which captures an image of radiation such as X-rays or an apparatus which captures an image of visible light. When the solid-state imaging apparatus 100 serves as an apparatus which captures an image of radiation, a scintillator 103 which converts radiation into visible light can typically be provided on the sensor panel SP. The scintillator 103 converts radiation into visible light, which strikes the sensor panel SP and is photoelectrically converted by each photoelectric converter on the sensor panel SP (imaging block 101).
An example of the arrangement of each imaging block 101 will be described next with reference to
The imaging block 101 includes vertical scanning circuits 204 and horizontal scanning circuits 205. Although the vertical scanning circuit 204 can be placed, for example, between the photoelectric converters 202 on two adjacent columns, it may be placed outside the photoelectric converter 202 on the outermost column in the pixel array GA. The vertical scanning circuit 204 includes, for example, a vertical shift register which performs a shift operation in accordance with a first clock CLK1, and scans a plurality of rows in the pixel array GA in accordance with the shift operation by the vertical shift register. The vertical shift register is formed by connecting a plurality of registers in series, and a pulse received by a register in the first stage is sequentially transferred to registers in subsequent stages in accordance with the first clock CLK1. A row corresponding to a register which holds a pulse is to be selected.
Although the horizontal scanning circuit 205 can be placed, for example, between the photoelectric converters 202 on two adjacent rows, it may be placed outside the photoelectric converter 202 on the outermost row in the pixel array GA. The horizontal scanning circuit 205 includes, for example, a horizontal shift register which performs a shift operation in accordance with a second clock CLK2, and scans a plurality of columns in the pixel array GA in accordance with the shift operation by the horizontal shift register. The horizontal shift register is formed by connecting a plurality of registers in series, and a pulse received by a register in the first stage is sequentially transferred to registers in subsequent stages in accordance with the second clock CLK2. A column corresponding to a register which holds a pulse is to be selected.
The vertical scanning circuit 204 can be formed by vertically arraying a plurality of unit vertical scanning circuits VSR each including one register that constitutes the vertical shift register. Each unit vertical scanning circuit VSR can be placed in the region sandwiched by a photoelectric converter 202 of a pixel belonging to a given column (the leftmost column (that is, the first column) in
The horizontal scanning circuit 205 can be formed by horizontally arraying a plurality of unit horizontal scanning circuits HSR each including one register that constitutes the horizontal shift register. Each unit horizontal scanning circuit HSR is placed in the region sandwiched by two photoelectric converters 202 in each pair of two adjacent pixels (a pair of pixels on the first and second columns, a pair of pixels on the third and fourth columns, . . . ) belonging to one row (the fourth row from the top (that is, the fourth row) in
The pixel array GA can be regarded as being obtained by arraying a plurality of unit cells 200 each including the pixel 201 so as to form pluralities of rows and columns. The unit cells 200 can include several types. A certain unit cell 200 includes at least part of the unit vertical scanning circuit VSR. Although a set of two unit cells 200 includes only one unit vertical scanning circuit VSR in the example shown in
An example of the arrangement of each pixel 201 will be described with reference to
The photoelectric converter 202 includes a charge storage unit, which is connected to the gate of a PMOS transistor 303 of the first amplifier circuit 310. The source of the PMOS transistor 303 is connected to a current source 305 via a PMOS transistor 304. A first source follower circuit is formed using the PMOS transistor 303 and current source 305. Forming a source follower circuit using the PMOS transistor 303 is effective in reducing 1/f noise. The PMOS transistor 304 serves as an enable switch which enables the first source follower circuit upon being turned on when an enable signal EN supplied to its gate changes to active level. The first amplifier circuit 310 outputs a signal corresponding to the potential of a charge-voltage converter CVC to an intermediate node n1.
In the example shown in
The clamp circuit 320 uses a clamp capacitance 321 to clamp noise output to the intermediate node n1 by the first amplifier circuit 310 in accordance with the reset potential of the charge-voltage converter CVC. In other words, the clamp circuit 320 is a circuit for canceling that noise from a signal output from the first source follower circuit to the intermediate node n1 in accordance with the charge generated by the photoelectric converter 202. The noise output to the intermediate node n1 contains kTC noise produced upon resetting. Clamping is done by changing a clamp signal PCL to active level to turn on a PMOS transistor 323, and thereupon changing the clamp signal PCL to inactive level to turn off the PMOS transistor 323. The output terminal of the clamp capacitance 321 is connected to the gate of a PMOS transistor 322. The source of the PMOS transistor 322 is connected to a current source 325 via a PMOS transistor 324. A second source follower circuit is formed using the PMOS transistor 322 and current source 325. The PMOS transistor 324 serves as an enable switch which enables the second source follower circuit upon being turned on when an enable signal EN0 supplied to its gate changes to active level.
A signal output from the second source follower circuit in accordance with the charge generated by photoelectric conversion by the photoelectric converter 202 is written in a capacitance 342 as a light signal via a switch 341 when a light signal sampling signal TS changes to active level. A signal output from the second source follower circuit upon turning on the PMOS transistor 323 immediately after the potential of the charge-voltage converter CVC is reset is noise. This noise is written in a capacitance 362 via a switch 361 when a noise sampling signal TN changes to active level. This noise contains the offset component of the second source follower circuit.
When the unit vertical scanning circuit VSR of the vertical scanning circuit 204 drives the row select signal VST to active level, a signal (light signal) held in the capacitance 342 is output to the column signal line 208a via the NMOS transistor 343 and row select switch 344 in the second amplifier circuit. At the same time, a signal (noise) held in the capacitance 362 is output to the column signal line 208b via the NMOS transistor 363 and row select switch 364 in the second amplifier circuit. The NMOS transistor 343 in the second amplifier circuit and a constant current source (not shown) provided on the column signal line 208a form a source follower circuit. Similarly, the NMOS transistor 363 in the second amplifier circuit and a constant current source (not shown) provided on the column signal line 208b form a source follower circuit.
The pixel 201 may include an add switch 346 which adds light signals from a plurality of adjacent pixels 201. In an add mode, an add mode signal ADD changes to active level, so the add switch 346 is turned on. Thus, the add switch 346 connects the capacitances 342 of adjacent pixels 201 to each other, thereby averaging the light signals. Similarly, the pixel 201 may include an add switch 366 which adds noise signals from a plurality of adjacent pixels 201. When the add switch 366 is turned on, the add switch 366 connects the capacitances 362 of adjacent pixels 201 to each other, thereby averaging the noise signals.
The pixel 201 may have a function for changing the sensitivity. The pixel 201 can include, for example, a first sensitivity change switch 380, a second sensitivity change switch 382, and a circuit element associated with them. When a first change signal WIDE1 changes to active level, the first sensitivity change switch 380 is turned on, so the capacitance value of a first additional capacitance 381 is added to that of the charge-voltage converter CVC. This lowers the sensitivity of the pixel 201. When a second change signal WIDE2 changes to active level, the second sensitivity change switch 382 is turned on, so the capacitance value of a second additional capacitance 383 is added to that of the charge-voltage converter CVC. This further lowers the sensitivity of the pixel 201.
In this manner, adding a function of lowering the sensitivity of the pixel 201 makes it possible to receive a larger amount of light, thus widening the dynamic range. When the first change signal WIDE1 changes to active level, an enable signal ENw may be changed to active level to enable a PMOS transistor 385 to perform a source follower operation, in addition to enabling the PMOS transistor 303 to perform a source follower operation.
Although the vertical scanning circuit 204 can have various arrangements, it can have an arrangement shown in, for example,
Although the horizontal scanning circuit 205 can have various arrangements, it can have an arrangement shown in, for example,
Main signals supplied to each pixel 201 will be described with reference to
First, the enable signal EN becomes active on all rows in the pixel array GA, and the light signal sampling signal TS changes to active level in a pulsed pattern, so a light signal is written in the capacitance 342. Next, the reset signal PRES changes to active level in a pulsed pattern, so the potential of the charge-voltage converter CVC is reset. The clamp signal PCL changes to active level in a pulsed pattern. When the clamp signal PCL is at active level, the noise sampling signal TN changes to active level in a pulsed pattern, so noise is written in the capacitance 362.
A unit vertical scanning circuit VSR corresponding to the first row of the vertical scanning circuit 204 changes its row select signal VST (VST0) to active level. This means that the vertical scanning circuit 204 selects the first row of the pixel array GA. In this state, unit horizontal scanning circuits HSR corresponding to the first to last columns of the horizontal scanning circuit 205 change their column select signals HST (HST0-HSTn) to active level. This means that the horizontal scanning circuit 205 sequentially selects the first to last columns of the pixel array GA. Thus, light signals and noise signals of pixels on the first to last columns on the first row of the pixel array GA are output from the output amplifiers 210a and 210b, respectively. After that, a unit vertical scanning circuit VSR corresponding to the second row of the vertical scanning circuit 204 changes its row select signal VST (VST1) to active level. Unit horizontal scanning circuits HSR corresponding to the first to last columns of the horizontal scanning circuit 205 change their column select signals HST (HST0-HSTn) to active level. By performing such an operation for the first to last rows, one image is output from the pixel array GA.
The structure of each pixel 201 will be exemplified next with reference to
The in-pixel readout circuit 203 includes the first amplifier circuit 310, as described above. The first amplifier circuit 310 outputs a signal corresponding to the potential of the charge-voltage converter CVC to the intermediate node (output line) n1. In the example shown in
The node (output line) n1 includes a first conductive pattern 801 arranged in the first wiring layer to form at least part of the shielding portion. The charge-voltage converter CVC includes a second conductive pattern 802 arranged in the second wiring layer above the first wiring layer along the first conductive pattern 801.
The conductive pattern (third conductive pattern) 620 arranged in the third wiring layer above the second wiring layer has an opening portion OP at part of the region where the photoelectric converter 202 exists when viewed from the upper side, as illustrated in
Another example of the pixel 201 will be described next with reference to
The photoelectric converter 202 is formed in the semiconductor substrate SUB. The charge-voltage converter CVC includes a first conductive pattern 1201 arranged in the first wiring layer, and a contact plug 1202 that connects the first conductive pattern 1201 to a floating diffusion region (impurity region) FD arranged in the semiconductor substrate SUB. The output line n1 includes a second conductive pattern 1203, a third conductive pattern 1204, and a via plug 1205. The second conductive pattern 1203 is arranged in the first wiring layer and includes a portion parallel to at least part of the first conductive pattern 1201. The third conductive pattern 1204 is arranged in the second wiring layer above the first wiring layer. The via plug 1205 connects the second conductive pattern 1203 to the third conductive pattern 1204. In the pixel array GA (or the pixel 201), a fourth conductive pattern 1210 serving as an electrical conductor to which a fixed electric potential (for example, a ground potential GND) is supplied is arranged in the third wiring layer above the second wiring layer. The third conductive pattern 1204 that forms part of the node (output line) n1 is arranged to shield at least part of the charge-voltage converter CVC with respect to the fourth conductive pattern 1210 that is the electrical conductor to which the fixed electric potential is supplied, as illustrated in
Also, the image processor 6070 can transfer the signal obtained by processing to a remote site via a transmission path 6090. This makes it possible to display the image on a display 6081 placed in, for example, a doctor room at another site or record the image on a recording medium such as an optical disk. The recording medium may be a film 6110, and a film processor 6100 records the image on the film 6110 in this case.
The solid-state imaging apparatus according to the present invention is also applicable to an imaging system which captures an image of visible light. Such an imaging system can include, for example, the solid-state imaging apparatus 100 and a processor which processes a signal output from the solid-state imaging apparatus 100. The processing by the processor can include at least one of, for example, processing of converting the image format, processing of compressing the image, processing of changing the image size, and processing of changing the image contrast.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2010-155260, filed Jul. 7, 2010, which is hereby incorporated by reference herein in its entirety.
Matsuda, Takashi, Koizumi, Toru, Kikuchi, Shin
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