A method of analyzing a phase of a clock signal for receiving data is described. The method comprises identifying an end of an eye pattern associated with received data; testing points along a contour of the eye pattern to establish a margin for an opening of the eye pattern; and determining whether a phase of the clock signal is acceptable for receiving the received data. A circuit for analyzing a phase of a clock signal for receiving data is also described.
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1. A method of analyzing a phase of a clock signal for receiving data, the method comprising:
establishing an end of an eye pattern associated with received data;
testing points to establish a margin for an opening of the eye pattern;
selectively moving horizontally and vertically, from the end of the eye pattern, along a voltage versus time plot after the end of the eye pattern is established to identify transitions between valid data and invalid data;
establishing a contour of the eye pattern using the selectively scanned points; and
determining whether the phase of the clock signal is acceptable for receiving the received data.
15. A circuit for analyzing a phase of a clock signal for receiving data, the circuit comprising:
a circuit generating a phase of a clock signal; and
a clock and data recovery circuit coupled to receive data and the phase of the clock signal;
wherein the clock and data recovery circuit identifies an end of an eye pattern and selectively tests points, from the end of the eye pattern, along a contour of the eye pattern by selectively moving horizontally and vertically along a voltage versus time plot after the end of the eye pattern is established to identify transitions between valid data and invalid data, wherein the transitions between valid data and invalid data enable determining whether the phase of the clock signal is acceptable for receiving data and establishing a contour of the eye pattern using the selectively tested points.
9. A method of analyzing a phase of a clock signal for receiving data, the method comprising:
scanning points along a time axis of a voltage versus time plot to identify a first end of an eye pattern;
scanning points along the time axis of the voltage versus time plot to identify a second end of the eye pattern;
determining whether a phase of the clock signal is acceptable for receiving data;
selectively moving horizontally and vertically along the voltage versus time plot, after the first and second ends of the eye pattern are established, by scanning points along a voltage axis of the voltage versus time plot to identify a first voltage of the eye pattern by identifying transitions between valid data and invalid data;
selectively moving horizontally and vertically along the voltage versus time plot, after the first and second ends of the eye pattern are established, by scanning points along the voltage axis of the voltage versus time plot to identify a second voltage of the eye pattern by identifying transitions between valid data and invalid data;
establishing a contour of the eye pattern using the selectively scanned points; and
determining a voltage variation of received data.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
testing points comprises identifying invalid data points along the time axis from a center point of the voltage versus time plot to identify two ends of the eye pattern, and identifying invalid data points at a top and a bottom of the eye pattern; and
the method further comprises determining a voltage range of received data from voltages at the invalid data points at the top and bottom of the eye pattern.
7. The method of
testing points comprises testing a plurality of points above a center voltage of the voltage versus time plot to determine the contour of a top portion of the eye pattern; and
the method further comprises determining a voltage range of received data from invalid data points at the top of the eye pattern.
8. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
16. The circuit of
17. The circuit of
18. The circuit of
19. The circuit of
testing points along a contour of the eye pattern comprises testing a plurality of points above a center voltage to determine a contour of a top portion of the eye pattern; and
the clock and data recovery circuit further enables determining a voltage range of received data from invalid data points at the top of the eye pattern.
20. The circuit of
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One or more embodiments generally relate to integrated circuits, and more particularly to methods of and circuits for analyzing a phase of a clock signal for receiving data.
A high-speed serial receiver samples incoming data symbols at some phase of the high-speed clock generated from a phase-locked loop (PLL). The PLL uses a reference clock to produce the high-speed clock. The edge transitions (i.e., the recovered clock) between incoming data symbols can be recovered using the high-speed clock. To properly sample the incoming data symbols, the receiver should sample the incoming data symbols between the edge transitions in the stream of incoming data symbols. The range of sampling phases for which the high-speed serial receiver properly recovers the incoming data symbols gives the margin for the sampling phase.
To check that the data symbols actually captured by the high-speed serial receiver match the data symbols that the external test equipment transmits to the high-speed serial receiver, the captured data symbols must be looped back to the external test equipment. However, it is time consuming and difficult to determine the margin of the sampling phase because external test equipment is required and because the tested receiver must generally include a transmitter supporting a loopback mode for returning the captured data symbols. Further, in order to determine whether a phase of a clock signal is acceptable for receiving data, numerous points must be checked. These numerous points must be checked for each phase of a plurality of available phases which could be used for receiving data. The requirement to check many points for a number of phases of a clock signal further increases the testing time for a receiver.
A method of analyzing a phase of a clock signal for receiving data is described. The method comprises identifying an end of an eye pattern associated with received data; testing points along a contour of the eye pattern to establish a margin for an opening of the eye pattern; and determining whether a phase of the clock signal is acceptable for receiving the received data.
Another method of analyzing a phase of a clock signal for receiving data comprises scanning points along a time axis of a voltage versus time plot to identify a first end of an eye pattern; scanning points along the time axis of the voltage versus time plot to identify a second end of the eye pattern; determining whether a phase of the clock signal is acceptable for receiving data; scanning points along a voltage axis of the voltage versus time plot to identify a first voltage of the eye pattern; scanning points along the voltage axis of the voltage versus time plot to identify a second voltage of the eye pattern; and determining a voltage variation of received data.
A circuit for analyzing a phase of a clock signal for receiving data is also described. The circuit comprising a circuit generating a phase of a clock signal; and a clock and data recovery circuit coupled to receive data and the phase of the clock signal, the clock and data recovery circuit enabling identifying an end of an eye pattern, and testing points along a contour of the eye pattern to determine whether the phase of the clock signal is acceptable for receiving data.
When the analog values and transitions of received data symbols are accumulated and displayed over a unit interval (UI), the resulting display is denoted as an “internal eye diagram” or “eye pattern” because the rising and falling transitions at the beginning and end of the unit interval frame the general shape of an open eye. The eye pattern gives the margin of the sampling phase by indicating the time between the two ends of the signal for receiving the data, and enables selection of an operating point with an optimum margin.
A contour eye-scan can enable the evaluation of data received at points along a voltage versus time plot on the boundary or contour of an eye pattern for a given phase of a clock signal. With the contour eye-scan, it is assumed that all the points inside the eye pattern are passing points. That is, the points at the center of the eye will be determined to be valid according to some criterion such as a bit error rate. This assumption can be made because the points on the contour of the eye pattern are the ones which are subjected to high jitter. For example, points on the contour of the eye pattern are subjected to either data transition and/or amplitude variation, whereas the points towards the center of the eye pattern are more stable sampling points. Therefore, the probability of error sampling on the edge of the eye pattern is high, while the probability of error sampling inside the eye pattern is very low. A contour scanning can reduce the number of points required to be scanned compared to traditional eye-scan methods, thus providing lower test time and greater test coverage. It also validates the optimum position where the CDR is sampling data. Further, contour eye-scan will give approximately the same level of confidence but reduced test time in identifying an opening of the eye pattern compared to a traditional eye-scan.
The “internal eye diagram” of the serial receiver and the margin of the sampling phase can be determined. Further, upstream circuits can be characterized according to the eye opening of the eye pattern. Some of the upstream components include, without limitation, termination resistors, a Continuous Time Linear Equalizer (CTLE) circuit and an Automatic Gain Control (AGC) circuit. The contour eye-scan allows characterization, validation and optimization of these components in terms of the opening of the eye pattern. This technique provides the ability to characterize an upstream circuit such as a linear equalizer using the determined optimum operating point, to enable in-circuit characterization and dynamic tuning of a receiver in an end-user application, and to improve production screening of the receivers within programmable integrated circuits.
An internal eye-scan measurement of the eye pattern at the receiver can be implemented using Bit Error Rate (BER) testing inside a programmable integrated circuit. An internal eye-scan implementing a contour eye-scan is a receiver margin test where the measurements and calculations are performed within the integrated circuits. The internal eye-scan measurements can provide direct measurements at the receiver, reduce test time, and eliminate expensive test equipment by eliminating the requirement to provide data back to the test equipment.
Turning first to
The programmable integrated circuit 102 implements a receiver coupled to the transmitter 110 via the communication signal on line 112. The receiver includes a decision feedback equalizer (DFE) circuit 114, a clock and data recovery (CDR) circuit 116, and an eye-scan controller 120. The DFE circuit 114 generates a filtered signal on line 122 from a signal 123 representing the first pass of filtering by the linear equalizer 124. The filtered signal on line 122 is a sum of the communication signal on line 123 and a variable weighting of a binary symbol recently sampled. The receiver includes the first level of filtering, the linear equalizer 124, that attenuates low frequencies and/or amplifies high frequencies.
Capture flip-flop 136 and 138 sample the filtered signal, where path 140 is the mission path and 142 is the replica path. In the replica path, capture flip-flop 136 is controlled by eye-scan circuit 120 for margin measurements.
PLL 134 provides the high speed clock 135. The CDR circuit 116 provides high speed clock signals 144 and 146 having controllable delays. A clock signal 148 is the parallel clock for a single in, parallel out (SIPO) buffer 150. The CDR circuit 116 provides clock signals 140, which is a selected phase relative to the clock signal 135, provided by the PLL 134, for sampling the filtered signal on line 122. The selected phase is such that the serial data stream on line 112 is aligned to the recovered clock. The serial-in parallel-out buffer 150 deserializes the received sequence of sampled binary symbols on line 126 into a series of received words. A clock signal 148 is the parallel clock for the SIPO. The CDR circuit 116 provides a selected phase relative to a clock signal for sampling the filtered signal on line 122. The selected phase is such that the serial stream is aligned to the recovered clock.
The clock source 130 of test equipment 104 provides the clock signal on line 132, and the transmitter 110 of test equipment 104 serially transmits the transmitted sequence of binary symbols in synchronization with the clock signal on line 132. A PLL 134 generates a clock signal 135 which generally matches the phase of the clock signal on line 132, and generates a clock signal that is synchronous with the transitions of the communication signal on line 112. The CDR circuit 116 varies the phase of the clock signal 135 from PLL 134 to sample the received sequence of sampled binary symbols using capture flip-flops 136 and 138. The eye-scan circuit 120 and the CDR circuit 116 will enable margin measurements to receive data, as is described in more detail below.
Turning now to
Because test equipment 206 transmits symbols that are asynchronous to a clock signal 209 from PLL 210, the CDR circuit 116 cannot successfully sample the transmitted symbols at a fixed phase of the clock signal 209 from PLL 210. Instead, the CDR circuit 116 aligns a variable phase with the transitions between the transmitted symbols, and samples about halfway between the transitions during normal operation. In an exemplary circuit with plesiochronous frequencies for clock sources 202 and 204, the variable sampling phase is often monotonically increasing or monotonically decreasing at a rate equaling the frequency difference between clock sources 202 and 204. Other than the differences discussed above, the asynchronous communication characterization circuit of
In another example, a synchronous communication characterization circuit includes a receiver that directly recovers a clock signal from the transmitted symbols without receiving a clock signal from a remote or local oscillator. In one example, the receiver includes a PLL that generates a clock signal having transitions locked in phase with the transitions between the transmitted symbols, where an eye-scan controller varies a sampling phase of the generated clock signal on the replica path.
The DFE circuit 302 is coupled to a communication signal 310, and is configured to generate a filtered signal on line 312. The DFE circuit 302 can include a serial shifter having registers 314 through 316, for example. Register 314 at a beginning of the serial shifter samples a symbol directly from the filtered signal on line 312, and each register 316 stores a less recently sampled symbol. The registers 314 through 316 are coupled to respective amplifiers 318 through 320. The respective amplifier 318 through 320 for each register 314 through 316 has a variable gain that scales the respective recently sampled symbol stored in the register by a respective weighting. The summing circuit 322 generates the filtered signal on line 312 that is a sum of the communication signal 310 and the outputs from the amplifiers 318 through 320. Thus, the DFE circuit 302 is configured to generate the filtered signal on line 312 that is the sum of the communication signal 310 and respective weightings of the recently sampled symbols stored in registers 314 through 316.
During normal operation, the negative feedback from the recently sampled symbols stored in registers 314 through 316 compensates for inter-symbol interference and for attenuation of the high-frequency components of the communication signal 310. In one exemplary circuit, only the most recently sampled symbol stored in register 314 is used to characterize the receiver, while feedback from the remaining recently sampled symbols is disabled during receiver characterization by setting each weight register 324 to zero. Thus, for characterization of the receiver, the filtered signal on line 312 is a sum of the communication signal 310 and the most recently sampled symbol from register 314.
The capture flip-flop 328 samples a sequence of sampled symbols from the filtered signal on line 312 in the replica path 329. In particular, the capture flip-flop 328 is configured to detect a signal at a certain voltage and time offset of a given phase of the clock signal 330 so that points along the contour of the eye pattern can be tested. That is, rather than testing each point in a conventional manner in a voltage versus time plot as shown in
In one exemplary circuit, the communication signal 310 provides a sequence of symbols that is synchronized to the clock signal 330. The CDR circuit 334 includes a phase interpolator 332 configured to generate the variable sampling phase from a clock signal generated by the PLL 333 as a function of an offset value from the finite state machine (FSM) of CDR circuit 334 and a phase of the clock signal indicated by the eye-scan controller 308. In this example, the eye-scan controller 308 causes the sampling phase to set the offset value provided to the phase interpolator 333.
The eye-scan controller 308 and the CDR circuit 334 enable the receiver to test certain data points of the eye pattern to determine whether a given phase of the clock signal is acceptable for receiving data. After a first phase of a clock signal is selected and provided to the CDR circuit 334, the phase interpolator 333 will generate a clock signal that is an offset in time based upon a phase of the clock signal generated by the PLL 333. Accordingly, the capture flip-flop 328, the phase interpolator 332, and the eye-scan circuit 308 will enable testing of various points on the contour of an eye pattern. By adjusting both the voltage detected by the capture flip-flop 328 and an offset of the clock signal provided to the capture flip-flop 328, particular points on the contour of the eye can be detected until a complete eye pattern is identified. The operation of the CDR circuit 334 having the eye-scan controller 308 may be implemented as set forth in
Turning now to
Unlike a conventional circuit for determining the eye configuration of the data which tests all points in the plot, only points around a contour of the eye pattern are tested, as shown in
Since each point on the voltage versus time plot is discrete, the classification is made as pass or fail. Each discrete point is a combination of voltage offset (Y axis) and Time (X Axis) from the data sampling edge. A circuit implementing the contour eye-scan scans initial points to find the ends of the eye pattern, and the boundary points of the eye pattern are extracted using BER detection. If invalid data is detected at the center of the voltage versus time plot (i.e., valid data indicating that a zero value is not present at the center point), it can be assumed that the current phase of the clock signal is too far out of phase, and there is no need to determine whether the margins of the eye pattern are adequate to recover data. Rather, a new phase is selected without detecting both ends of the eye pattern. As is described in more detail below, assuming that valid data indicating that no data is received at the center of the eye, the ends of the eye are detected. A margin for the eye and optionally, the voltage range of the received signal, may then be determined based upon one or more points along the contour of the eye.
Turning now to
A different number of points along the contour can be tested to determine the margins of the eye and optionally the voltage levels of the received signal, where the number of points being tested represents a tradeoff between accuracy of the scan results and scanning speed. In a most basic test, the margins of the eye pattern for a given phase of a clock signal could be determined. Additionally or alternatively, a voltage variation of the received signals can be determined based upon the voltage levels at the top and the bottom of the eye pattern. In one example, only three points need to be identified to determine the margins of the eye pattern for a given phase of the clock signal. In particular, a center point, i.e., a point at approximately the center of the voltage versus time plot of
Turning now to
If data is valid, points along the horizontal axis having the selected center point are tested until a point fails at a block 610. That is, the ends of the eye are determined by testing points along the time axis until the two ends points on either side of the center point are identified. Various calculations can then be made based upon the results of testing points along the horizontal axis. For example, the margins of the eye pattern of the received signal are determined at a block 612. The voltage variation of the received signal may also be determined at a block 614. As is described in more detail below, additional points along the contour of the eye pattern may be tested to determine the voltage variation of the received signal from invalid data detected at the top of the eye pattern and/or the bottom of the eye pattern. It is then determined whether additional phases need to be tested at a block 616. If so, the phase of the clock signal is incremented at a block 618. If not, the phase of the clock signal is used for receiving data is selected at a block 620. The gain of the received input data may be adjusted if necessary based upon the voltage variation of the received signal at a block 622.
Turning now to
Turning now to
The software flow for a circuit design to be implemented in a programmable integrated circuit comprises synthesis, packing, placement, and routing, as is well known in the art. Synthesis comprises the step of converting a circuit design in a high level design to a configuration of elements found in the programmable integrated circuit. For example, a synthesis tool operated by the computer 802 may implement the portions of a circuit design implementing certain functions in configurable logic blocks (CLBs) or digital signal processing (DSP) blocks, for example. An example of a synthesis tool is the ISE tool available from Xilinx, Inc. of San Jose Calif. Packing comprises the step of grouping portions of the circuit design into defined blocks of the device, such as CLBs. Placing comprises the step of determining the location of the blocks of the device defined during the packing step. Finally, routing comprises selecting paths of interconnect elements, such as programmable interconnects, in a programmable integrated circuit. At the end of place and route, all functions, positions and connections are known, and a configuration bitstream is then created. The bitstream may be created by a software module called BitGen, available from Xilinx, Inc. of San Jose, Calif. The bitstream is either downloaded by way of a cable or programmed into an EPROM for delivery to the programmable integrated circuit.
Turning now to
The device of
In some FPGAs, each programmable tile includes a programmable interconnect element (INT) 911 having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element 911 also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of
For example, a CLB 902 may include a configurable logic element (CLE) 912 that may be programmed to implement user logic plus a single programmable interconnect element 911. A BRAM 903 may include a BRAM logic element (BRL) 913 in addition to one or more programmable interconnect elements. The BRAM includes dedicated memory separate from the distributed RAM of a configuration logic block. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as five CLBs, but other numbers may also be used. A DSP tile 906 may include a DSP logic element (DSPL) 914 in addition to an appropriate number of programmable interconnect elements. An 10B 904 may include, for example, two instances of an input/output logic element (IOL) 915 in addition to one instance of the programmable interconnect element 911. The location of connections of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The programmable interconnects, in response to bits of a configuration bitstream, enable connections comprising interconnect lines to be used to couple the various signals to the circuits implemented in programmable logic, or other circuits such as BRAMs or the processor.
In the pictured embodiment, a columnar area near the center of the die is used for configuration, clock, and other control logic. The config/clock distribution regions 909 extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA. Some FPGAs utilizing the architecture illustrated in
Note that
In one embodiment, an MGT 901 includes the characterized receiver and certain CLBs 902 are configured to implement the eye-scan controller and the PRBS data checker using error indications stored in a BRAM 903.
Turning now to
In the pictured embodiment, each memory element 1002A-1002D may be programmed to function as a synchronous or asynchronous flip-flop or latch. The selection between synchronous and asynchronous functionality is made for all four memory elements in a slice by programming Sync/Asynch selection circuit 1003. When a memory element is programmed so that the S/R (set/reset) input signal provides a set function, the REV input terminal provides the reset function. When the memory element is programmed so that the S/R input signal provides a reset function, the REV input terminal provides the set function. Memory elements 1002A-1002D are clocked by a clock signal CK, which may be provided by a global clock network or by the interconnect structure, for example. Such programmable memory elements are well known in the art of FPGA design. Each memory element 1002A-1002D provides a registered output signal AQ-DQ to the interconnect structure. Because each LUT 1001A-1001D provides two output signals, O5 and O6, the LUT may be configured to function as two 5-input LUTs with five shared input signals (IN1-IN5), or as one 6-input LUT having input signals IN1-IN6.
In the embodiment of
The invention is thought to be applicable to a variety of systems for characterizing a receiver. Other aspects and embodiments will be apparent to those skilled in the art from consideration of the specification. The embodiments may be implemented as one or more processors configured to execute software, as an application specific integrated circuit (ASIC), or as a logic on a programmable logic IC, for example. It is intended that the specification and illustrated embodiments be considered as examples only, with a true scope and spirit of the invention being indicated by the following claims.
Asuncion, Santiago G., Fanaswalla, Mustansir, Fernandes, Brandon L., Kamdar, Vaibhav, Patil, Jayesh
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