A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.
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1. A semiconductor device comprising:
a dielectric structure which has an opening exposing a surface of a substrate; and
a conductive structure which is formed in the opening, wherein the conductive structure comprises:
a first conductive pattern recessed in the opening;
a second conductive pattern covering a top surface and sidewalls of the first conductive pattern;
an air gap defined between sidewalls of the opening and the second conductive pattern; and
a third conductive pattern capping the second conductive pattern and the air gap.
2. The semiconductor device according to
3. The semiconductor device according to
4. The semiconductor device according to
5. The semiconductor device according to
a barrier pattern formed between the third conductive pattern and the second conductive pattern, and capping the air gap and the second conductive pattern; and
a glue pattern formed over the barrier pattern.
6. The semiconductor device according to
7. The semiconductor device according to
a capacitor coupled to the conductive structure; and
a plurality of bit line structures coupled to the substrate, wherein the opening is defined between the plurality of bit line structures, and the first conductive pattern and the second conductive pattern are separated from the bit line structures by the air gap.
8. The semiconductor device according to
a buried gate type transistor having a gate electrode which is buried in the substrate, wherein the conductive structure is coupled to a source region or a drain region of the buried gate type transistor.
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The present application claims priority of Korean Patent Application No. 10-2013-0081885, filed on Jul. 12, 2013, which is incorporated herein by reference in its entirety.
1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with air gaps and a method for fabricating the same.
2. Description of the Related Art
In general, in a semiconductor device, a dielectric material is formed between adjacent conductive structures. As a semiconductor device is highly integrated, a distance between conductive structures is gradually decreasing, thus, parasitic capacitance increases. As parasitic capacitance increases, the performance of the semiconductor device is degraded.
To reduce parasitic capacitance, the dielectric constant of a dielectric material may be decreased. However, since the dielectric material has a high dielectric constant, limitations may exist in reducing parasitic capacitance.
Various exemplary embodiments are directed to a semiconductor device capable of reducing the parasitic capacitance between adjacent conductive structures, and a method for fabricating the same.
In an exemplary embodiment, a semiconductor device may include: a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.
In an exemplary embodiment, a semiconductor device may include: a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening and including metal silicide; an air gap defined between sidewalls of the opening and the first conductive pattern; and a second conductive pattern capping the first conductive pattern and the air gap.
In an exemplary embodiment, a semiconductor device may include: a plurality of conductive structures including first conductive patterns which are formed over a substrate; second conductive patterns recessed between the conductive structures; third conductive patterns covering top surfaces and sidewalls of the second conductive patterns; air gaps defined between the first conductive patterns and the third conductive patterns; and fourth conductive patterns capping the air gaps and the third conductive patterns.
In an exemplary embodiment, a semiconductor device may include: a plurality of bit line structures including bit lines which are formed over a substrate; first plugs recessed between the bit line structures and including metal silicide; air gaps defined between the first plugs and the bit line structures; and second plugs capping the air gaps and the first plugs.
In an exemplary embodiment, a method for fabricating a semiconductor device may include: forming a plurality of conductive structures including first conductive patterns over a substrate; forming a dielectric layer over the conductive structures; etching the dielectric layer to define openings between the conductive structures; forming sacrificial spacers over sidewalls of the openings; forming second conductive patterns recessed in the openings over the sacrificial spacers; removing the sacrificial spacers to define air gaps; forming third conductive patterns which are separated from the first conductive patterns by the air gaps and cover sidewalls and top surfaces of the second conductive patterns; and forming fourth conductive patterns which cap the air gaps over the third conductive patterns.
In an exemplary embodiment, a method for fabricating a semiconductor device may include: forming a plurality of conductive structures including first conductive patterns over a substrate; forming a dielectric layer over the conductive structures; etching the dielectric layer to define openings between the conductive structures; forming sacrificial spacers over sidewalls of the openings; forming second conductive patterns recessed in the openings over the sacrificial spacers, the second conductive patterns including metal silicide; removing the sacrificial spacers to define air gaps; and forming third conductive patterns which cap the air gaps over the second conductive patterns.
In an exemplary embodiment, a method for fabricating a semiconductor device may include: forming a plurality of bit line structures including bit lines over a substrate; forming a dielectric layer over the bit line structures; etching the dielectric layer to define contact holes between the bit line structures; forming sacrificial spacers over sidewalls of the contact holes; forming silicon plugs recessed in the contact holes over the sacrificial spacers; removing the sacrificial spacers to define air gaps; forming ohmic contact layers which are separated from the bit lines by the air gaps that cover sidewalls and top surfaces of the silicon plugs; and forming metal plugs which cap the air gaps over the ohmic contact layer.
In an exemplary embodiment, a method for fabricating a semiconductor device may include: forming a plurality of bit line structures including bit lines over a substrate; forming a dielectric layer over the bit line structures; etching the dielectric layer to define openings between the bit line structures; forming sacrificial spacers over sidewalls of the openings; forming silicide plugs recessed in the openings over the sacrificial spacers; removing the sacrificial spacers to define air gaps; and forming metal plugs which cap the air gaps over the silicide plugs.
In an exemplary embodiment, a method for fabricating a semiconductor device may include: forming isolation regions in a substrate which isolate first regions and second regions from each other; forming bit line structures and gate structures in the first regions and the second regions, respectively; forming a dielectric layer over the bit line structures; etching the dielectric layer to define contact holes between the bit line structures; forming sacrificial spacers over sidewalls of the contact holes; forming silicon plugs recessed in the contact holes over the sacrificial spacers; removing the sacrificial spacers to define air gaps; forming ohmic contact layers which are separated from the bit line structures by the air gaps that cover sidewalls and top surface of the silicon plugs; forming metal plugs which cap the air gaps over the ohmic contact layer; and forming capacitors over the metal plugs.
In accordance with the above embodiments, since air gaps are defined between conductive structures, parasitic capacitance (Cb) may be reduced.
Additionally, since conductive structures include a silicide layer, the sheet resistance (Rs) of the conductive structures may be reduced. In particular, since a low resistance silicide layer is included, the sheet resistance (Rs) of the conductive structures may be further reduced. As the sheet resistance (Rs) is reduced, a contact resistance (Rc) may be improved.
Further, since a contact area increases as an ohmic contact layer covers a silicon plug, the contact resistance (Rc) of the conductive structures may be further improved. Moreover, it is possible to cap the air gaps using a conductive material without using a dielectric material. As a consequence, a parasitic capacitance (Cb) may be reduced due to the air gaps, a sheet resistance (Rs) may be reduced by the low resistance silicide layer, and the contact resistance (Rc) of the conductive structures may be improved attributable to an increase in contact area.
Various exemplary embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” means not only “directly on” but also “on” something with an intermediate feature(s) or a layer(s) in between, and that “over” means not only directly on top but also on top of something with an intermediate feature(s) or a layer(s) in between. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.
Referring to
The substrate 101 includes a silicon substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. The dielectric layer 102 includes a low-k material. The dielectric layer 102 may include silicon nitride or silicon oxide. The dielectric layer 102 serves as an interlayer dielectric layer.
The opening 103 may have a hole shape or a line shape. For example, the opening 103 includes a contact hole, a via hole, a through hole, a trench, a recess, or the like. When the opening 103 is a contact hole, the conductive structure 105 becomes a contact plug.
Each of the first conductive pattern 106 and the third conductive pattern 110 includes a silicon-containing material or a metal-containing material. The first conductive pattern 106 and the third conductive pattern 110 may include the same conductive material or different conductive materials. For example, the first conductive pattern 106 includes a silicon-containing material, and the third conductive pattern 110 includes a metal-containing material. The first conductive pattern 106 may include polysilicon, and the third conductive pattern 110 may include tungsten. When the silicon-containing material and the metal-containing material contact each other, an ohmic contact is required. For such an ohmic contact, the second conductive pattern 107 is formed.
The second conductive pattern 107 covers the top surface and the sidewalls of the first conductive pattern 106. The second conductive pattern 107 includes silicide. The second conductive pattern 107 may include metal silicide. The second conductive pattern 107 may include titanium silicide, cobalt silicide, nickel silicide or tungsten silicide. In the exemplary embodiment, the second conductive pattern 107 includes cobalt silicide. The second conductive pattern 107 includes cobalt silicide with a phase of CoSi2.
The spacer 104 includes a low-k material. The low-k material includes oxide or nitride. The low-k material may include silicon oxide, silicon nitride or metal oxide. The spacer 104 includes SiO2, Si3N4 or SiN. The spacer 104 may be omitted.
The air gap 111 may be defined by removing a sacrificial material formed between the spacer 104 and the second conductive pattern 107.
The barrier pattern 108 covers the top surface and the sidewalls of an upper portion of the second conductive pattern 107 and caps the air gap 111. Further, the barrier pattern 108 covers the sidewalls of the opening 103 over the air gap 111. The barrier pattern 108 does not fill the air gap 111 but caps the air gap 111. The barrier pattern 108 includes a metal-containing material. The barrier pattern 108 may include titanium.
The glue pattern 109 includes a metal-containing material. The glue pattern 109 may include titanium nitride (TiN).
Referring to
In
Referring to
The first conductive pattern 126 includes silicide. The first conductive pattern 126 may include metal silicide. The first conductive pattern 126 includes metal silicide which is formed by deposition. The metal silicide may be formed by chemical vapor deposition (CVD). The first conductive pattern 126 may also be formed by a fully-silicidation process. The first conductive pattern 126 may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. In the exemplary embodiment, the first conductive pattern 126 includes cobalt silicide. The first conductive pattern 126 includes cobalt silicide with the phase of CoSi2.
Referring to
In
In
While not shown, a transistor which includes a gate electrode formed on the substrate 101 and 121, and a source region and a drain region formed in the substrate 101 and 121 may be formed. Each of the conductive structures 105, 105B, 125, and 125D may be connected to the source region or the drain region of the transistor. The transistor may include a planar gate type transistor, a trench gate type transistor, a buried gate type transistor, a recess gate type transistor, or a vertical channel transistor. An additional conductive structure may be formed on each of the conductive structures 105, 105B, 125, and 125D. The additional conductive structure may include a metal line or a memory element. The memory element may include a capacitor which is comprised of a storage node, a dielectric layer, and a plate node. The storage node may be electrically connected onto each of the conductive structures 105, 105B, 125, and 125D. The memory element may be constructed in a variety of ways. For example, the memory element may include a resistance variable material. The memory element may include a first electrode, a resistance variable material and a second electrode which are sequentially stacked, and the first electrode may be electrically connected to each of the conductive structures 105, 105B, 125, and 125D. Data may be stored by using the fact that the resistance of the resistance variable material is changed according to the voltages applied to the first electrode and the second electrode. The resistance variable material may include a phase change material or a magnetic tunnel junction.
Referring to
By etching the first dielectric layer 12, an opening 13 is defined in the first dielectric layer 12 to expose the surface of the substrate 11. The opening 13 has a hole shape or a line shape. The opening 13 may include a contact hole, a via hole, a through hole, a trench, a recess, or the like. A plurality of openings 13 may be formed in the first dielectric layer 12 at regular intervals to define an opening array. In order to etch the first dielectric layer 12, a mask pattern (not shown) may be used. The mask pattern includes a photoresist pattern or a hard mask pattern that is patterned using a photoresist pattern. The surface of the substrate 11 which is exposed by the opening 13 may include an impurity region.
A second dielectric layer 14A is formed. The second dielectric layer 14A is formed over the first dielectric layer 12 including the opening 13. The second dielectric layer 14A is a material to be a liner or spacer. The second dielectric layer 14A is conformally formed with a thin thickness that does not fill the opening 13. The second dielectric layer 14A includes a low-k material. The second dielectric layer 14A may include silicon nitride or silicon oxide. For example, the first dielectric layer 12 may include silicon oxide, and the second dielectric layer 14A may include silicon nitride. In an alternative embodiment, the second dielectric layer 14A may be omitted.
A sacrificial layer 15A is formed on the second dielectric layer 14A. The sacrificial layer 15A is conformally formed on the second dielectric layer 14A with a thin thickness that does not fill the opening 13. The sacrificial layer 15A includes a material which may be removed by wet etching. The sacrificial layer 15A may include a material different from the first dielectric layer 12 and the second dielectric layer 14A. The sacrificial layer 15A includes metal nitride. The sacrificial layer 15A may include titanium nitride (TiN).
Referring to
Referring to
Referring to
After the sacrificial spacer 15 is removed by the strip process, spaces occupied by the sacrificial spacer 15 remain as an air gap 17. The air gap 17 is defined between the first conductive pattern 16A and the sidewalls of the opening 13. Accordingly, a dielectric structure constituted by the air gap 17 and the spacer 14 is formed between the first conductive pattern 16A and the sidewalls of the opening 13. When the spacer 14 is omitted, a dielectric structure constituted by the air gap 17 is formed between the first conductive pattern 16A and the sidewalls of the opening 13.
Referring to
Hereinafter, in the exemplary embodiment, the silicidable layer 18 includes cobalt.
A capping layer 19 is formed on the silicidable layer 18. The capping layer 19 is conformally formed. The capping layer 19 prevents a silicide layer to be subsequently formed, from being attacked. The capping layer 19 is formed by atomic layer deposition (ALD). The capping layer 19 includes metal nitride. The capping layer 19 includes a titanium-containing material. The capping layer 19 may include titanium nitride. The capping layer 19 may be formed by stacking titanium and titanium nitride. The capping layer 19 may be formed in the air gap 17 or may not be formed in the air gap 17. For example, when the silicidable layer 18 is formed without gap-filling the air gap 17, the capping layer 19 may be formed in the air gap 17. In the case when the silicidable layer 18 is formed to gap-fill the air gap 17, the capping layer 19 is not formed in the air gap 17.
According to the above descriptions, the silicidable layer 18 is formed to cover the top surface and the sidewalls of the first conductive pattern 16A. Therefore, because the contact area between the first conductive pattern 16A and the silicidable layer 18 increases, an area for forming a silicide layer to be subsequently formed increases.
Referring to
As the annealing process 21 is performed, the silicon of the first conductive pattern 16A and the metal of the silicidable layer 18 react with each other, and a metal silicide layer is formed. The metal silicide layer may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. Since the first conductive pattern 16A includes polysilicon and the silicidable layer 18 includes cobalt, a cobalt silicide layer is formed by the annealing process 21.
For example, in order to form the cobalt silicide layer, the annealing process 21 may be performed twice. By a primary annealing process, cobalt silicide with a phase of CoSix (x=0.1˜1.5) is formed. A secondary annealing process is performed after the primary annealing process. The secondary annealing process may be performed at a temperature higher than the primary annealing process. The secondary annealing process is performed at a temperature ranging from approximately 600° C. to approximately 800° C. A phase change of the cobalt silicide layer occurs by the secondary annealing process. For example, a phase change to cobalt silicide with the phase of CoSi2 occurs by the secondary annealing process. The resistivity of the cobalt silicide with the phase of CoSi2 is lower than the cobalt silicide with the phase of CoSix (x=0.1˜1.5). By forming the cobalt silicide with the phase of CoSi2, contact resistance may be reduced, and at the same time, it is possible to form cobalt silicide with a lower resistance even in the small area of the opening 13 with a fine line width. The secondary annealing process may be performed after removing an unreacted silicidable layer 18A.
Because the second conductive pattern 20 is formed by consuming the silicon of the first conductive pattern 16A, the first conductive pattern 16A may be reduced in its volume as indicated by the reference numeral ‘16’. After the annealing process 21, the first conductive pattern 16 is covered by the second conductive pattern 20.
As described above, the second conductive pattern 20 which covers the top surface and the sidewalls of the first conductive pattern 16 is formed by the annealing process 21. The second conductive pattern 20 serves as an ohmic contact layer between the first conductive pattern 16 and a third conductive pattern to be subsequently formed.
The unreacted silicidable layer 18A may remain on the second conductive pattern 20.
Referring to
By the strip process, the unreacted silicidable layer 18A is removed, and the air gap 17 is opened again. The volumes of the air gap 17 may be identical to or smaller than the initially defined air gap 17.
Referring to
Referring to
The air gap 17 is defined between the first conductive pattern 16C and the sidewalls of the opening 13.
The first conductive pattern 16C according to the second embodiment may be formed by performing a fully-silicidation process when performing the annealing process 21 in
Referring to
Referring to
Referring to
Accordingly, a conductive structure 24 including the first conductive pattern 16, the second conductive pattern 20, and the third conductive pattern 23 is formed in the opening 13. The air gap 17 is defined between the conductive structure 24 and the sidewalls of the opening 13. The second conductive pattern 20 forms an ohmic contact between the first conductive pattern 16 and the third conductive pattern 23. The air gap 17 is defined between the second conductive pattern 20 and the sidewalls of the opening 13. A dielectric structure including the air gap 17 and the spacer 14 is formed between the conductive structure 24 and the sidewalls of the opening 13.
Referring to
By forming the barrier layer 25A, it is possible to cap the air gap 17 without filling the insides of the air gap 17.
A glue layer 26A is formed on the barrier layer 25A. The glue layer 26A includes a conductive material. The glue layer 26A includes a titanium-containing layer. The glue layer 26A may include titanium nitride (TiN). The glue layer 26A is formed by CVD.
A third conductive layer 27A is formed. The third conductive layer 27A fills the remainder of the opening 13 on the glue layer 26A. The third conductive layer 27A may include a metal-containing layer. The third conductive layer 27A may include a tungsten layer. The third conductive layer 27A is formed by CVD.
Referring to
As the barrier pattern 25, the glue pattern 26 and the third conductive pattern 27 are formed, a conductive structure 28 is formed in the opening 13. The conductive structure 28 includes the first conductive pattern 16, the second conductive pattern 20, the barrier pattern 25, the glue pattern 26 and the third conductive pattern 27. The second conductive pattern 20 forms an ohmic contact between the first conductive pattern 16 and the third conductive pattern 27. The barrier pattern 25 caps the air gap 17. The glue pattern 26 increases the adhesion force between the second conductive pattern 20 and the third conductive pattern 27. The barrier pattern 25 and the glue pattern 26 prevent inter-diffusion between the second conductive pattern 20 and the third conductive pattern 27. The air gap 17 is defined between the second conductive pattern 20 and the sidewalls of the opening 13. A dielectric structure including the air gap 17 and the spacer 14 is formed between the conductive structure 28 and the sidewalls of the opening 13.
By the air gap capping methods shown in
The conductive structure 24 and 28 may become a plug, an electrode, or the like. For example, when the conductive structure 24 and 28 is a plug, the conductive structure 24 and 28 may be constituted by a stack structure of a silicon plug, an ohmic contact layer, and a metal plug, and the air gap 17 is defined around the silicon plug. The first conductive pattern 16 becomes the silicon plug, the third conductive pattern 23 and 27 becomes the metal plug, and the second conductive pattern 20 becomes the ohmic contact layer. Further, the conductive structure 24 and 28 may become a bit line, a metal line, a gate electrode, a word line, a through electrode, or the like.
According to the first embodiment and the modification thereof, as the air gap 17 is defined, the electrical insulation characteristics of the conductive structure 24 and 28 may be improved. For example, in the case where another conductive pattern is disposed adjacent to the first conductive pattern 16, the parasitic capacitance between the two conductive patterns may be reduced.
Moreover, since the second conductive pattern 20 includes a silicide layer, the sheet resistance (Rs) of the conductive structure 24 and 28 may be reduced. In particular, since a low resistance silicide layer is included, the sheet resistance (Rs) of the conductive structure 24 and 28 may be further reduced. As the sheet resistance (Rs) is reduced, a contact resistance (Rc) may be improved.
Further, since the contact area between the first conductive pattern 16 and the second conductive pattern 20 increases, the contact resistance (Rc) of the conductive structure 24 and 28 may be further improved.
Furthermore, it is possible to cap the air gap 17 using a conductive material without using a dielectric material. As a consequence, a parasitic capacitance (Cb) may be reduced due to the air gap 17, a sheet resistance (Rs) may be reduced by the low resistance silicide layer, and the contact resistance (Rc) of the conductive structure 24 and 28 may be improved attributable to an increase in the contact area between the first conductive pattern 16 and the second conductive pattern 20.
Referring to
The substrate 201 may include a silicon substrate, a silicon germanium substrate, or an SOI substrate.
Each of the first conductive structures 204 includes the first conductive pattern 202. Each first conductive structure 204 may include a stack structure of the first conductive pattern 202 and the dielectric pattern 203. The first conductive pattern 202 may include a silicon-containing layer or a metal-containing layer. The first conductive pattern 202 may include a stack structure of a silicon-containing layer and a metal-containing layer. The first conductive pattern 202 may include polysilicon, metal, metal nitride, or metal silicide. The first conductive pattern 202 may include a stack structure of a polysilicon layer and a metal layer. The metal layer may include tungsten. The dielectric pattern 203 includes a dielectric material. The dielectric pattern 203 may include oxide or nitride. Each of the first conductive structures 204 has a line shape or a pillar shape.
Each of the second conductive structure 205 includes the second conductive pattern 206. The second conductive pattern 206 is formed in such a way as to be recessed between adjacent first conductive structures 204. The second conductive structure 205 may include a stack structure of the second conductive pattern 206, the third conductive pattern 207, the barrier pattern 211, the glue pattern 212, and the fourth conductive pattern 208. The height of the second conductive pattern 206 is identical to or larger than the first conductive pattern 202. An interlayer dielectric layer (not shown) which has openings between adjacent first conductive structures 204 may be formed, and the second conductive structures 205 may be formed in the openings. Each of the openings may have a shape which exposes the sidewalls of adjacent first conductive structures 204. The third conductive pattern 207 covers the top surface and the sidewalls of the second conductive pattern 206. The air gaps 209 are defined between the third conductive patterns 207 and the first conductive patterns 202. The third conductive patterns 207 and the air gaps 209 are capped by the barrier patterns 211. The second conductive pattern 206 includes a silicon-containing material. The second conductive pattern 206 may include polysilicon. The fourth conductive pattern 208 includes a metal-containing material. The fourth conductive pattern 208 may include tungsten. The third conductive pattern 207 includes silicide. The third conductive pattern 207 may include metal silicide. For instance, the third conductive pattern 207 may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. In the exemplary embodiment, the third conductive pattern 207 includes cobalt silicide. The third conductive pattern 207 includes cobalt silicide with a phase of CoSi2. Each of the barrier patterns 211 covers the top surface and the sidewalls of an upper portion of the third conductive pattern 207 and caps the air gaps 209. The barrier pattern 211 does not fill the air gaps 209 but caps the air gaps 209. The barrier patterns 211 cover the sidewalls of the first conductive structures 204 over the air gaps 209. The barrier patterns 211 include a metal-containing material. The barrier patterns 211 may include titanium. The glue patterns 212 include a metal-containing material. The glue patterns 212 may include titanium nitride (TiN). Each of the second conductive structures 205 has a line shape or a pillar shape.
The spacers 210 are formed on the sidewalls of the first conductive structures 204. The spacers 210 include a low-k material. The low-k material includes oxide or nitride. The spacers 210 may include silicon oxide, silicon nitride or metal oxide.
The air gaps 209 may be defined by removing a sacrificial material formed between the third conductive patterns 207 and the spacers 210.
Referring to
In
Referring to
The second conductive patterns 228 include silicide. The second conductive patterns 228 may include metal silicide. The second conductive patterns 228 include metal silicide which is formed by deposition. The metal silicide may be formed by CVD. The second conductive patterns 228 may include metal silicide which is formed by a fully-silicidation process. The second conductive patterns 228 may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. In the exemplary embodiment, the second conductive patterns 228 include cobalt silicide. The second conductive patterns 228 include cobalt silicide with the phase of CoSi2.
Referring to
In
While not shown, in each of the semiconductor devices shown in
Referring to
The plurality of first conductive structures 34 is disposed at regular intervals. Each of the first conductive structures 34 may have a line shape. In order to form the first conductive structures 34, hard mask patterns 33 are formed on a first conductive layer (not shown). By etching the first conductive layer using the hard mask patterns 33 as an etch mask, first conductive patterns 32 are formed. In each of the first conductive structures 34, the first conductive pattern 32 and the hard mask pattern 33 are stacked and formed. The first conductive patterns 32 include a silicon-containing layer or a metal-containing layer. For example, the first conductive patterns 32 may include polysilicon or tungsten. The first conductive patterns 32 may be formed by stacking a silicon-containing layer and a metal-containing layer. For example, the first conductive patterns 32 may be formed by stacking a polysilicon layer and a tungsten layer. A barrier layer (not shown) may be formed between the polysilicon layer and the tungsten layer. The first conductive patterns 32 may include a stack structure of a polysilicon layer, a titanium layer and a tungsten layer. The titanium layer as the barrier layer may be formed by stacking titanium (Ti) and titanium nitride (TiN). The hard mask patterns 33 are formed using a dielectric material.
A first dielectric layer 35A is formed on the plurality of first conductive structures 34. The first dielectric layer 35A includes a low-k material. The first dielectric layer 35A includes nitride or oxide. For instance, the first dielectric layer 35A may include silicon nitride or silicon oxide. The first dielectric layer 35A is conformally formed on the entire surface of the resultant structure including the first conductive structures 34. The first dielectric layer 35A is a material which will become spacers.
A second dielectric layer 36A is formed on the first dielectric layer 35A. The second dielectric layer 36A may include silicon oxide. The second dielectric layer 36A may be formed on the first dielectric layer 35A in such a way as to fill the spaces between the first conductive structures 34. The second dielectric layer 36A becomes an interlayer dielectric layer.
Referring to
Openings 37 are defined in the second dielectric layer 36A which has been planarized. The openings 37 are defined by etching the planarized second dielectric layer 36A shown in
The first dielectric layer 35A may remain on the substrate 31 on the bottoms of the openings 37.
Referring to
In an alternative embodiment, after defining the openings 37, the first dielectric layer 35A and the sacrificial layer 38A may be sequentially formed. Accordingly, the first dielectric layer 35A and the sacrificial layer 38A are formed to cover the surface of exposed portions of the substrate 31, the sidewalls of the openings 37, and the top surfaces of the hard mask patterns 33.
Referring to
Referring to
By forming the second conductive patterns 39A to be recessed in the openings 37 between the first conductive structures 34, portions of the sacrificial spacers 38 are exposed.
Referring to
After the sacrificial spacers 38 are removed by the strip process, and the spaces occupied by the sacrificial spacers 38 remain as air gaps 40. The air gaps 40 are defined between the second conductive patterns 39A and the sidewalls of the openings 37. Accordingly, dielectric structures constituted by the air gaps 40 and the spacers 35 are formed between the second conductive patterns 39A and the sidewalls of the openings 37.
Referring to
Hereinafter, in the exemplary embodiment, the silicidable layer 41 includes cobalt.
A capping layer 42 is formed on the silicidable layer 41. The capping layer 42 is conformally formed. The capping layer 42 prevents a silicide layer to be subsequently formed, from being attacked. The capping layer 42 is formed by atomic layer deposition (ALD). The capping layer 42 includes metal nitride. The capping layer 42 includes a titanium-containing material. The capping layer 42 may include titanium nitride (TiN). The capping layer 42 may be formed by stacking titanium and titanium nitride. The capping layer 42 may be formed in the air gaps 40 or may not be formed in the air gaps 40. For example, when the silicidable layer 41 is formed without gap-filling the air gaps 40, the capping layer 42 may be formed in the air gaps 40. In the case when the silicidable layer 41 is formed to gap-fill the air gaps 40, the capping layer 42 is not formed in the air gaps 40.
According to the above descriptions, the silicidable layer 41 is formed to cover the top surfaces and the sidewalls of the second conductive patterns 39A. Therefore, because the contact area between each second conductive pattern 39A and the silicidable layer 41 increases, an area for forming a silicide layer to be subsequently formed increases.
Referring to
As the annealing process 43 is performed, the silicon of the second conductive patterns 39A and the metal of the silicidable layer 41 react with each other, and a metal silicide layer is formed. The metal silicide layer may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. Since the second conductive patterns 39A include polysilicon and the silicidable layer 41 includes cobalt, a cobalt silicide layer is formed by the annealing process 43.
In order to form the cobalt silicide layer, the annealing process 43 may be performed twice. By a primary annealing process, cobalt silicide with a phase of CoSix (x=0.1˜1.5) is formed. A secondary annealing process is performed after the primary annealing process. The secondary annealing process may be performed at a temperature higher than the primary annealing process. The secondary annealing process is performed at a temperature ranging from approximately 600° C. to approximately 800° C. A phase change of the cobalt silicide layer occurs by the secondary annealing process. For example, a phase change to cobalt silicide with the phase of CoSi2 occurs by the secondary annealing process. The resistivity of the cobalt silicide with the phase of CoSi2 is lower than the cobalt silicide with the phase of CoSix (x=0.1˜1.5). By forming the cobalt silicide with the phase of CoSi2, contact resistance may be reduced, and at the same time, it is possible to form cobalt silicide with a lower resistance even in the small area of each opening 37 with a fine line width. The secondary annealing process may be performed after removing an unreacted silicidable layer 41A.
Because the third conductive patterns 44 are formed by consuming the silicon of the second conductive patterns 39A, the second conductive patterns 39A may be reduced in their volumes as indicated by the reference numeral 39. After the annealing process 43, the second conductive patterns 39 are covered by the third conductive patterns 44.
As described above, the third conductive patterns 44 which cover the top surfaces and the sidewalls of the second conductive patterns 39 are formed by the silicidation reaction. The third conductive patterns 44 serve as an ohmic contact layer between the second conductive patterns 39 and fourth conductive patterns to be subsequently formed.
The unreacted silicidable layer 41A may remain on the third conductive patterns 44.
Referring to
By the strip process, the unreacted silicidable layer 41A is removed. Accordingly, the air gaps 40 are opened again. Since the air gaps 40 are defined between the third conductive patterns 44 and the sidewalls of the openings 37, dielectric structures constituted by the air gaps 40 and the spacers 35 are formed between the third conductive patterns 44 and the sidewalls of the openings 37. The volumes of the air gaps 40 may be identical to or smaller than the initially defined air gaps 40.
Referring to
Accordingly, second conductive structures 46 are formed in the openings 37. Each of the second conductive structures 46 includes the second conductive pattern 39, the third conductive pattern 44, and the fourth conductive pattern 45. The third conductive pattern 44 forms an ohmic contact between the second conductive pattern 39 and the fourth conductive pattern 45. The air gaps 40 are defined between the third conductive patterns 44 and the sidewalls of the openings 37. When the openings 37 are self-aligned with the sidewalls of the first conductive structures 34, the air gaps 40 may be defined between the third conductive patterns 44 and the first conductive patterns 32. Dielectric structures including the air gaps 40 and the spacers 35 are formed between the second conductive structures 46 and the first conductive structures 34.
Referring to
According to the third embodiment and the modification thereof, by defining the air gaps 40, the parasitic capacitance between the first conductive structures 34 and the second conductive structures 46 and 50 may be reduced.
Additionally, since the third conductive patterns 44 include a silicide layer, the sheet resistance (Rs) of the second conductive structures 46 and 50 may be reduced. In particular, since a low resistance silicide layer is included, the sheet resistance (Rs) of the second conductive structures 46 and 50 may be further reduced. As the sheet resistance (Rs) is reduced, a contact resistance (Rc) may be improved.
Furthermore, it is possible to cap the air gaps 40 using a conductive material without using a dielectric material. As a consequence, a parasitic capacitance (Cb) may be reduced due to the air gaps 40, a sheet resistance (Rs) may be reduced by the low resistance silicide layer, and the contact resistance (Rc) of the second conductive structures 46 and 50 may be improved.
Referring to
Each of the bit line structures 310 includes a bit line 307, a bit line hard mask 308, and a bit line spacer 309. The bit line 307 is connected with the active region 303 through a bit line contact plug 306. The bit line contact plug 306 is formed in a bit line contact hole 305 that is defined in a first interlayer dielectric layer 304.
Storage node contact plugs 312 are formed to be connected with the active regions 303. The storage node contact plugs 312 are formed in storage node contact holes 311 that penetrate the first interlayer dielectric layer 304 and a second interlayer dielectric layer 304A. Each of the storage node contact plugs 312 includes a first plug 313, an ohmic contact layer 314, a barrier pattern 315, a glue pattern 316 and a second plug 317. The first plug 313 is a silicon plug which includes polysilicon. The second plug 317 is a metal plug which includes tungsten. The ohmic contact layer 314 covers the top surface and the sidewalls of the first plug 313.
Dielectric structures including air gaps 318 and spacers 319 are formed between the storage node contact plugs 312 and the bit lines 307. The air gaps 318 are capped by the barrier patterns 315. The air gaps 318 and the barrier patterns 315 may be defined and formed by applying the methods described in the exemplary embodiments.
Capacitors including storage nodes 320 are connected to the storage node contact plugs 312. Each of the storage nodes 320 has a pillar shape. While not shown, a dielectric layer and plate nodes may be formed on the storage nodes 320. Each of the storage nodes 320 may have a cylinder shape instead of the pillar shape.
As can be seen from the above descriptions, each memory cell includes a buried gate type transistor including the buried gate electrode 323, the bit line 307, the storage node contact plug 312, and the capacitor including storage nodes 320. The storage node contact plug 312 is separated from the sidewalls of the bit lines 307 by the air gaps 318. Therefore, the parasitic capacitance between the bit line 307 and the storage node contact plug 312 may be reduced.
Referring to
Referring to
While not shown, after forming the isolation regions 52, buried gate electrodes (see the reference numeral ‘323’ in
Hereinafter, a method for forming the buried gate electrodes will be described with reference to
First, after defining the gate trenches 321 by etching the substrate 301, the buried gate electrodes 323 are formed to be recessed in the gate trenches 321. Thereafter, the sealing layer 324 is formed on the buried gate electrodes 323. Before forming the buried gate electrodes 323, the gate dielectric layer 322 may be formed along the surface of the gate trenches 321. The buried gate electrodes 323 may be formed by forming a metal-containing layer to fill the gate trenches 321 and then etching back the metal-containing layer. The metal-containing layer may include a material which includes metal, such as titanium, tantalum, and tungsten, as a main constituent. The metal-containing layer may include at least any one selected from the group consisting of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and tungsten (W). For example, the buried gate electrodes 323 may include a single layer structure having any of titanium nitride, tantalum nitride, and tungsten, or may include a dual layer structure such as TiN/W or TaN/W in which tungsten (W) is stacked on titanium nitride (TiN) or tantalum nitride (TaN). Also, the buried gate electrodes 323 may include a dual layer structure such as WN/W in which tungsten (W) is stacked on a tungsten nitride (WN), and also may include a low-resistance metal material. The sealing layer 324 may fill the gate trenches 321 on the buried gate electrodes 323. The sealing layer 324 may protect the buried gate electrodes 323 from a subsequent process. The sealing layer 324 may include a dielectric material. The sealing layer 324 may include silicon nitride. After forming the sealing layer 324, source regions and drain regions (not shown) may be formed in the active regions 303. Consequently, buried gate type transistors including the buried gate electrodes 323 are formed.
Referring back to
A bit line contact hole 55 is defined by etching the first interlayer dielectric layer 54A. In order to define the bit line contact hole 55, mask patterns (not shown) may be used as an etch mask. After defining the bit line contact hole 55, the active regions 53 may be recessed by a set depth. Accordingly, it is possible to increase the contact area between a bit line contact plug 56 to be subsequently formed and the active regions 53. The active regions 53 which are exposed by the bit line contact hole 55 include any one of source regions and drain regions of the buried gate type transistors.
The bit line contact plug 56 is formed in the bit line contact hole 55. The bit line contact plug 56 is formed in the bit line contact hole 55. To form the bit line contact plug 56, after forming a conductive layer (not shown) on the entire surface of the resultant structure to fill the bit line contact hole 55, the conductive layer may be planarized. The bit line contact plug 56 may include a polysilicon layer or a metal layer.
Bit lines 57 and bit line hard masks 58 are formed on the bit line contact plug 56. In an alternative embodiment, a line width of the bit lines 57 and the bit line hard masks 58 may be set to be smaller than the bit line contact hole 55 such as to etch the bit line contact plug 56. In this case, although the sidewalls of the bit line contact hole 55 may be exposed as the bit line contact plug 56 is etched, the exposed sidewalls may be filled by bit line spacers 59 which are to be subsequently formed. The bit lines 57 include a metal-containing layer such as tungsten. The bit line hard masks 58 include silicon nitride.
The bit line spacers 59 are formed on the sidewalls of the bit lines 57 and the bit line hard masks 58. The bit line spacers 59 may include silicon nitride.
By forming the bit line spacers 59 as described above, bit line structures 60 each including the bit line 57, the bit line hard mask 58 and the bit line spacers 59 are formed.
While not shown, the process for forming the bit line structures 60 may be performed simultaneously with a process for forming the gate structures of transistors formed in a peripheral circuit region. Gate structures including silicon electrodes the same as bit line contact plugs and metal electrodes the same as bit lines, may be formed.
A second interlayer dielectric layer 61 is formed on the entire surface of the resulting structure including the bit line structures 60. The second interlayer dielectric layer 61 may be subsequently patterned or planarized to fill the spaces between adjacent bit line structures 60.
Referring to
Referring to
First plugs 65A are formed in the storage node contact holes 62. The first plugs 65A fill a part of the storage node contact holes 62. That is, the first plugs 65A are formed in such a way as to be recessed in the storage node contact holes 62. The first plugs 65A are formed by forming a conductive layer (not shown) on the entire surface of the resulting structure to fill the storage node contact holes 62 and then recessing the conductive layer. The recessed surfaces of the first plugs 65A may be controlled to be higher than the top surface of the bit lines 57. The first plugs 65A may have a height to minimize an area between each first plug 65A and each bit line 57 arranged opposite one another. Accordingly, the parasitic capacitance between the bit lines 57 and the first plugs 65A may be reduced. The first plugs 65A include a silicon-containing layer. The first plugs 65A may include a polysilicon layer. The first plugs 65A become silicon plugs.
By forming the recessed first plugs 65A, the top surfaces and the sidewalls of the sacrificial spacers 64 are exposed.
Referring to
After the sacrificial spacers 64 are removed by the strip process, the spaces occupied by the sacrificial spacers 64 remain as air gaps 66.
The air gaps 66 are defined between the first plugs 65A and the sidewalls of the storage node contact holes 62. Dielectric structures comprised of the air gaps 66 and the spacers 63 are formed between the first plugs 65A and the bit line structures 60.
Referring to
Hereinafter, in the exemplary embodiment, the silicidable layer 67 includes cobalt.
A capping layer 68 is formed on the silicidable layer 67. The capping layer 68 is conformally formed. The capping layer 68 prevents a silicide layer to be subsequently formed, from being attacked. The capping layer 68 is formed by ALD. The capping layer 68 includes metal nitride. The capping layer 68 includes a titanium-containing material. The capping layer 68 may include titanium nitride (TiN). The capping layer 68 may be formed by stacking titanium and titanium nitride. The capping layer 68 may be formed in the air gaps 66 or may not be formed in the air gaps 66. For example, when the silicidable layer 67 is formed without gap-filling the air gaps 66, the capping layer 68 may be formed in the air gaps 66. When the silicidable layer 67 gap-fills the air gaps 66, the capping layer 68 is not formed in the air gaps 66.
According to the above descriptions, the silicidable layer 67 is formed to cover the top surfaces and the sidewalls of the first plugs 65A. Therefore, because the contact area between the first plug 65A and the silicidable layer 67 increases, an area for forming a silicide layer to be subsequently formed increases.
Referring to
As the annealing process 69 is performed, the silicon of the first plugs 65A shown in
In order to form the cobalt silicide layer, the annealing process 69 may be performed twice. By a primary annealing process, cobalt silicide with a phase of CoSix (x=0.1˜1.5) is formed. A secondary annealing process is performed after the primary annealing process. The secondary annealing process may be performed at a temperature higher than the primary annealing process. The secondary annealing process is performed at a temperature ranging from approximately 600° C. to approximately 800° C. A phase change of the cobalt silicide layer occurs by the secondary annealing process. For example, a phase change to cobalt silicide with the phase of CoSiz occurs by the secondary annealing process. The resistivity of the cobalt silicide with the phase of CoSi2 is lower than the cobalt silicide with the phase of CoSix (x=0.1˜1.5). By forming the cobalt silicide with the phase of CoSi2, it is possible to form cobalt silicide with a lower resistance. The secondary annealing process may be performed after removing an unreacted silicidable layer 67A.
Because the ohmic contact layer 70 is formed by consuming the silicon of the first plugs 65A shown in
As described above, the ohmic contact layer 70 which covers the top surfaces and sidewalls of the first plugs 65 is formed by the silicidation reaction.
The unreacted silicidable layer 67A may remain on the ohmic contact layer 70.
Referring to
By the strip process, the unreacted silicidable layer 67A shown in
Referring to
In this way, the barrier patterns 71, the glue patterns 72 and the second plugs 73 are formed on the ohmic contact layer 70. Accordingly, storage node contact plugs 74 formed in the storage node contact holes 62 include the first plugs 65, the ohmic contact layer 70, the barrier patterns 71, the glue patterns 72 and the second plugs 73. The ohmic contact layer 70 forms ohmic contacts between the first plugs 65 and the second plugs 73. When the first plugs 65 include a silicon-containing layer and the second plugs 73 include a metal-containing layer, the first plugs 65 and the second plugs 73 become semi-metal plug structures.
The air gaps 66 are defined between the first plugs 65 and the sidewalls of the storage node contact holes 62. Dielectric structures constituted by the air gaps 66 and the spacers 63 are formed between the storage node contact plugs 74 and the bit line structures 60. The air gaps 66 are capped by the barrier patterns 71.
In an alternative embodiment, the air gaps 66 and the ohmic contact layer 70 may be capped using only the second plugs 73.
Referring to
The semiconductor devices according to the exemplary embodiments may be applied to a dynamic random access memory (DRAM), without a limiting sense, and may also be limited to a memory such as a static RAM (SRAM), a flash memory, a ferroelectric RAM (FeRAM), a magnetic RAM (MRAM) and a phase change RAM (PRAM).
Referring to
Referring to
Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Lee, Nam-Yeal, Yeom, Seung-Jin
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