Disclosed are a jig for measuring emc of a semiconductor chip and a method for measuring emc that can accurately measure the emc at a semiconductor chip level. The jig for measuring emc of a semiconductor chip according to the exemplary embodiment of the present disclosure includes: a chip mount unit on which the semiconductor chip for which the emc is to be measured is mounted; a memory unit configured to store emc information of components in a system in which the semiconductor chip is used; and a measurement control unit configured to extract the emc information stored in the memory unit and provide the extracted emc information to the chip mount unit at the time of measuring the emc of the semiconductor chip.
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2. A jig for measuring electro magnetic compatibility (emc) at a semiconductor chip level, comprising:
a chip mount unit on which a semiconductor chip, for which the emc is to be measured, is mounted;
a memory unit configured to store emc information of components in a system in which the semiconductor chip is used; and
a measurement control unit configured to extract the emc information stored in the memory unit and provide the extracted emc information to the chip mount unit at a time of measuring the emc of the semiconductor chip.
8. A method for measuring electro magnetic compatibility (emc)of a semiconductor chip, comprising:
mounting the semiconductor chip for which the emc is to be measured on a jig;
implementing predetermined operation environments of a system in which the semiconductor chip is used through the jig, wherein the jig stores emc information of components in the system according to an operation situation of the system and implements the predetermined operation environments of the system by using the stored emc information; and
measuring the emc of the semiconductor chip under the implemented operation environments.
1. A jig for measuring electro magnetic compatibility (emc) at a semiconductor chip level, comprising:
a chip mount unit on which a semiconductor chip, for which the emc is to be measured, is mounted; and
a memory unit storing various operation environments including emc information of components in the same operation environment of the same system in which the semiconductor chip is used, each of the components being different from all other of the components and having different emc characteristics from all the other of the components,
wherein the same operation environment of the same system, in which the semiconductor chip is used, is implemented in the chip mount unit at a time of measuring the emc of the semiconductor chip by using the emc information.
3. The jig of
4. The jig of
a general database configured to store general information required for a general function test of the semiconductor chip;
an emc database configured to store emc information of components in the system according to an operation situation of the system into a database;
a data selection unit configured to provide the general or emc information stored in the general database or the emc database to the chip mount unit by control of the measurement control unit; and
a measurement database configured to store a measurement result of the chip mount unit.
5. The jig of
a signal input unit configured to receive a plurality of control signals for driving the jig; and
a measurement result output unit configured to output the measurement result of the emc for the semiconductor chip.
6. The jig of
7. The jig according to
9. The method according to
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This application is based on and claims priority from Korean Patent Application No. 10-2012-0008210 , filed on Jan. 27, 2012 , with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The present disclosure relates to a jig for measuring electro magnetic compatibility (EMC) at a semiconductor chip level and a method for measuring EMC using the same.
EMC means the capability of electronic equipment that can coexist with other equipment under an environment in which electronic equipment generates without mutually causing degradation or loss of function. Today, electronic equipment manufactured in international markets needs to coincide with numerous regulations associated with the EMC and product stability presented by governmental organizations, private standard groups, self-regulation associations and the like.
EMC measurement in the related art is generally performed at a printed circuit board level, that is, a system level, and for the EMC measurement, a TEM cell (including a GTEM cell) method, a surface scan method, a bulk current injection (BCI) method, a direct power injection (DPI) method, a workbench Faraday cage method and the like are used. However, the influence of each of internal semiconductor chips or components cannot be known by the system-level measurement.
A method using a jig on which the semiconductor chips can be mounted may be considered in order to measure EMC at a semiconductor chip level. However, when a general jig in the related art is used, it is difficult to reflect a real operation situation of the system in the EMC measurement, and as a result, it is difficult to accurately measure the EMC with respect to the semiconductor chip.
As one example, a case of measuring EMC of a chip for a micro controller unit 105 used in a tire pressure monitoring system (TPMS) 100 among automobile semiconductor chips will be described through
As illustrated in
Among them, when a jig mounted with the MCU 105 is manufactured in order to measure EMC of the chip for the MCU 105, according to the related art, only the MCU 105 is mounted on the jig, and as a result, interactions with other components including the tire pressure sensor 101, the A/D converter 103, and the like constituting the TPMS 100 are not considered. Since the components have different characteristics for each model of each manufacturing company, EMC characteristics thereof have no choice but to be different, but the jig is manufactured without considering the matters.
The present disclosure has been made in an effort to provide a jig for measuring EMC of a semiconductor chip and a method for measuring EMC that can accurately measure the EMC at a semiconductor chip level by providing means that can allow various operation environments of a system in which the semiconductor chip is used into a database and store the database within a jig.
An exemplary embodiment of the present disclosure provides a jig for measuring EMC of a semiconductor chip, including: a chip mount unit on which the semiconductor chip for which the EMC is to be measured is mounted; a memory unit configured to store EMC information of components in a system in which the semiconductor chip is used; and a measurement control unit configured to extract the EMC information stored in the memory unit and provide the extracted EMC information to the chip mount unit at the time of measuring the EMC of the semiconductor chip. The jig may further include: a signal input unit configured to receive a plurality of control signals for driving the jig; and a measurement result output unit configured to output the measurement result of the EMC for the semiconductor chip.
The chip mount unit may implement various operation environments of the system in which the semiconductor chip is used by using the EMC information provided from the memory unit at the time of measuring the EMC of the semiconductor chip.
The memory unit may include: a general database configured to store information required for a general function test of the semiconductor chip; an EMC database configured to make EMC information of components in the system according to an operation situation of the system into a database and store the EMC data; a data selection unit configured to provide the information stored in the general database or the EMC database to the chip mount unit by the control of the measurement control unit; and a measurement database configured to store a measurement result of the chip mount unit.
Another exemplary embodiment of the present disclosure provides a method for measuring EMC of a semiconductor chip, including: mounting the semiconductor chip for which the EMC is to be measured on a jig; implementing predetermined operation environments of a system in which the semiconductor chip is used through the jig; and measuring the EMC of the semiconductor chip under the implemented operation environments.
According to the exemplary embodiments of the present disclosure, the EMC can be measured at the level of each of the semiconductor chips constituting the system.
EMC information on the components in the system in which the semiconductor chip is used is made into the database and stored in the memory of the jig, and the information stored at the time of measuring EMC is used to measure the EMC of the semiconductor chip while various real operation environments of the system are reflected.
The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.
In the following detailed description, reference is made to the accompanying drawing, which form a part hereof. The illustrative embodiments described in the detailed description, drawing, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.
Referring to
In the present disclosure, EMC information under various operation situations of the components in the system in which the semiconductor chip for which the EMC is to be measured is used is made into a database and is stored in the memory unit 203, and the EMC information stored in the memory unit 203 is referred at the time of measuring the EMC of the semiconductor chip so as to reflect an operating environment in an actually implemented system as it is.
The signal input unit 207 receives a plurality of control signals including all signals for driving the jig, that is, a mode signal for determining whether the EMC is measured for the semiconductor chip, a clock signal for synchronizing the jig and the semiconductor chip, a voltage signal for driving the memory unit 203 and a reset signal and transfers the received control signals to the respective components in the jig. Herein, it may be determined by the mode signal whether the EMC of the semiconductor chip mounted on the jig will be measured or whether a general function test will be performed.
Referring to
Information required for the general function test of the semiconductor chip is stored in the general database 301 and the EMC information of the components in the system according to various operation situations of the system is made into the database and stored in the EMC database 303. The data selection unit 307 provides the information stored in the general database 301 or the EMC database 303 to the chip mount unit 201 by the control of the measurement control unit 205.
In detail, only the information stored in the general database 301 may be extracted to be transferred to the chip mount unit 201 through the data selection unit 307 at the time of performing the general function test of the semiconductor chip mounted on the jig, and the information stored in the general database 301 and the information stored in the EMC database 303 may be together extracted to be transferred to the chip mount unit 201 through the data selection unit 307 at the time of measuring EMC of semiconductor chip.
The measurement database 305 stores a measurement result of the chip mount unit 201. In this case, for more precise measurement, an intermediate result may be stored even when measurement is in progress in the chip mount unit 201. For example, when a measurement range intends to be increased by a method of increasing a clock frequency during the measurement, previous measurement data may be temporarily stored so as to compare measurement results in different ranges after the measurement is completely terminated.
From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
Patent | Priority | Assignee | Title |
10773348, | May 21 2018 | Electronics and Telecommunications Research Institute | Reconfigurable jig device |
Patent | Priority | Assignee | Title |
6400160, | Jun 22 2000 | Advanced Micro Devices, Inc. | Method and apparatus for mutual impedance coupling for component level EMI measurements |
6967486, | May 22 2000 | ENDRESS + HAUSER GMBH + CO KG | Two conductor measuring device, method for testing the same and testing system therefor |
20060043979, | |||
20080084218, | |||
20100207641, | |||
20130082717, | |||
KR1020110065153, | |||
KR1020110098563, |
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