A digital camera includes an image capture assembly; a print media transport assembly; a pagewidth ink jet printhead; a roll of print media; an internal chassis serving as a frame on which the image capture assembly, the print media transport assembly, and the printhead are directly supported; and an external casing completely encasing therewithin the internal chassis. The external casing is openable, and the internal chassis together with the assemblies and printhead supported thereon are removable from the external casing. The internal chassis is provided as an integral frame configured with pre-molded fittings adapted to receive and support the assemblies and printhead.
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1. A digital camera, comprising:
an image capture assembly;
a print media transport assembly;
a pagewidth ink jet printhead;
a roll of print media;
an internal chassis serving as a frame on which the image capture assembly, the print media transport assembly, and the printhead are directly supported; and
an external casing completely encasing therewithin the internal chassis, wherein the external casing is openable, and the internal chassis together with the assemblies and printhead supported thereon are removable from the external casing, and the internal chassis is provided as an integral frame configured with pre-molded fittings adapted to receive and support the assemblies and printhead.
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This is a Continuation of U.S. Ser. No. 11/026,135 filed Jan. 3, 2005, which is a continuation of U.S. Ser. No. 10/729,151 filed on Dec. 8, 2003, now issued U.S. Pat. No. 7,551,201, which is a continuation of Ser. No. 09/112,774 filed on Jul. 10, 1998 (now abandoned), all of which are herein incorporated by reference. With respect to the present application, any disclaimer of claim scope made in the parent application or any predecessor or related application is hereby rescinded. Further, any disclaimer of claim scope that may occur in the present application should not be read back into any predecessor or related application.
The present invention relates substantially to the concept of a disposable camera having instant printing capabilities and in particular, discloses an image capture and processing device for a digital camera system.
Recently, the concept of a “single use” disposable camera has become an increasingly popular consumer item. Disposable camera systems presently on the market normally include an internal film roll and a simplified gearing mechanism for traversing the film roll across an imaging system including a shutter and lensing system. The user, after utilising a single film roll returns the camera system to a film development centre for processing. The film roll is taken out of the camera system and processed and the prints returned to the user. The camera system is then able to be re-manufactured through the insertion of a new film roll into the camera system, the replacement of any worn or wearable parts and the re-packaging of the camera system in accordance with requirements. In this way, the concept of a single use “disposable” camera is provided to the consumer.
Recently, a camera system has been proposed by the present applicant which provides for a handheld camera device having an internal print head, image sensor and processing means such that images sense by the image sensing means, are processed by the processing means and adapted to be instantly printed out by the printing means on demand. The proposed camera system further discloses a system of internal “print rolls” carrying print media such as film on to which images are to be printed in addition to ink to supplying the printing means for the printing process. The print roll is further disclosed to be detachable and replaceable within the camera system.
Unfortunately, such a system is likely to only be constructed at a substantial cost and it would be desirable to provide for a more inexpensive form of instant camera system which maintains a substantial number of the quality aspects of the aforementioned arrangement.
It would be further advantageous to provide for the effective interconnection of the sub components of a camera system.
According to an aspect of the present disclosure, a digital camera includes an image capture assembly; a print media transport assembly; a pagewidth ink jet printhead; a roll of print media; an internal chassis serving as a frame on which the image capture assembly, the print media transport assembly, and the printhead are directly supported; and an external casing completely encasing therewithin the internal chassis. The external casing is openable, and the internal chassis together with the assemblies and printhead supported thereon are removable from the external casing. The internal chassis is provided as an integral frame configured with pre-molded fittings adapted to receive and support the assemblies and printhead.
Notwithstanding any other forms which may fall within the scope of the present invention, preferred forms of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Turning initially to
The camera system 1 provides for a standard number of output prints after which the camera system 1 ceases to function. A prints left indicator slot 10 is provided to indicate the number of remaining prints. A refund scheme at the point of purchase is assumed to be operational for the return of used camera systems for recycling.
Turning now to
As shown in
Turning next to
A dial mechanism 44 is provided for indicating the number of “prints left”. The dial mechanism 44 is snap fitted through a corresponding mating portion 46 so as to be freely rotatable.
As shown in
The ink supply mechanism 40 interacts with a platen unit 60 which guides print media under a printhead located in the ink supply mechanism.
The platen unit 60 includes an internal recapping mechanism 80 for recapping the print head when not in use. The recapping mechanism 80 includes a sponge portion 81 and is operated via a solenoid coil so as to provide for recapping of the print head. In the preferred embodiment, there is provided an inexpensive form of printhead re-capping mechanism provided for incorporation into a handheld camera system so as to provide for printhead re-capping of an inkjet printhead.
A second moveable arm 78 of the solenoid actuator is also provided. The arm 78 is moveable and is also made of ferrous material. Mounted on the arm is a sponge portion surrounded by an elastomer strip 79. The elastomer strip 79 is of a generally arcuate cross-section and act as a leaf spring against the surface of the printhead ink supply cartridge 42 (
When it is desired to operate the printhead unit, upon the insertion of paper, the solenoid coil 75 is activated so as to cause the arm 78 to move down to be adjacent to the end plate 76. The arm 78 is held against end plate 76 while the printhead is printing by means of a small “keeper current” in coil 75. Simulation results indicate that the keeper current can be significantly less than the actuation current. Subsequently, after photo printing, the paper is guillotined by the cutting mechanism 63 of
It can be seen that the preferred embodiment provides for a simple and inexpensive means of re-capping a printhead through the utilisation of a solenoid type device having a long rectangular form. Further, the preferred embodiment utilises minimal power in that currents are only required whilst the device is operational and additionally, only a low keeper current is required whilst the printhead is printing.
Turning next to
Of course, many other inkjet technologies, may also be utilised when constructing a printhead unit 102. The fundamental requirement of the ink supply cartridge 42 is the supply of ink to a series of colour channels etched through the back surface of the printhead 102. In the description of the preferred embodiment, it is assumed that a three colour printing process is to be utilised so as to provide full colour picture output. Hence, the print supply unit includes three ink supply reservoirs being a cyan reservoir 104, a magenta reservoir 105 and a yellow reservoir 106. Each of these reservoirs is required to store ink and includes a corresponding sponge type material 107-109 which assists in stabilising ink within the corresponding ink channel and inhibiting the ink from sloshing back and forth when the printhead is utilised in a handheld camera system. The reservoirs 104, 105, 106 are formed through the mating of first exterior plastic piece 110 and a second base piece 111.
At a first end 118 of the base piece 111 a series of air inlet 113-115 are provided. Each air inlet leads to a corresponding winding channel which is hydrophobically treated so as to act as an ink repellent and therefore repel any ink that may flow along the air inlet channel. The air inlet channel further takes a convoluted path assisting in resisting any ink flow out of the chambers 104-106. An adhesive tape portion 117 is provided for sealing the channels within end portion 118.
At the top end, there is included a series of refill holes (not shown) for refilling corresponding ink supply chambers 104, 105, 106. A plug 121 is provided for sealing the refill holes.
Turning now to
The ink supply cartridge 42 includes two guide walls 124, 125 which separate the various ink chambers and are tapered into an end portion abutting the surface of the printhead 102. The guide walls 124, 125 are further mechanically supported by block portions eg. 126 which are placed at regular intervals along the length of the ink supply unit. The block portions 126 leave space at portions close to the back of printhead 102 for the flow of ink around the back surface thereof.
The ink supply unit is preferably formed from a multi-part plastic injection mould and the mould pieces eg. 110, 111 (
Turning now to
The Image Capture and Processing integrated circuit 48 provides most of the electronic functionality of the camera with the exception of the print head integrated circuit. The integrated circuit 48 is a highly integrated system. It combines CMOS image sensing, analog to digital conversion, digital image processing, DRAM storage, ROM, and miscellaneous control functions in a single integrated circuit.
The integrated circuit is estimated to be around 32 mm2 using a leading edge 0.18 micron CMOS/DRAM/APS process. The integrated circuit size and cost can scale somewhat with Moore's law, but is dominated by a CMOS active pixel sensor array 201, so scaling is limited as the sensor pixels approach the diffraction limit.
The ICP 48 includes CMOS logic, a CMOS image sensor, DRAM, and analog circuitry. A very small amount of flash memory or other non-volatile memory is also preferably included for protection against reverse engineering.
Alternatively, the ICP can readily be divided into two integrated circuits: one for the CMOS imaging array, and the other for the remaining circuitry. The cost of this two integrated circuit solution should not be significantly different than the single integrated circuit ICP, as the extra cost of packaging and bond-pad area is somewhat cancelled by the reduced total wafer area requiring the color filter fabrication steps.
The ICP preferably contains the following functions:
Function
1.5 megapixel image sensor
Analog Signal Processors
Image sensor column decoders
Image sensor row decoders
Analogue to Digital Conversion (ADC)
Column ADC's
Auto exposure
12 Mbits of DRAM
DRAM Address Generator
Color interpolator
Convolver
Color ALU
Halftone matrix ROM
Digital halftoning
Print head interface
8 bit CPU core
Program ROM
Flash memory
Scratchpad SRAM
Parallel interface (8 bit)
Motor drive transistors (5)
Clock PLL
JTAG test interface
Test circuits
Busses
Bond pads
The CPU, DRAM, Image sensor, ROM, Flash memory, Parallel interface, JTAG interface and ADC can be vendor supplied cores. The ICP is intended to run on 1.5V to minimize power consumption and allow convenient operation from two M type battery cells.
The latest advances in the field of image sensing and CMOS image sensing in particular can be found in the October, 1997 issue of IEEE Transactions on Electron Devices and, in particular, pages 1689 to 1968. Further, a specific implementation similar to that disclosed in the present application is disclosed in Wong et. al, “CMOS Active Pixel Image Sensors Fabricated Using a 1.8V, 0.25 μm CMOS Technology”, IEDM 1996, page 915
The imaging array uses a 4 transistor active pixel design of a standard configuration. To minimize integrated circuit area and therefore cost, the image sensor pixels should be as small as feasible with the technology available. With a four transistor cell, the typical pixel size scales as 20 times the lithographic feature size. This allows a minimum pixel area of around 3.6 μm×3.6 μm. However, the photosite must be substantially above the diffraction limit of the lens. It is also advantageous to have a square photosite, to maximize the margin over the diffraction limit in both horizontal and vertical directions. In this case, the photosite can be specified as 2.5 μm×2.5 μm. The photosite can be a photogate, pinned photodiode, charge modulation device, or other sensor.
The four transistors are packed as an ‘L’ shape, rather than a rectangular region, to allow both the pixel and the photosite to be square. This reduces the transistor packing density slightly, increasing pixel size. However, the advantage in avoiding the diffraction limit is greater than the small decrease in packing density.
The transistors also have a gate length which is longer than the minimum for the process technology. These have been increased from a drawn length of 0.18 micron to a drawn length of 0.36 micron. This is to improve the transistor matching by making the variations in gate length represent a smaller proportion of the total gate length.
The extra gate length, and the ‘L’ shaped packing, mean that the transistors use more area than the minimum for the technology. Normally, around 8 μm2 would be required for rectangular packing. Preferably, 9.75 μm2 has been allowed for the transistors.
The total area for each pixel is 16 μm2, resulting from a pixel size of 4 μm×4 μm. With a resolution of 1,500×1,000, the area of the imaging array 101 is 6,000 μm×4,000 μm, or 24 mm2.
The presence of a color image sensor on the integrated circuit affects the process required in two major ways:
Color filters are required. These can be fabricated using dyed photosensitive polyimides, resulting in an added process complexity of three spin coatings, three photolithographic steps, three development steps, and three hardbakes.
There are 15,000 analog signal processors (ASPs) 205, one for each of the columns of the sensor. The ASPs amplify the signal, provide a dark current reference, sample and hold the signal, and suppress the fixed pattern noise (FPN).
There are 375 analog to digital converters 206, one for each four columns of the sensor array. These may be delta-sigma or successive approximation type ADC's. A row of low column ADC's are used to reduce the conversion speed required, and the amount of analog signal degradation incurred before the signal is converted to digital. This also eliminates the hot spot (affecting local dark current) and the substrate coupled noise that would occur if a single high speed ADC was used. Each ADC also has two four bit DAC's which trim the offset and scale of the ADC to further reduce FPN variations between columns. These DAC's are controlled by data stored in flash memory during integrated circuit testing.
The column select logic 204 is a 1:1500 decoder which enables the appropriate digital output of the ADCs onto the output bus. As each ADC is shared by four columns, the least significant two bits of the row select control 4 input analog multiplexors.
A row decoder 207 is a 1:1000 decoder which enables the appropriate row of the active pixel sensor array. This selects which of the 1000 rows of the imaging array is connected to analog signal processors. As the rows are always accessed in sequence, the row select logic can be implemented as a shift register.
An auto exposure system 208 adjusts the reference voltage of the ADC 205 in response to the maximum intensity sensed during the previous frame period. Data from the green pixels is passed through a digital peak detector. The peak value of the image frame period before capture (the reference frame) is provided to a digital to analogue converter (DAC), which generates the global reference voltage for the column ADCs. The peak detector is reset at the beginning of the reference frame. The minimum and maximum values of the three RGB color components are also collected for color correction.
The second largest section of the integrated circuit is consumed by a DRAM 210 used to hold the image. To store the 1,500×1,000 image from the sensor without compression, 1.5 Mbytes of DRAM 210 are required. This equals 12 Mbits, or slightly less than 5% of a 256 Mbit DRAM. The DRAM technology assumed is of the 256 Mbit generation implemented using 0.18 μm CMOS.
Using a standard 8F cell, the area taken by the memory array is 3.11 mm2. When row decoders, column sensors, redundancy, and other factors are taken into account, the DRAM requires around 4 mm2.
This DRAM 210 can be mostly eliminated if analog storage of the image signal can be accurately maintained in the CMOS imaging array for the two seconds required to print the photo. However, digital storage of the image is preferable as it is maintained without degradation, is insensitive to noise, and allows copies of the photo to be printed considerably later.
A DRAM address generator 211 provides the write and read addresses to the DRAM 210. Under normal operation, the write address is determined by the order of the data read from the CMOS image sensor 201. This will typically be a simple raster format. However, the data can be read from the sensor 201 in any order, if matching write addresses to the DRAM are generated. The read order from the DRAM 210 will normally simply match the requirements of a color interpolator and the print head. As the cyan, magenta, and yellow rows of the print head are necessarily offset by a few pixels to allow space for nozzle actuators, the colors are not read from the DRAM simultaneously. However, there is plenty of time to read all of the data from the DRAM many times during the printing process. This capability is used to eliminate the need for FIFOs in the print head interface, thereby saving integrated circuit area. All three RGB image components can be read from the DRAM each time color data is required. This allows a color space converter to provide a more sophisticated conversion than a simple linear RGB to CMY conversion.
Also, to allow two dimensional filtering of the image data without requiring line buffers, data is re-read from the DRAM array.
The address generator may also implement image effects in certain models of camera. For example, passport photos are generated by a manipulation of the read addresses to the DRAM. Also, image framing effects (where the central image is reduced), image warps, and kaleidoscopic effects can all be generated by manipulating the read addresses of the DRAM.
While the address generator 211 may be implemented with substantial complexity if effects are built into the standard integrated circuit, the integrated circuit area required for the address generator is small, as it consists only of address counters and a moderate amount of random logic.
A color interpolator 214 converts the interleaved pattern of red, 2×green, and blue pixels into RGB pixels. It consists of three 8 bit adders and associated registers. The divisions are by either 2 (for green) or 4 (for red and blue) so they can be implemented as fixed shifts in the output connections of the adders.
A convolver 215 is provided as a sharpening filter which applies a small convolution kernel (5×5) to the red, green, and blue planes of the image. The convolution kernel for the green plane is different from that of the red and blue planes, as green has twice as many samples. The sharpening filter has five functions:
These functions are all combined into a single convolution matrix. As the pixel rate is low (less than 1 Mpixel per second) the total number of multiplies required for the three color channels is 56 million multiplies per second. This can be provided by a single multiplier. Fifty bytes of coefficient ROM are also required.
A color ALU 113 combines the functions of color compensation and color space conversion into the one matrix multiplication, which is applied to every pixel of the frame. As with sharpening, the color correction should match the most popular settings, rather than the most accurate.
A color compensation circuit of the color ALU provides compensation for the lighting of the photo. The vast majority of photographs are substantially improved by a simple color compensation, which independently normalizes the contrast and brightness of the three color components.
A color look-up table (CLUT) 212 is provided for each color component. These are three separate 256×8 SRAMs, requiring a total of 6,144 bits. The CLUTs are used as part of the color correction process. They are also used for color special effects, such as stochastically selected “wild color” effects.
A color space conversion system of the color ALU converts from the RGB color space of the image sensor to the CMY color space of the printer. The simplest conversion is a 1's complement of the RGB data. However, this simple conversion assumes perfect linearity of both color spaces, and perfect dye spectra for both the color filters of the image sensor, and the ink dyes. At the other extreme is a tri-linear interpolation of a sampled three dimensional arbitrary transform table. This can effectively match any non-linearity or differences in either color space. Such a system is usually necessary to obtain good color space conversion when the print engine is a color electrophotographic
However, since the non-linearity of a halftoned ink jet output is very small, a simpler system can be used. A simple matrix multiply can provide excellent results. This requires nine multiplies and six additions per contone pixel. However, since the contone pixel rate is low (less than 1 Mpixel/sec) these operations can share a single multiplier and adder. The multiplier and adder are used in a color ALU which is shared with the color compensation function.
Digital halftoning can be performed as a dispersed dot ordered dither using a stochastic optimized dither cell. A halftone matrix ROM 216 is provided for storing dither cell coefficients. A dither cell size of 32×32 is adequate to ensure that the cell repeat cycle is not visible. The three colors—cyan, magenta, and yellow—are all dithered using the same cell, to ensure maximum co-positioning of the ink dots. This minimizes ‘muddying’ of the mid-tones which results from bleed of dyes from one dot to adjacent dots while still wet. The total ROM size required is 1 KByte, as the one ROM is shared by the halftoning units for each of the three colors.
The digital halftoning used is dispersed dot ordered dither with stochastic optimized dither matrix. While dithering does not produce an image quite as ‘sharp’ as error diffusion, it does produce a more accurate image with fewer artifacts. The image sharpening produced by error diffusion is artificial, and less controllable and accurate than ‘unsharp mask’ filtering performed in the contone domain. The high print resolution (1,600 dpi×1,600 dpi) results in excellent quality when using a well formed stochastic dither matrix.
Digital halftoning is performed by a digital halftoning unit 217 using a simple comparison between the contone information from the DRAM 210 and the contents of the dither matrix 216. During the halftone process, the resolution of the image is changed from the 250 dpi of the captured contone image to the 1,600 dpi of the printed image. Each contone pixel is converted to an average of 40.96 halftone dots.
The ICP incorporates a 16 bit microcontroller CPU core 219 to run the miscellaneous camera functions, such as reading the buttons, controlling the motor and solenoids, setting up the hardware, and authenticating the refill station. The processing power required by the CPU is very modest, and a wide variety of processor cores can be used. As the entire CPU program is run from a small ROM 220[.], program compatibility between camera versions is not important, as no external programs are run. A 2 Mbit (256 Kbyte) program and data ROM 220 is included on integrated circuit. Most of this ROM space is allocated to data for outline graphics and fonts for specialty cameras. The program requirements are minor. The single most complex task is the encrypted authentication of the refill station. The ROM requires a single transistor per bit.
A Flash memory 221 may be used to store a 128 bit authentication code. This provides higher security than storage of the authentication code in ROM, as reverse engineering can be made essentially impossible. The Flash memory is completely covered by third level metal, making the data impossible to extract using scanning probe microscopes or electron beams. The authentication code is stored in the integrated circuit when manufactured. At least two other Flash bits are required for the authentication process: a bit which locks out reprogramming of the authentication code, and a bit which indicates that the camera has been refilled by an authenticated refill station. The flash memory can also be used to store FPN correction data for the imaging array. Additionally, a phase locked loop rescaling parameter is stored for scaling the clocking cycle to an appropriate correct time. The clock frequency does not require crystal accuracy since no date functions are provided. To eliminate the cost of a crystal, an on integrated circuit oscillator with a phase locked loop 224 is used. As the frequency of an on-integrated circuit oscillator is highly variable from integrated circuit to integrated circuit, the frequency ratio of the oscillator to the PLL is digitally trimmed during initial testing. The value is stored in Flash memory 221. This allows the clock PLL to control the ink-jet heater pulse width with sufficient accuracy.
A scratchpad SRAM is a small static RAM 222 with a 6T cell. The scratchpad provided temporary memory for the 16 bit CPU. 1024 bytes is adequate.
A print head interface 223 formats the data correctly for the print head. The print head interface also provides all of the timing signals required by the print head. These timing signals may vary depending upon temperature, the number of dots printed simultaneously, the print medium in the print roll, and the dye density of the ink in the print roll.
The print head utilized is composed of eight identical segments, each 1.25 cm long. There is no connection between the segments on the print head integrated circuit. Any connections required are made in the external TAB bonding film, which is double sided. The division into eight identical segments is to simplify lithography using wafer steppers. The segment width of 1.25 cm fits easily into a stepper field. As the print head integrated circuit is long and narrow (10 cm×0.3 mm), the stepper field contains a single segment of 32 print head integrated circuits. The stepper field is therefore 1.25 cm×1.6 cm. An average of four complete print heads are patterned in each wafer step.
A single BitClock output line connects to all 8 segments on the print head. The 8 DataBits lines lead one to each segment, and are clocked into the 8 segments on the print head simultaneously (on a BitClock pulse). For example, dot 0 is transferred to segment0, dot 750 is transferred to segment1, dot 1500 to segment2 etc simultaneously.
The ParallelXferClock is connected to each of the 8 segments on the print head, so that on a single pulse, all segments transfer their bits at the same time.
The NozzleSelect, BankEnable and ColorEnable lines are connected to each of the 8 segments, allowing the print head interface to independently control the duration of the cyan, magenta, and yellow nozzle energizing pulses. Registers in the Print Head Interface allow the accurate specification of the pulse duration between 0 and 6 ms, with a typical duration of 2 ms to 3 ms.
A parallel interface 125 connects the ICP to individual static electrical signals. The CPU is able to control each of these connections as memory mapped I/O via a low speed bus.
Seven high current drive transistors eg. 227 are required. Four are for the four phases of the main stepper motor, two are for the guillotine motor, and the remaining transistor is to drive the capping solenoid. These transistors are allocated 20,000 square microns (600,000 F) each. As the transistors are driving highly inductive loads, they must either be turned off slowly, or be provided with a high level of back EMF protection. If adequate back EMF protection cannot be provided using the integrated circuit process chosen, then external discrete transistors should be used. The transistors are never driven at the same time as the image sensor is used. This is to avoid voltage fluctuations and hot spots affecting the image quality. Further, the transistors are located as far away from the sensor as possible.
A standard JTAG (Joint Test Action Group) interface 228 is included in the ICP for testing purposes and for interrogation by the refill station. Due to the complexity of the integrated circuit, a variety of testing techniques are required, including BIST (Built In Self Test) and functional block isolation. An overhead of 10% in integrated circuit area is assumed for integrated circuit testing circuitry for the random logic portions. The overhead for the large arrays the image sensor and the DRAM is smaller.
The JTAG interface is also used for authentication of the refill station. This is included to ensure that the cameras are only refilled with quality paper and ink at a properly constructed refill station, thus preventing inferior quality refills from occurring. The camera must authenticate the refill station, rather than vice versa. The secure protocol is communicated to the refill station during the automated test procedure. Contact is made to four gold plated spots on the ICP/print head TAB by the refill station as the new ink is injected into the print head.
Turning now to
The solenoid coil is interconnected (not shown) to interconnects 97, 98 (
Turning now to
Next, as illustrated in
Turning now to
An optical element 31 is provided for snapping into a top portion of the chassis 12. The optical element 31 includes portions defining an optical view finder 32, 33 which are slotted into mating portions 35, 36 in view finder channel 37. Also provided in the optical element 31 is a lensing system 38 for magnification of the prints left number in addition to an optical pipe element 39 for piping light from the LED 5 for external display.
Turning next to
Turning now to
Subsequently, the preferred embodiment is ready for use as a one time use camera system that provides for instant output images on demand. It will be evident that the preferred embodiment further provides for a refillable camera system. A used camera can be collected and its outer plastic cases removed and recycled. A new paper roll and batteries can be added and the ink cartridge refilled. A series of automatic test routines can then be carried out to ensure that the printer is properly operational. Further, in order to ensure only authorised refills are conducted so as to enhance quality, routines in the on-integrated circuit program ROM can be executed such that the camera authenticates the refilling station using a secure protocol. Upon authentication, the camera can reset an internal paper count and an external case can be fitted on the camera system with a new outer label. Subsequent packing and shipping can then take place.
It will be further readily evident to those skilled in the art that the program ROM can be modified so as to allow for a variety of digital processing routines. In addition to the digitally enhanced photographs optimised for mainstream consumer preferences, various other models can readily be provided through mere reprogramming of the program ROM. For example, a sepia classic old fashion style output can be provided through a remapping of the colour mapping function. A further alternative is to provide for black and white outputs again through a suitable colour remapping algorithm. Minimum colour can also be provided to add a touch of colour to black and white prints to produce the effect that was traditionally used to colourize black and white photos. Further, passport photo output can be provided through suitable address remappings within the address generators. Further, edge filters can be utilised as is known in the field of image processing to produce sketched art styles. Further, classic wedding borders and designs can be placed around an output image in addition to the provision of relevant clip arts. For example, a wedding style camera might be provided. Further, a panoramic mode can be provided so as to output the well known panoramic format of images. Further, a postcard style output can be provided through the printing of postcards including postage on the back of a print roll surface. Further, cliparts can be provided for special events such as Halloween, Christmas etc. Further, kaleidoscopic effects can be provided through address remappings and wild colour effects can be provided through remapping of the colour lookup table. Many other forms of special event cameras can be provided for example, cameras dedicated to the Olympics, movie tie-ins, advertising and other special events.
The operational mode of the camera can be programmed so that upon the depressing of the take photo a first image is sampled by the sensor array to determine irrelevant parameters. Next a second image is again captured which is utilised for the output. The captured image is then manipulated in accordance with any special requirements before being initially output on the paper roll. The LED light is then activated for a predetermined time during which the DRAM is refreshed so as to retain the image. If the print copy button is depressed during this predetermined time interval, a further copy of the photo is output. After the predetermined time interval where no use of the camera has occurred, the onboard CPU shuts down all power to the camera system until such time as the take button is again activated. In this way, substantial power savings can be realized.
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