A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first area and a second area divided by a shallow trench isolation (STI) area, a first dummy structure on the STI area, a second dummy structure located on the STI area, a first semiconductor structure on the first area, and a second semiconductor structure on the second area of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a high-k dielectric first, high-k metal gate last procedure.
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12. A semiconductor device comprising:
a substrate having a first area and a second area divided by a shallow trench isolation (STI) area;
a first dummy structure on the STI area at the side of the first area of the substrate, comprising a first dummy gate stack;
a second dummy structure located on the STI area at the side of the second area of the substrate, comprising a second dummy gate stack with a high-k dielectric layer, a first spacer next to the second dummy gate stack, and a third dummy gate structure with a trench stack next to the first spacer;
a memory device on the first area of the substrate; and
a logic device on the second area of the substrate.
1. A semiconductor device comprising:
a substrate having a first area and a second area divided by a shallow trench isolation (STI) area;
a first dummy structure on the STI area at the side of the first area of the substrate, comprising a first dummy gate stack;
a second dummy structure on the STI area at the side of the second area of the substrate, comprising a second dummy gate stack with a high-k dielectric layer, a first spacer next to the second dummy gate stack, and a third dummy gate stack with a trench stack next to the first spacer;
a first semiconductor structure on the first area of the substrate, comprising a first gate structure with a second intermediate layer and a second conductive layer over the second intermediate layer; and
a second semiconductor structure on the second area of the substrate, comprising a high-k dielectric layer and a metal gate layer over the high-k dielectric layer.
2. The device of
a storage structure next to the third dummy gate stack; and
a third spacer next to the second dummy gate stack.
3. The device of
a storage layer having a L-shape over the substrate;
a third conductive layer having the L-shape over the storage layer; and
a third protective layer over the third conductive layer.
4. The device of
a second intermediate layer over the substrate;
a second conductive layer over the second intermediate layer, comprising a trench on a upper surface of the second conductive layer; and
the trench stack filling the trench of the second conductive layer to flat the upper surface of the second conductive layer.
5. The device of
a storage structure next to the first dummy gate stack;
a second dielectric layer next to the other side of first dummy gate stack; and
a third spacer next to the second dielectric layer.
6. The device of
a storage layer having a L-shape over the substrate;
a third conductive layer having the L-shape over the storage layer; and
a third protective layer over the third conductive layer.
8. The device of
9. The device of
10. The device of
11. The device of
a first intermediate layer over the substrate; and
an etch stop layer over the first intermediate layer, wherein the high-k dielectric layer is interposed between the first intermediate layer and the etch stop layer.
13. The device of
15. The device of
a storage structure next to the third dummy gate stack; and
a third spacer next to the second dummy gate stack.
16. The device of
a second intermediate layer over the substrate;
a second conductive layer over the second intermediate layer, comprising a trench on a upper surface of the second conductive layer; and
the trench stack filling the trench of the second conductive layer to flat the upper surface of the second conductive layer.
18. The device of
19. The device of
20. The device of
a storage structure next to the first dummy gate stack;
a second dielectric layer next to the other side of first dummy gate stack; and
a third spacer next to the second dielectric layer.
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Semiconductor devices with various functions may be embedded in the same integrated circuit (IC). The semiconductor devices for example include non-volatile memory (NVM), complementary metal oxide semiconductor (CMOS), and capacitor. The fabricating processes for the different semiconductor devices need to be designed and integrated. Upon the integration, the fabricating processes are able to have the different devices all together such as memory device like dynamic random access memory (DRAM), static random access memory (SRAM), magnetic RAM, or non-volatile memory, and logic circuit like p-type metal oxide semiconductor (PMOS), n-type metal oxide semiconductor (NMOS), and COMS. The semiconductor devices with different material also need to be considered in the integration of the fabricating process.
Flash NVM is commonly embedded in a system on chip (SOC) integrated circuits having CMOS logic circuit. The integration of the split-gate thin film flash memory with polysilicon gate electrode and the COMS logic circuit having high-k dielectric and metal gate on the same integrated circuit may require many additional process steps. The traditional integration process having memory device without high-k dielectric and logic device with high-k metal gate (HKMG) structure starts from forming the memory device, than depositing high-k dielectric and forming the logic device. Such process may have high-k dielectric residue, and thus requires additional masks to solve the problem which however results in contamination problems.
Embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity.
As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
The singular forms “a,” “an” and “the” used herein include plural referents unless the context clearly dictates otherwise. Therefore, reference to, for example, a dielectric layer includes embodiments having two or more such dielectric layers, unless the context clearly indicates otherwise. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are intended for illustration.
In various embodiments of the present disclosure, the first semiconductor structure 1560 is a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic RAM, a non-volatile memory, or combinations thereof, and the second semiconductor structure 1620 is a logic device such as a p-type metal oxide semiconductor (PMOS), a n-type metal oxide semiconductor (NMOS), a complementary metal-oxide-semiconductor (COMS), or combinations thereof. In various embodiments of the present disclosure, the first semiconductor structure 1560 includes a second intermediate layer 910 and a second conductive layer 920 over the second intermediate layer 910, the second conductive layer 920 includes polysilicon, and the second semiconductor structure 1620 includes the high-k dielectric layer 320 and a metal gate layer 1610 over the high-k dielectric layer 320. In various embodiments of the present disclosure, the first semiconductor structure 1560 is a thin film split-gate flash memory, and the second semiconductor structure 1620 is a COMS includes high-k metal gate (HKMG) structure.
The first dummy structure 1570 and the second dummy structure 1580 are residual structures during the high-k dielectric layer first, HKMG device last process in an embedded system as a dummy guard ring to separate and protect the first and second semiconductor structures 1560,1620 in different area, respectively. The corresponding elements of such as the first dummy structure 1570 and the second dummy structure 1580 are referred to
In various embodiments of the present disclosure, the second dummy structure 1580 includes a second dummy gate stack 1540 with a high-k dielectric layer 320 and a first spacer 500 next to the second dummy gate stack, a third dummy gate stack 1522 next to the first spacer 500, a storage structure next to the third dummy gate stack 1522, and a third spacer next to the second dummy gate stack. The second dummy gate stack 1540 includes a first intermediate layer over the substrate 200, a high-k dielectric layer 320 over the first intermediate layer, an etch stop layer over the high-k dielectric layer 320, and a first conductive layer over the etch stop layer. The third dummy gate stack 1522 includes a second intermediate layer overlying the substrate 200, a second conductive layer over the a second intermediate layer, comprising a trench on a upper surface of the second conductive layer, and a trench stack 1524 filling the trench of the second conductive layer to flat the upper surface of the second conductive layer. The width of the dummy structures is about 0.2-0.6 μm.
In various embodiments of the present disclosure, the first semiconductor structure 1560 includes a first gate structure 1510, a storage structure next to the first gate structure 1510, and a second dielectric layer on the sidewall at the other side of the first gate structure 1510, two third spacers next to the storage structure and the second dielectric layer separately. The first gate structure 1510 includes a second intermediate layer 910 over the substrate 200, and a second conductive layer 920 over the second intermediate layer 910.
In various embodiments of the present disclosure, the second semiconductor structure 1620 includes a first intermediate layer over the substrate 200, a high-k dielectric layer 320 over the first intermediate layer, an etch stop layer over the high-k dielectric layer 320, a metal gate layer 1610 over the etch stop layer, and two third spacers on the substrate 200 next to the metal gate layer 1610.
In various embodiments of the present disclosure, the first and second semiconductor structures 1560,1620 further include doped regions 1410 including lightly and heavily doped region as source/drain region. In various embodiments of the present disclosure, the semiconductor device further includes a first interlayer dielectric layer 1590 on the substrate 200 and between the first and second semiconductor structures 1560,1620 and the first and second dummy structures 1570,1580, a second interlayer dielectric layer 1630 overlying the first interlayer dielectric layer 1590, the first and second semiconductor structures 1560,1620 and the first and second dummy structures 1570,1580, a metal layer 1640 overlying the second dielectric layer 1630, a plurality of contacts 1650 connecting the doped regions 1410 and the metal layer 1640.
In
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The first dummy structure 1570 includes a first dummy gate stack 1520, a second dielectric layer 1110 at one side of the first dummy gate stack 1520, a storage structure 1550 at the other side of the first dummy gate stack 1520, and a third spacer 1310 next to the second dielectric layer. The first dummy gate stack 1520 includes a second intermediate layer 910 and a second conductive layer 920 over the second intermediate layer 910. The storage structure 1550 is the storage stacks 1120 after planarization.
The second dummy structure 1580 includes a second dummy gate stack 1540 with a high-k dielectric layer 320 and a first spacer 500 next to the second dummy gate stack 1540, a third dummy gate stack 1522 next to the first spacer 500, a storage structure 1550 next to the third dummy gate stack 1522, and a third spacer 1310 next to the second dummy gate stack 1540. The second dummy gate stack 1540 is the fourth gate stack 1220 after planarization, includes a first intermediate layer 310 over the substrate 200, a high-k dielectric layer 320 over the first intermediate layer 310, an etch stop layer 330 over the high-k dielectric layer 320, and a first conductive layer 340 over the etch stop layer 330. The third dummy gate stack 1522 is the residue gate stack 740 after planarization, includes the second intermediate layer 710 overlying the substrate 200, the second conductive layer 720 over the a second intermediate layer 710, comprising the trench 750 on a upper surface of the second conductive layer 720, and a trench stack 1524 filling the trench 750 of the second conductive layer 720 to flat the upper surface of the second conductive layer 720. The trench stack 1524 is the first storage stack 940 left in the trench 750 after planarization, may include the storage layer 910, third conductive layer 920 over the storage layer 910, and the second residue layer 1020 over the third conductive layer 920. The width of the dummy structures 1570,1580 is about 0.2-0.6 μm.
The first semiconductor structure 1560 includes a first gate structure 1510, a storage structure 1550 next to the first gate structure 1510, and a second dielectric layer 1110 on the sidewall at the other side of the first gate structure 1510, two third spacers 1310 next to the storage structure 1550 and the second dielectric layer 1110 separately. The first gate structure 1510 includes the second intermediate layer 610 over the substrate 200, and the second conductive layer 620 over the second intermediate layer 610.
The second gate structure 1530 is the second gate stack 1230 after planarization, includes the first intermediate layer 310 over the substrate 200, the high-k dielectric layer 320 over the first intermediate layer 310, the etch stop layer 330 over the high-k dielectric layer 320, and the first conductive layer 340 over the etch stop layer 330.
Referring to
After the formation of the second semiconductor structure 1620, a second interlayer dielectric layer 1630 is disposed over the semiconductor device 100, a plurality of contacts 1640 are formed through the interlayer dielectric layers 1630, 1590, and a metal layer 1650 is disposed over the second interlayer dielectric layer 1640. The second interlayer dielectric layer 1630 includes silicon oxide or borophosphosilicate glass (BPSG) and formed by deposition method as LPCVD, PECVD or other suitable methods. The contacts 1640 connect the doped regions 1410 to the metal layer 1650, formed by etching the interlayer dielectric layers 1640,1590 and depositing a contact material like tungsten or cobalt. The metal layer 1650 includes aluminium, tungsten or other suitable material, and is formed by deposition process as LPCVD or PECVD or other suitable methods.
Thus, according to various embodiments of the present disclosure and referring to
In which depositing a high-k stack and a first dielectric layer over the substrate includes depositing a first intermediate layer over the substrate; depositing a high-k dielectric layer over the first intermediate layer; depositing an etch stop layer over the high-k dielectric layer; depositing a first conductive layer over the etch stop layer; depositing a first protective layer over the first conductive layer; and depositing a first dielectric layer over the first protective layer. Depositing a conductive gate stack over the substrate and the high-k stack includes depositing a second conductive layer over the second intermediate layer and the first dielectric layer; and depositing a second protective layer over the second conductive layer.
In various embodiments of the present disclosure, a method of forming a first semiconductor structure on the first region includes forming a first gate stack on the first active region and a third gate stack on the dummy region; depositing a first storage stack over the gate stacks, the high-k stack, the first spacer, and the substrate; etching part of the first storage stack to form a plurality second spacers next to the stacks; and etching part of the first storage stack to form a plurality of second storage stacks.
In various embodiments of the present disclosure, a method of forming a second semiconductor structure on the second region includes etching the high-k stacks to form a second gate stack on the second active region on the substrate and a fourth gate stack on the dummy region next to the second active region; forming a plurality of third spacers next to the gate stacks and the storage stacks on the substrate; forming a plurality of doped regions between the third spacers on the first active region and second active region of the substrate; depositing a first interlayer dielectric layer over the substrate; planarizing the semiconductor device to expose the conductive layers in gate stacks; forming a high-k metal gate structure by replacing the first conductive layer to a metal gate layer in the second gate structure; depositing a second interlayer dielectric layer over the semiconductor device; forming a plurality of contacts to the doped regions; and depositing a metal layer over the second interlayer dielectric layer.
Referring to
The present disclosure includes a semiconductor device and a method of fabricating the semiconductor device. In various embodiments of the present disclosure, the fabricating method is a high-k material first, HKMG device last process. Because the method is a high-k material first process, it can cost down 2 masks of memory process during the fabrication, and has no contamination problem made by the 2 masks. In order to make the high-k to material first, HKMG device last process available, the first spacer is added to protect the first formed high-k stack and to separate the HKMG device and the memory device. Therefore, the semiconductor device fabricating by the method will have two dummy structures, the first dummy structure includes a dummy gate stack including a doped polysilicon conductive layer, and the second dummy structure includes the first spacer and an another doped polysilicon conductive layer. The method can form embedded split gate SiON-MONOS memory structure in HKMG technology for system on chip application.
In various embodiments of the present disclosure, a semiconductor device includes a substrate, a first dummy structure, a second dummy structure, a first semiconductor structure, and a second semiconductor structure. The substrate has a first area and a second area divided by a shallow trench isolation (STI) area. The first dummy structure on the STI area at the side of the first area of the substrate includes a first dummy gate stack. The second dummy structure on the STI area at the side of the second area of the substrate includes a second dummy gate stack with a high-k dielectric layer and a first spacer next to the second dummy gate stack. The first semiconductor structure on the first area of the substrate includes a first gate structure with a second intermediate layer and a second conductive layer over the second intermediate layer. Further, the second semiconductor structure on the second area of the substrate includes a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. In one embodiment of the present disclosure, the semiconductor device can make spilt gate memory embed in HKMG technology.
In various embodiments of the present disclosure, the first and second dummy structure separate the first and second semiconductor structure, the semiconductor structures can be chosen by materials, in which the first semiconductor structure includes non high-k material and poly silicon gate, the second semiconductor structure includes high-k material and metal gate structure, so the first and second semiconductor structures can include memory devices, logic device, lens, sensors, amplifiers, oscillators, light emitting diode or combinations thereof. Or the semiconductor devices can be chosen by functions as the first semiconductor structure is a memory device and the second semiconductor structure is logic device. Therefore, the first semiconductor structure is a memory device can be a DRAM, SRAM, magnetic RAM, NVM, flash memory, thin film split gate flash memory, or combinations thereof, and the second semiconductor structure is a logic device includes pFET, nFET, MOSFET, BJT, PMOS, NMOS, COMS, or combinations thereof.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
Wu, Wei-Cheng, Chuang, Harry Hak-Lay
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