A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip.
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1. A semiconductor package comprising:
a first semiconductor chip including a target circuit surface, a rear surface, and a side surface;
a first sealing insulating layer including a first surface positioned toward the target circuit surface, a second surface positioned on a side opposite to the first surface, and a first via hole penetrating the first sealing insulating layer from the first surface to the second surface, wherein the first sealing insulating layer is a single layer that seals the target circuit surface and the side surface of the first semiconductor chip;
at least one wiring layer formed on the first surface of the first sealing insulating layer;
at least one insulating layer formed on the at least one wiring layer and filling the first via hole;
a second semiconductor chip mounted on the at least one insulating layer;
a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip; and
an electrode pad exposed from the second surface of the first sealing insulating layer;
wherein the first sealing insulating layer and the at least one insulating layer are formed of the same material,
wherein the rear surface of the first semiconductor chip is exposed from the second surface of the first sealing insulating layer,
wherein the first via hole includes a sidewall on which a wiring is formed,
wherein the at least one wiring layer includes a first penetration wiring being formed in the first via hole and penetrating the first sealing insulating layer to electrically connect the at least one wiring layer and the electrode pad by way of the wiring formed on the sidewall of the first via hole,
wherein the rear surface of the first semiconductor chip is positioned on a side opposite to the target circuit surface,
wherein the electrode pad has an exposed surface that is exposed from the second surface of the first sealing insulating layer,
wherein the entire rear surface and the exposed surface are flush with the second surface of the first sealing insulating layer,
wherein a second penetration wiring being formed in a second via hole to electrically connect the at least one wiring layer and the first semiconductor chip by way of a filled-via,
wherein the first and second penetration wirings each has a truncated-cone shape,
wherein the second penetration wiring directly connects the at least one wiring layer and the first semiconductor chip,
wherein the second via hole is completely filled by the second penetration wiring.
3. A semiconductor package comprising:
a first semiconductor chip including a target circuit surface, a rear surface, and a side surface;
a first sealing insulating layer including a first surface positioned toward the target circuit surface, a second surface positioned on a side opposite to the first surface, and a first via hole penetrating the first sealing insulating layer from the first surface to the second surface, wherein the first sealing insulating layer is a single layer that seals the target circuit surface and the side surface of the first semiconductor chip;
at least one wiring layer formed on the first surface of the first sealing insulating layer;
at least one insulating layer formed on the at least one wiring layer and filling the first via hole;
an inorganic member having a planar shape and mounted on the at least one insulating layer;
a second sealing insulating layer formed on the at least one insulating layer and configured to seal the inorganic member; and
an electrode pad exposed from the second surface of the first sealing insulating layer;
wherein the first sealing insulating layer and the at least one insulating layer are formed of the same material,
wherein the rear surface of the first semiconductor chip is exposed from the second surface of the first sealing insulating layer,
wherein the first via hole includes a sidewall on which a wiring is formed,
wherein the at least one wiring layer includes a first penetration wiring being formed in the first via hole and penetrating the first sealing insulating layer to electrically connect the at least one wiring layer and the electrode pad by way of the wiring formed on the sidewall of the first via hole,
wherein the rear surface of the first semiconductor chip is positioned on a side opposite to the target circuit surface,
wherein the electrode pad has an exposed surface that is exposed from the second surface of the first sealing insulating layer,
wherein the entire rear surface and the exposed surface are flush with the second surface of the first sealing insulating layer,
wherein a second penetration wiring being formed in a second via hole to electrically connect the at least one wiring layer and the first semiconductor chip by way of a filled-via,
wherein the first and second penetration wirings each has a truncated-cone shape,
wherein the second sealing insulating layer includes a through-hole that exposes a second electrode pad,
wherein the second penetration wiring directly connects the at least one wiring layer and the first semiconductor chip,
wherein the second via hole is completely filled by the second penetration wiring,
wherein the inorganic member has no semiconductor integrated circuit formed thereon.
2. The semiconductor package as claimed in
wherein a plurality of wiring layers and a plurality of insulating layers are alternately layered on the first surface of the first sealing insulating layer;
wherein the second semiconductor chip is mounted on one of the plural insulating layers that is positioned farthest from the first sealing insulating layer.
4. The semiconductor package as claimed in
wherein the second semiconductor chip includes a target circuit surface and a side surface,
wherein the second sealing insulating layer is a single layer that seals the target circuit surface and the side surface of the second semiconductor chip.
5. The semiconductor package as claimed in
wherein the inorganic member includes an upper surface and a side surface,
wherein the second sealing insulating layer is a single layer that seals the upper surface and the side surface of the inorganic member.
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This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2011-206549 filed on Sep. 21, 2011, the entire contents of which are incorporated herein by reference.
The embodiments discussed herein are related to a semiconductor package and a method for manufacturing the semiconductor package; for example, a semiconductor package having a semiconductor chip embedded therein and a method for manufacturing the semiconductor package.
Conventionally, there is proposed a semiconductor package having a semiconductor chip embedded therein. For example, the semiconductor package includes a first insulating layer sealing a target circuit surface (i.e. a surface on which a circuit is formed) and a side surface of a semiconductor chip, a first wiring layer formed (layered) on the first insulating layer and electrically connected to an electrode pad of the semiconductor chip, and other insulating layers and wiring layers formed on the first wiring layer.
The semiconductor package may be manufactured by the following steps. First, the first insulating layer is formed by arranging a semiconductor chip on a support member and sealing the target circuit surface and the side surface of the semiconductor chip. Then, a via hole, which exposes an electrode pad of the semiconductor chip, is formed in the first insulating layer. Then, a wiring layer, which is electrically connected to the electrode pad of the semiconductor chip interposed by way of the via hole, is formed on the first insulating layer. Then, for example, one or more other insulating layers and wiring layers are formed on the first wiring layer. Then, by removing the support member, the manufacturing of the semiconductor package is completed.
However, the above-described semiconductor package has a structure in which the semiconductor chip is embedded only in the first insulating layer on a first side of the semiconductor package (with respect to the thickness direction) and only has a layered body including the insulating layer and the wiring layer on a second side of the semiconductor package (with respect to the thickness direction) without having the semiconductor chip embedded therein. This structure may lead to a problem of warping of the semiconductor package.
More specifically, in a case where the main component of the semiconductor chip is silicon, the thermal expansion coefficient of the semiconductor chip is approximately 3.4 ppm/° C., and the Young's modulus of the semiconductor chip is 200 GPa. Meanwhile, in a case where an epoxy type resin is the main component of the first insulating layer or the other insulating layer, the thermal expansion coefficient of the first insulating layer or the other insulating layer is approximately 8-150 ppm/° C. and the Young's modulus of the first insulating layer or the other insulating layer is approximately 0.03-13 GPa. Due to the different values of the physical properties (thermal expansion coefficient, Young's modulus) of the semiconductor package, the side of the semiconductor package having the semiconductor chip embedded in the first insulating layer (i.e. the first side of the semiconductor package) is resistant to deformation due to thermal stress or the like whereas the side of the semiconductor chip having no semiconductor chip embedded (i.e. the second side of the semiconductor package) tends to easily deform due to thermal stress or the like.
As a result, warping of the semiconductor package occurs at room temperature of, for example, approximately 20-30° C. (in this case, the semiconductor package tends to project toward the first side of the semiconductor package), and warping of the semiconductor chip occurs at a high temperature of, for example, approximately 200-300° C., (in this case, the semiconductor chip tends to become recessed toward the first side of the semiconductor package).
Because the semiconductor chip and layers such as the first insulating layer and the first wiring layer are formed on the substrate member having high rigidity according to the above-described steps for manufacturing the semiconductor package, warping hardly occurs before the removal of the support member. However, the removal of the support member causes loss of balance (unevenness) in the values of the physical properties (e.g., thermal expansion coefficient, Young's modulus) of the semiconductor package. This leads to warping of the semiconductor package.
According to an aspect of the invention, there is provided a semiconductor package including a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the insulating layer and configured to seal the second semiconductor chip.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing generation description and the followed detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
In the following, embodiments of the present invention are described with reference to the accompanying drawings.
[Structure of Semiconductor Package of First Embodiment]
The wiring substrate 30 is a wiring substrate having a semiconductor chip embedded therein (chip-embedded wiring substrate). The wiring substrate 30 includes, for example, a semiconductor chip 20, a wiring layer 31, an insulating layer 32, a wiring layer 33, an insulating layer 34, a wiring layer 35, an insulating layer 36, a wiring layer 37, and a solder resist layer 38.
Although the position of the semiconductor package 10 may be upside down depending on how the semiconductor package 10 is mounted, the side of the semiconductor package 10 toward the insulating layer 32 is described as a lower side of the semiconductor package 10 and the side of the semiconductor package 10 toward the sealing resin 49 is described as an upper side of the semiconductor package 10 for the sake of convenience. Therefore, for example, a surface of the insulating layer 32 that contacts the insulating layer 34 is referred to as an upper (top) surface 32a of the insulating layer 32, and a surface of the insulating layer. 32 that is exposed (i.e. surface on the opposite side of the upper surface of the insulating layer 32) is referred to as a lower (bottom) surface 32b of the insulating layer 32. This not only applies to the first embodiment but also to the embodiments described below.
The semiconductor package 10 has, for example, a rectangular shape in plan view. The semiconductor package 10 has a size in which the width is, for example, approximately 10 mm (X direction), the depth is, for example, approximately 10 mm (Y direction), and the thickness is, for example, approximately 0.5 mm (Z direction). Next, components (e.g., semiconductor chip 20) constituting the semiconductor package 10 are described in further detail.
The semiconductor chip 20 includes, for example, a semiconductor substrate 21, an electrode pad 22, and a bump (protruding electrode) 23. The semiconductor chip 20 has, for example, a rectangular shape in plan view. The semiconductor chip 20 has a size in which the width is, for example, approximately 5 mm (X direction), the depth is, for example, approximately 5 mm (Y direction), and the thickness is, for example, approximately 100 μm (Z direction).
The semiconductor substrate 21 may be a substrate including, for example, silicon (Si) as a main component and having a semiconductor integrated circuit (not illustrated) formed thereon. The electrode pad 22 is formed on the side of the target circuit surface 20a of the semiconductor substrate (i.e. surface of the semiconductor substrate 21 of the semiconductor chip 20 on which the semiconductor integrated circuit is to be formed). The electrode pad 22 is electrically connected to the semiconductor integrated circuit (not illustrated) of the semiconductor substrate 21. For example, aluminum (Al) may be used as the material of the electrode pad 22. Alternatively, a material having a copper (Cu) layer and an aluminum (Al) layer layered in this order or a material having copper (Cu) layer, an aluminum (Al) layer, and a silicon (Si) layer layered in this order may be used as the material of the electrode pad 22.
The bump 23 is formed on the electrode pad 22. For example, a copper post having a pillar shape may be used as the bump 23. The diameter of the bump 23 may be, for example, approximately 50 μm. The height of the bump 23 may be, for example, approximately 5-10 μm. The pitch between the bumps 23 may be, for example, approximately 100 μm. It is to be noted that the bump 23 does not necessarily have to be formed on the electrode pad 22. In a case where the bump 23 is not formed on the electrode pad 22, the electrode pad 22 itself serves as an electrode to be electrically connected to the wiring layer 33.
The surface of the semiconductor chip 20, which is on the opposite side of the target circuit surface 20a and substantially parallel to the target circuit surface, may be hereinafter referred to as a “rear surface” 20b of the semiconductor chip 20. Further, the surface of the semiconductor chip 20, which is substantially perpendicular to the target circuit surface 20a and the rear surface 20b of the semiconductor chip 20, may be hereinafter referred to as a “side surface” 20c of the semiconductor chip 20.
The target circuit surface 20a and the side surface 20c of the semiconductor chip 20 are sealed by the insulating layer 32. An adhesive layer 24 (e.g., die attach film) is exposed on the rear surface of the semiconductor chip 20. The adhesive layer 24, which is adhered to the rear surface of the semiconductor chip 20, is substantially flush with the bottom surface 32b of the insulating layer 32. Because the thickness of the adhesive layer 24 is approximately a few 10 s of micrometers (μm), the rear surface of the semiconductor chip 20 may be considered to be substantially flush with the bottom surface 32b of the insulating layer 32.
Although
The wiring layer 31 includes first and second layers 31a, 31b. For example, the first layer 31a may be a conductive layer including a gold (Au) film, a palladium (Pd) film, and a nickel (Ni) film layered in this order and having the gold (Au) film exposed toward the outside of the semiconductor package 10. Alternatively, the first layer 31a may be a conductive layer including a gold (Au) film and a nickel (Ni) film layered in this order and having the gold (Au) film exposed toward the outside of the semiconductor package 10. For example, the second layer 31b may be a conductive layer such as a copper layer. The thickness of the wiring layer 31 may be, for example, approximately 10 μm to 20 μm.
A part of the wiring layer 31 (bottom surface of the first layer 31a) is exposed on the insulating layer 32 and is substantially flush with the bottom surface 32b of the insulating layer 32 and the rear surface of the semiconductor chip 20 or the adhesive layer 24 adhered to the rear surface of the semiconductor chip 20. The part of the wiring layer 31 (bottom surface of the first layer 31a) functions as an electrode pad which is electrically connected to, for example, another semiconductor package, a semiconductor chip, a mounting substrate (e.g., motherboard), or an electronic component (not illustrated). The part of the wiring layer 31 exposed on the insulating layer 32 may hereinafter be referred to as “first electrode pad 31”.
The number of first electrode pads 31 illustrated in
The insulating layer 32 seals the upper and side surfaces of the wiring layer 31 along with the target circuit surface 20a and the side surface 20c of the semiconductor chip 20. The bottom surface of the wiring layer 31 and the adhesive layer 24 are exposed on the insulating layer 32. An insulating resin having a thermosetting property may be used as the material of the insulating layer 32. For example, a material having an epoxy type resin or a phenol type resin as a main component may be used as the material of the insulating layer 32. The thickness of the insulating layer 32 may be, for example, approximately 150 μm. The insulating layer 32 may include a filler such as silica (SiO2). The insulating layer 32 is a representative example of the first sealing insulating layer according to an embodiment of the present invention.
A via hole 32x, which penetrates the insulating layer 32 and exposes the upper surface of the wiring layer 31, is formed in the insulating layer 32. Further, a via hole 32y, which penetrates the insulating layer 32 and exposes the upper surface of the bump 23, is also formed in the insulating layer 32. In this embodiment, the via hole 32x is a recess having a shape of a circular truncated cone. The via hole 32x has an opening part toward the insulating layer 34 and a bottom surface part on the upper surface of the wiring layer 31. The area of the opening part of the via hole 32x is larger than the area of the bottom surface part of the via hole 32x. The diameter of the opening part of the via hole 32x may be, for example, approximately 150 μm.
The via hole 32y is a recess having a shape of a circular truncated cone. The via hole 32y has an opening part toward the insulating layer 34 and a bottom surface part on the upper surface of the bump 23. The area of the opening part of the via hole 32y is larger than the area of the bottom surface part of the via hole 32y. The diameter of the opening part of the via hole 32y may be, for example, approximately 30 μm.
The wiring layer 33 is formed on the insulating layer 32. The wiring layer 33 includes a first via wiring (penetration wiring), a second via wiring (penetration wiring), and a wiring pattern. The first via wiring is formed on a sidewall of the via hole 32x and an upper surface 32a of the insulating layer 32. The second via wiring fills the inside of the via hole 32y. The wiring pattern of the wiring layer 33 is also formed on the insulating layer 32.
The wiring layer 33 is electrically connected to the wiring layer 31 exposed on the bottom surface part of the via hole 32x and the bump 23 exposed on the bottom surface part of the via hole 32y. For example, a metal material having copper (Cu) as a main component may be used as the material of the wiring layer 33. The thickness of the wiring pattern of the wiring layer 33 may be, approximately 10 μm to 20 μm.
For example, in a case where the thickness of the insulating layer 32 is 150 μm, and the thickness of the wiring layer 31 is 10 μm, the depth of the via hole 32x would be 140 μm. The depth of the via hole 32x in this case makes it difficult to fill the inside of the via hole 32x with the first via wiring. Therefore, rather than filling the inside of the via hole 32x with the first via wiring, the first via wiring is formed as a film that only covers the sidewall of the via hole 32x and the upper surface of the wiring layer 31. On the other hand, in a case where the thickness of the insulating layer 32 is 150 μm, and the thickness of the semiconductor chip 20 (including the height of the bump 23), the depth of the via hole 32y would be 50 μm. The depth of the via hole 32y is significantly shallower than the depth of the via hole 32x. Therefore, the second via wiring fills the inside of the via hole 32y.
The insulating layer 34 is formed on the insulating layer 32 and covers the wiring layer 33. For example, the same insulating resin used for the insulating layer 32 may be used as the material of the insulating layer 34. The thickness of the insulating layer 34 may be, for example, approximately 15 μm to 35 μm. The insulating layer 34 may include a filler such as silica (SiO2).
The wiring layer 35 is formed on the insulating layer 34. The wiring layer 35 includes a via wiring and a wiring pattern. The via wiring of the wiring layer 35 penetrates the insulating layer 34 and fills the inside of a via hole 34x exposed on the upper surface of the wiring layer 33. The via hole 34x is a recess having a shape of a circular truncated cone. The via hole 34x has an opening part toward the insulating layer 36 and a bottom surface part on the upper surface of the wiring layer 33. The area of the opening part of the via hole 34x is larger than the area of the bottom surface part of the via hale 34x. A via wiring is formed inside the recess of the via hole 34x.
The wiring layer 35 is electrically connected to the wiring layer 33 exposed on the bottom surface part of the via hole 34x. For example, a metal material having copper (Cu) as a main component may be used as the material of the wiring layer 35. The thickness of the wiring pattern of the wiring layer 35 may be, for example, approximately 10 μm to 20 μm.
The insulating layer 36 is formed on the insulating layer 34 and covers the wiring layer 35. For example, the same insulating resin used for the insulating layer 32 may be used as the material of the insulating layer 36. The thickness of the insulating layer 36 may be, for example, approximately 15 μm to 35 μm. The insulating layer 36 may include a filler such as silica (SiO2).
The wiring layer 37 is formed on the insulating layer 36. The wiring layer 37 includes a via wiring and a wiring pattern. The via wiring of the wiring layer 37 penetrates the insulating layer 36 and fills the inside of a via hole 36x exposing the upper surface of the wiring layer 35. The wiring pattern of the wiring layer 37 is formed on the insulating layer 36. The via hole 36x is a recess having a shape of a circular truncated cone. The via hole 36x has an opening part toward the solder resist layer 38 and a bottom surface part on the upper surface of the wiring layer 35. The area of the opening part of the via hole 36x is larger than the area of the bottom surface part of the via hole 36x. The via wiring of the wiring layer 37 is formed inside the recess of the via hole 36x.
The wiring layer 37 is electrically connected to the wiring layer 35 exposed on the bottom surface part of the via hole 36x. For example, a metal material having copper (Cu) as a main component may be used as the material of the wiring layer 37. The thickness of the wiring pattern of the wiring layer 37 may be, for example, approximately 10 μm to 20 μm.
The solder resist layer 38 is formed on the insulating layer 36 and covers the wiring layer 37. The thickness of the solder resist layer 38 may be, for example, approximately 15 μm to 35 μm. The solder resist layer 38 may include a filler such as silica (SiO2). The solder resist layer 38 includes an opening part 38x having a bottom part that exposes a part of the wiring layer 37.
The part of the wiring layer 37, which is exposed at the bottom part of the opening part 38x, functions as an electrode pad that is electrically connected to the semiconductor chip 40. The part of the wiring layer 37 exposed at the bottom part of the opening part 38x may hereinafter be referred to as a “second electrode pad 37”. The second electrode pad 37 has, for example, a circular shape from plan view. The diameter of the circular-shaped second electrode pad 37 may be, for example, approximately 100 μm to 350 μm. The pitch between the second electrode pads 37 may be, for example, approximately 400 μm to 500 μm.
A metal layer may be formed on the second electrode pad 37 according to necessity. The metal layer may be, for example, a gold layer (Au), a nickel/gold (Ni/Au) layer (i.e. metal layer including a Ni layer and a Au layer layered in this order), or a nickel/palladium/gold (Ni/Pd/Au) layer (i.e. metal layer including a Ni layer, a Pd layer, and a Au layer layered in this order). It is to be noted that the solder resist layer 38 may be simply referred to as an insulating layer.
The semiconductor chip 40 is mounted on the wiring substrate 30. The semiconductor chip 40 includes a semiconductor substrate 41 and an electrode pad 42. The semiconductor chip 40 has, for example, a rectangular shape in plan view. The semiconductor chip 40 has a size in which the width is, for example, approximately 8 mm (X direction), the depth is, for example, approximately 8 mm (Y direction), and the thickness is, for example, approximately 200 μm (Z direction).
The semiconductor substrate 41 may be a substrate having, for example, silicon (Si) as a main component and having a semiconductor integrated circuit (not illustrated) formed thereon. The electrode pad 42 is formed on the side of the target circuit surface 40a of the semiconductor substrate (i.e. surface of the semiconductor substrate 41 of the semiconductor chip 40 on which the semiconductor integrated circuit is to be formed). The electrode pad 42 is electrically connected to the semiconductor integrated circuit (not illustrated) of the semiconductor substrate 41. The pitch between the electrode pads 42 may be, for example, approximately 100 μm.
For example, aluminum (Al) may be used as the material of the electrode pad 42. Alternatively, a material having a copper (Cu) layer and an aluminum (Al) layer layered in this order or a material having a copper (Cu) layer, an aluminum (Al) layer, and a silicon (Si) layer layered in this order may be used as the material of the electrode pad 42.
The semiconductor chip 40 is fixed on the solder resist layer 38 interposed by an adhesive layer (e.g., die attach film) 43. The electrode pad 42 of the semiconductor chip 40 is bonded to the second electrode pad 37 of the wiring substrate 30 by way of the bonding wire 45. The bonding wire 45 is a thin conductive wire formed of, for example, gold (Au) or copper (Cu).
The sealing resin 49 is formed covering the target circuit surface 40a and the side surface of the semiconductor chip 40 and the bonding wire 45. For example, an insulating resin (mold resin) such as an epoxy type resin having a thermosetting property or a polyimide type resin may be used as the material of the sealing resin 49. The sealing resin 49 may include a filler such as silica (SiO2). The thickness of the sealing resin 49 may be, for example, 300 μm to 400 μm.
The sealing resin 49 has a function of protecting the semiconductor chip 40 and the bonding wire 45 from externally applied stress, humidity, and contaminants. The sealing resin 49 also has a function of improving the mechanical strength of the semiconductor package 10. However, because the overall mechanical strength of the semiconductor package 10 can be improved by mounting the semiconductor chip 40 thereon, the semiconductor package 10 may be formed without the sealing resin 49. The sealing resin 49 is a representative example of the second sealing insulating layer according to an embodiment of the present invention.
[Method for Manufacturing Semiconductor Package According to First Embodiment]
Next, a method for manufacturing the semiconductor package 10 according to the first embodiment of the present invention is described.
First, the wiring substrate 30 is manufactured by performing the steps illustrated in
In order to form the resist layer 52 having the opening part 52x, a liquid or paste-like resin formed of a photosensitive resin compound is applied to the first surface 51a of the supporting member 51. The photosensitive resin compound of the liquid or paste-like resist may include, for example, an epoxy type resin or an acrylic type resin. Alternatively, a film-like resin (e.g., dry film resist) formed of a photosensitive resin compound may be laminated on the first surface 51a of the supporting member 51. The photosensitive resin compound of the film-like resin may include, for example, an epoxy type resin or an acrylic type resin.
Then, the opening part 52x is formed by exposing and developing the applied or laminated photosensitive resin compound. Thereby, the resist layer 52 having the opening part 52x is formed. Alternatively, a film-like resist including the opening part 52x formed beforehand may be laminated on the first surface 51a of the supporting member 51. The opening part 52x is formed in a position corresponding to a position at which the wiring layer 31 is formed in the below-described process illustrated in
Then, in the process illustrated in
Therefore, first, in order to form the wiring layer 31, the first layer 31a having the layered structure is formed by performing, for example, an electroplating method using the supporting member 51 as the power feeding layer. In forming the layered structure of the wiring layer 31, a gold (Au) film, a palladium (Pd) film, and a nickel (Ni) film are plated in this order. Then, the second layer 31b is formed on the first layer 31a by, performing, for example, an electroplating method using the supporting member 51 as the power feeding layer. The second layer 31b may be formed of, for example, copper (Cu). Alternatively, the first layer 31a may have a layered structure having a gold (Au) film and a nickel (Ni) film layered in this order.
Then, in the process illustrated in
Then, in the process illustrated in
In a case where, for example, a film-like thermosetting insulating resin having an epoxy type resin or a phenol type resin as a main component is used as the material of the insulating layer 32, the insulating layer 32 is formed as follows.
An insulating resin film being in a semi-cured state is laminated on the first surface 51a of the supporting member 51. The laminated insulating resin covers the target circuit surface 20a and the side surface 20c of the semiconductor chip 20 and the upper and side surfaces of the wiring layer 31. Then, the laminated insulating resin is cured by applying a pressing force to the laminated resin while heating the laminated insulating resin to a temperature greater than or equal to a thermosetting temperature. Thereby, the insulating layer 32 is formed. It is to be noted that generation of voids can be prevented by laminating the insulating resin in a vacuum atmosphere.
In a case where, for example, a liquid or a paste-like thermosetting insulating resin having an epoxy type resin or a phenol type resin as a main component is used as the material of the insulating layer 32, the insulating layer 32 is formed as follows. An insulating resin liquid or paste is applied on the first surface 51a of the supporting member 51 by using, for example, a roll-coating method. The applied insulating resin covers the target circuit surface 20a and the side surface 20c of the semiconductor chip 20 and the upper and side surfaces of the wiring layer 31. Then, the applied insulating resin is cured by heating the applied insulating resin to a temperature greater than or equal to a thermosetting temperature. Thereby, the insulating layer 32 is formed.
Then, in the process illustrated in
Then, in the process illustrated in
In a case where the via holes 32x, 32y are formed by using the laser processing method, it is preferable to remove residual resin of the insulating layer 32 adhered to the upper surface of the wiring layer 31 (exposed on the bottom surface part of the via hole 32x) and the upper surface of the bump 23 (exposed on the bottom surface part of the via hole 32y). Therefore, in this case, a desmearing process may be used to remove the residual resin of the insulating layer 32.
In the process illustrated in
For example, a metal material having copper (Cu) as a main component may be used as the material of the wiring layer 33. The thickness of the wiring pattern of the wiring layer 33 may be, approximately 10 μm to 20 μm. As described above, due to, for example, the difficulty of filling the inside of the via hole 32x with the first via wiring, the first via wiring does not substantially completely fill the via hole 32x whereas the second via wiring does substantially completely fill the via hole 32y.
Although the wiring layer 33 may be formed by using various wiring forming methods (e.g., semi-additive method, subtractive method), an example of forming the wiring layer 33 with the semi-additive method is described below.
First, a seed layer (not illustrated) is formed on the upper surface of the wiring layer 31 exposed in the via hole 32x, the upper surface of the bump 23 exposed in the via hole 32y, and the insulating layer 32 including the sidewalls of the via holes 32x, 32y. For example, a seed layer, that is formed of a metal material having capper (Cu) as a main component, may be formed by performing an electroless plating method or a sputtering method. Then, a resist layer (not illustrated) having an opening part corresponding to the wiring layer 33 is formed on the seed layer.
Then, a wiring layer (not illustrated), that is formed of a metal material having copper (Cu) as a main component, is formed in the opening part of resist layer. The wiring layer is formed by an electroplating method using the seed layer as the power feeding layer. Then, after removing the resist layer, a part of the seed layer that is not covered by the wiring layer is removed by using the wiring layer as a mask and etching the part of the seed layer that is not covered by the wiring layer. Thereby, the wiring layer 33 including the first via wiring (having been formed on the sidewall of the via hole 32x and the upper surface of the wiring layer 31), the second via wiring (filling the inside of the via hole 32y), and the wiring pattern (having been formed on the insulating layer 32) is formed.
Then, in the process illustrated in
Then, the wiring layer 35 is formed on the insulating layer 34. The wiring layer 35 is connected to the wiring layer 33 by way of the via hole 34x. The wiring layer 35 includes a via wiring that fills the inside of the via hole 34x and the wiring layer that is formed on the insulating layer 34. The wiring layer 35 is electrically connected to the wiring layer 33 exposed in the bottom surface part of the via hole 34x. For example, a metal material having capper (Cu) as a main component may be used as the material of the wiring layer 35. The wiring layer 35 may be formed by using, for example, a semi-additive method. The thickness of the wiring pattern of the wiring layer 35 may be, for example, approximately 10 μm to 20 μm.
Then, the via hole 36x, which penetrates the insulating layer 36 and exposes the upper surface of the wiring layer 35, is formed after the insulating layer 36 covering the wiring layer 35 is formed on the insulating layer 34. The material of the insulating layer 36 may be the same insulating resin used for forming the insulating layer 34. The thickness of the insulating layer 36 may be, for example, approximately 15 μm to 35 μm. The insulating layer 36 may include a filler such as silica (SiO2).
Then, the wiring layer 37 is formed on the insulating layer 36. The wiring layer 37 is connected to the wiring layer 35 by way of the via hole 36x. The wiring layer 37 includes a via wiring that fills the inside of the via hole 36x and the wiring layer that is formed on the insulating layer 36. The wiring layer 37 is electrically connected to the wiring layer 35 exposed in the bottom surface part of the via hole 36x. For example, a metal material having copper (Cu) as a main component may be used as the material of the wiring layer 37. The wiring layer 37 may be formed by using, for example, a semi-additive method. The thickness of the wiring pattern of the wiring layer 37 may be, for example, approximately 10 μm to 20 μm.
Thereby, a predetermined built-up wiring structure is formed on the first surface 51a of the supporting member 51. Although a built-up wiring structure including 3 layers (wiring layers 33, 35, and 37) is formed in the above-described embodiment, a built-up wiring structure including n layers (“n” being an integer greater than or equal to 1) may be formed.
Then, in the process illustrated in
The opening part 38x can be formed by exposing and developing the applied or laminated insulating resin (photolithographic method). Alternatively, a film-like insulating resin having the opening part 38x formed beforehand may be laminated on the insulating layer 36 and cover the wiring layer 37. Alternatively, a non-photosensitive insulating resin may be used as the material of the solder resist layer 38. In the case where the non-photosensitive insulating resin is used, the opening part 38x is formed by, for example, using a laser processing method using CO2 laser or performing a blasting process using a polishing agent (e.g., alumina abrasive grain) after the solder resist layer 38 is formed on the insulating layer 36 and cured.
According to necessity, a metal layer may be formed on the wiring layer 37 exposed in the bottom surface part of the opening part 38x by using, for example, an electroless plating method. The metal layer may be, for example, a gold layer (Au), a nickel/gold (Ni/Au) layer (i.e. metal layer including a Ni layer and a Au layer layered in this order), or a nickel/palladium/gold (Ni/Pd/Au) layer (i.e. metal layer including a Ni layer, a Pd layer, and a Au layer layered in this order).
Then, in the process illustrated in
Then, in the process illustrated in
Then, after performing the process illustrated in
It is to be noted that the rear surface of the semiconductor chip 20 may be exposed from the insulating layer 32 after removing the supporting member 51 and then removing the adhesive layer 24 adhered to the rear surface of the semiconductor chip 20 by using, for example, a plasma etching process.
The semiconductor package 10 has a first surface side on which the semiconductor chip 20 is formed and a second surface side on which the semiconductor chip 40 is formed. In a case where silicon (Si) is the main component of both of the semiconductor chips 20, 40, the thermal expansion coefficient of both of the semiconductor chips 20, 40 is approximately 3.4 ppm/° C., and the Young's modulus of both of the semiconductor chips 20, 40 is approximately 200 GPa.
In other words, the semiconductor package 10 has a structure in which components having a low thermal expansion coefficient and a high Young's modulus are arranged symmetrical to each other in the vertical direction (i.e. arranged on the upper and lower sides of the semiconductor package 10). Thereby, the values of the physical properties (e.g., thermal expansion coefficient, Young's modulus) between the upper and lower sides of the semiconductor package 10 can be balanced. Thus, the structure of the semiconductor package 10 prevents the above-described problem of the semiconductor package of the related art example (i.e. the side in which the semiconductor chip is embedded is resistant to deformation from thermal stress or the like whereas the side in which the semiconductor chip is not embedded tends to deform due to thermal stress or the like). Therefore, even after the supporting member 51 is removed after the process illustrated in
As illustrated in
With the semiconductor package 10 according to the first embodiment of the present invention, there can be provided a structure in which components having a low thermal expansion coefficient and a high Young's modulus are substantially symmetrically arranged with respect to the vertical direction (Z direction) of the semiconductor package 10. Thereby, the values of the physical properties (e.g., thermal expansion coefficient, Young's modulus) between the upper and lower sides of the semiconductor package 10 can be balanced. Accordingly, the semiconductor package 10 can be prevented from being warped by thermal stress or the like.
Because the semiconductor package 10 has a structure in which components having a low thermal expansion coefficient and a high Young's modulus are substantially symmetrically arranged with respect to the vertical direction of the semiconductor package 10, the mechanical strength of the entire semiconductor package can be improved.
With the method for manufacturing the semiconductor package 10 according to the first embodiment of the present invention, the semiconductor chip 40 is mounted on the solder resist layer 39 of the wiring substrate 30 (i.e. on the side opposite from the semiconductor chip 20 in the vertical direction) before the removal of the supporting member 51. Therefore, the semiconductor package 10 has a structure in which the semiconductor chips 20, 40 having high rigidity are arranged on the upper and lower sides of the semiconductor package 10. Thereby, the values of the physical properties (e.g., thermal expansion coefficient, Young's modulus) between the upper and lower sides of the semiconductor package 10 can be balanced. As a result, even after the supporting member 51 is removed after the process illustrated in
Unlike a case of connecting a semiconductor chip to a wiring substrate by using a flip-chip bonding method, a semiconductor chip need not be heated in a case of connecting the semiconductor chip on a wiring substrate by way of a bonding wire. Therefore, according to the above-described embodiment of the present invention, the method of connecting the semiconductor chip on the wiring substrate by way of the bonding wire is effective for preventing the wiring substrate from warping and reducing bending of the wiring substrate.
In the following first modified example of the first embodiment of the present invention, a semiconductor package is manufactured by a method different from the manufacturing method of the above-described first embodiment of the present invention. In the description and drawings of first modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
In the process illustrated in
Then, in the process illustrated in
Then, after the process illustrated in
By preparing the supporting member 55 having the first and the second supporting members 511, 512 adhered one on top of the other, the layered structure including the wiring substrate 30 can be simultaneously formed on the upper surface of the first supporting member part 511 and the lower surface of the second supporting member part 512. Then, by separating the supporting member 51 into the first and the second supporting member parts 511, 512 and removing the first and the second supporting member parts 511, 512 along with performing the above-described series of processes illustrated in
In the following second modified example of the first embodiment of the present invention, a semiconductor chip is formed on a wiring substrate by using a flip-chip bonding method. In the description and drawings of second modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
The semiconductor chip 60 includes a semiconductor chip 61 and an electrode pad 62. Because the semiconductor chip 61 and the electrode pad 62 have substantially the same configuration as that of the semiconductor chip 40 and the electrode pad 42, description of the semiconductor chip 61 and the electrode pad 62 is omitted. Unlike the semiconductor chip 40, the semiconductor chip 60 is mounted on the wiring substrate 30 in a state facing downward (i.e. a state having the target circuit surface facing downward). More specifically, the electrode pad 62 of the semiconductor chip 60 is electrically connected to the second electrode pad 37 of the wiring substrate 30 by way of a bonding part 65.
The bonding part 65 may be, for example, a solder ball. For example, an alloy including lead (Pb), an alloy including tin (Sn) and copper (Cu), an alloy including tin (Sn) and antimony (Sb), an alloy including tin (Sn) and silver (Ag), or an alloy including tin (Sn), silver (Ag), and copper (Cu) may be used as the material of the solder ball. The semiconductor chip 60 is sealed by the sealing resin 49. In order to improve the heat releasing property of the semiconductor package 10A, the rear surface of the semiconductor chip 60 may be exposed from the sealing resin 49. Similar to the semiconductor package 10, the semiconductor package 10A may be formed without the sealing resin 49 because the overall mechanical strength of the semiconductor package 10A can be improved by mounting the semiconductor chip 60. Further, an underfill resin may be provided between the semiconductor chip 60 and the wiring substrate 30.
Accordingly, the semiconductor package 10A of the second modified example can attain substantially the same effects as those of the semiconductor package 10 of the first embodiment even in a case where the semiconductor chip 60 is connected to the wiring substrate 30 by flip-chip bonding.
In the following third modified example of the first embodiment of the present invention, a semiconductor chip is formed on a wiring substrate by using an anisotropic conductive film. In the description and drawings of third modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
Unlike the semiconductor chip 40, the semiconductor chip 60 of the third modified example is mounted on the wiring substrate 30 in a state facing downward (i.e. a state having the target circuit surface facing downward). More specifically, a bump 63 is formed on the electrode pad 62 of the semiconductor chip 60. For example, a copper post having a pillar shape may be used as the bump 63. The bump 63 is electrically connected to the second pad 37 of the wiring substrate 30 by way of an anisotropic conductive film.
For example, a semi-cured resin film (e.g., epoxy type thermosetting resin) having conductive particles of nickel (Ni), gold (Au), or silver (Ag) dispersed therein may be used as the anisotropic conductive film.
The semiconductor chip 60 is sealed by the sealing resin 49. In order to improve the heat releasing property of the semiconductor package 10B, the rear surface of the semiconductor chip 60 may be exposed from the sealing resin 49. Similar to the semiconductor package 10, the semiconductor package 10B may be formed without the sealing resin 49 because the overall mechanical strength of the semiconductor package 10B can be improved by mounting the semiconductor chip 60.
Next, a method for electrically connecting the bump 63 of the semiconductor chip 60 and the second electrode pad 37 of the wiring substrate 30 by using the anisotropic conductive film 69 is described. First, the anisotropic conductive film 69 is adhered (temporarily stuck) to the solder resist layer 38 of the wiring substrate 30, so that the second electrode pad 37 is covered by the anisotropic conductive film 69.
Then, the semiconductor chip 60 is prepared. Then, the position of the bump 63 of the semiconductor chip 60 is matched with the position of the second electrode pad 37 of the wiring substrate 30, so that the bump 63 of the semiconductor chip 60 faces the corresponding second electrode pad 37 of the wiring substrate 30 interposed by the anisotropic conductive film 69. The matching of the position of the bump 63 of the semiconductor chip 60 and the position of the second electrode pad 37 of the wiring substrate 30 may be performed by using, for example, a bonding tool.
Then, a pressing force is applied from the semiconductor chip 60 to the anisotropic conductive film 69 by using, for example, a bonding tool. For example, in the case where the bonding tool is used, the anisotropic conductive film 69 is cured by applying a pressing force to the anisotropic conductive film 69 being in a semi-cured state while heating the semiconductor chip 60.
In curing the anisotropic conductive film 69, the anisotropic conductive film 69 is compressed by holding (sandwiching) the anisotropic conductive film 69 between the bump 63 of the semiconductor chip 60 and the second electrode pad 37 of the wiring substrate 30. This causes the conductive particles dispersed in the anisotropic conductive film 69 to contact each other and electrically connect the bump 63 of the semiconductor chip 60 and the second electrode pad 37 of the wiring substrate 30.
Accordingly, the semiconductor package 10B of the third modified example can attain substantially the same effects as those of the semiconductor package 10 of the first embodiment even in a case where the semiconductor chip 60 is connected to the wiring substrate 30 by the anisotropic conductive film 69.
In the following fourth modified example of the first embodiment of the present invention, a semiconductor chip is formed on a wiring substrate by using a flip-chip bonding method and another semiconductor chip is formed on the semiconductor chip by using the flip-chip bonding method. In the description and drawings of fourth modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
The semiconductor chip 70 includes a semiconductor substrate 71, electrode pads 72, 74, and a through-electrode 73. The electrode pad 72 is provided on the first side of the semiconductor substrate 71. The electrode pad 74 is provided on the second side of the semiconductor substrate 71 (a side opposite to the first side of the semiconductor substrate. The electrode pad 72 and the electrode pad 74 are electrically connected to each other by way of the through-electrode 73.
Because the semiconductor substrate 71 and the electrode pads 72, 74 have substantially the same configuration as that of the semiconductor substrate 41 and the electrode pad 42 of the semiconductor chip 40, description of the semiconductor substrate 71 and the electrode pads 72, 74 is omitted. For example, a metal material having copper (Cu) as a main component may be used as the material of the through-electrode 73.
The semiconductor chip 80 includes a semiconductor substrate 81 and an electrode pad 82. Because the semiconductor substrate 81 and the electrode pad 82 have substantially the same configuration as that of the semiconductor substrate 41 and the electrode pad 42 of the semiconductor chip 40, description of the semiconductor substrate 81 and the electrode pad 82 is omitted.
Unlike the semiconductor chip 40, the semiconductor chip 70 of the fourth modified example is mounted on the wiring substrate 30 in a state facing downward (i.e. a state having the target circuit surface facing downward). More specifically, the electrode pad 72 of the semiconductor chip 70 is electrically connected to the second electrode pad 37 of the wiring substrate 30 by way of the bonding part (e.g., solder ball) 65. The electrode pad 72 is electrically connected to a semiconductor integrated circuit (not illustrated) of the semiconductor chip 70.
The electrode pad 82 of the semiconductor chip 80 is electrically connected to the electrode pad 74 of the semiconductor chip 70 by way of a bonding part 75. Similar to the bonding part 65, a solder ball may be used as the bonding part 75.
The semiconductor chips 70, 80 are sealed by the sealing resin 49. In order to improve the heat releasing property of the semiconductor package 10C, the rear surface of the semiconductor chip 80 may be exposed from the sealing resin 49. Similar to the semiconductor package 10, the semiconductor package 10C may be formed without the sealing resin 49 because the overall mechanical strength of the semiconductor package 10C can be improved by mounting the semiconductor chips 70, 80.
In the following fifth modified example of the first embodiment of the present invention, a planar member having no semiconductor integrated circuit formed thereon is mounted on a wiring substrate. In the description and drawings of fifth modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
The planar member 90 is mounted on the solder resist layer 38 of the wiring substrate 30 and is sealed by the sealing resin 49. A through-hole 49x exposing the second electrode pad 37 is formed in the sealing resin 49. By forming the through-hole 49x, other semiconductor chips and electronic components (e.g., condenser) may be mounted on the sealing resin 49 and electrically connect with the second electrode pad 37 by way of the through-hole 49x.
The through-hole 49x has, for example, a circular shape from plan view. The diameter of the circular-shaped through-hole 49x may be, for example, approximately 100 μm to 350 μm. The through-hole 49x may be formed by, for example, a transfer molding method using a die having a protruding part corresponding to the through-hole, a laser processing method, or a blasting method.
In order to improve the heat releasing property of the semiconductor package 10D, the rear surface of the planar member 90 may be exposed from the sealing resin 49. Similar to the semiconductor package 10, the semiconductor package 10D may be formed without the sealing resin 49 because the overall mechanical strength of the semiconductor package 10D can be improved by mounting the planar member 49. It is preferable to form the planer member 90 by using an inorganic material having a planar shape. For example, a planar silicon, glass, or ceramic having no semiconductor integrated circuit formed thereon may be used as the planer member 90.
In a case where a type of glass such as borosilicate glass is used as the planar member 90, the thermal expansion coefficient of the planar member 90 is approximately 3 ppm/° C. In a case where a type of ceramic such as mullite is used as the planar member 90, the thermal expansion coefficient of the planar member 90 is approximately 4.5 ppm/t. In a case where alumina is used as the planar member 90, the thermal expansion coefficient of the planar member 90 is approximately 6-7 ppm/° C.
The thickness of the planar member may be, for example, approximately 200 μm. Although the planar member 90 is mounted on a part of the solder resist layer 38 in this embodiment, the planar member 90 may be mounted on the entire surface of the solder resist layer 38. In this case, a through-hole that exposes the second electrode pad 37 may be formed in the planar member 90 and the sealing resin 49.
Accordingly, the semiconductor package 10D of the fifth modified example can attain substantially the same effects as those of the semiconductor package 10 of the first embodiment even in a case where a planar member having substantially the same thermal expansion coefficient as the semiconductor chip 40 is formed on the wiring substrate 30.
In a case where other semiconductor chips or electronic components (e.g., condenser) are not further mounted on the sealing resin 49, the opening part 38x and the through-hole 49x need not be provided.
In the following sixth modified example of the first embodiment of the present invention, a semiconductor chip is formed on a wiring substrate by using a flip-chip bonding method and sealed with a sealing resin, and a through-hole is formed in the sealing resin. In the description and drawings of sixth modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
The semiconductor chip 60 of the sixth modified example is mounted on the wiring substrate 30 in a state facing downward (i.e. a state having the target circuit surface facing downward). More specifically, the electrode pad 62 of the semiconductor chip 60 is electrically connected to the second electrode pad 37 of the wiring substrate 30 by way of the bonding part 65. The semiconductor chip 60 is sealed by the sealing resin 49. In order to improve the heat releasing property of the semiconductor package 10E, the rear surface of the semiconductor chip 60 may be exposed from the sealing resin 49.
The through-hole 49x is formed in the sealing resin 49. The through-hole 49x penetrates the solder resist layer 38. A part of the wiring layer 37 is exposed in the through-hole 49x. The wiring layer 37 exposed in the through-hole 49x has functions as an electrode pad that is electrically connected to a semiconductor chip or an electronic component (e.g., condenser) mounted on the sealing resin.
Alternatively, the sealing resin 49 may be replaced with an underfill resin. In this case, the underfill resin is provided, so that a part of the wiring layer 37, which is to become an electrode pad, is exposed.
In addition to the effects attained by the first embodiment of the present invention, a semiconductor chip or an electronic component (e.g., condenser), which is to be electrically connected to the wiring layer 37, can be further mounted on the sealing resin 49 by connecting the semiconductor chip 60 to the wiring substrate 30 by flip-chip bonding and sealing the semiconductor chip 60 with the sealing resin 49.
In the following seventh modified example of the first embodiment of the present invention, a semiconductor chip is formed on a wiring substrate by using a flip-chip bonding method and sealed with an underfill resin. In the description and drawings of seventh modified example, like components are denoted by like reference numerals as those of the first embodiment and are not further described.
The underfill resin 79 is filled in a space between the semiconductor chip 60 and the wiring substrate 30. The underfill resin 79 is also formed covering a part of a side surface of the semiconductor chip 60. For example, an insulating resin such as an epoxy type resin may be used as the underfill resin 79. The underfill resin 79 is another representative example of the second sealing insulating layer according to an embodiment of the present invention.
After connecting the semiconductor chip 60 to the wiring substrate 30 by flip-chip bonding, the underfill resin 79 is formed by filling the space between the semiconductor chip 60 and the wiring substrate 30 with an insulating resin (e.g., epoxy type resin) and curing the insulating resin. Alternatively, the underfill resin 79 may be formed by placing an insulating resin film being in a semi-cured state on the wiring substrate 30, connecting the semiconductor chip 60 to the wiring substrate 30 (interposed by the insulating resin film) by flip-chip bonding, and curing the insulating resin film.
Accordingly, the semiconductor package 10F of the seventh modified example can attain substantially the same effects as those of the semiconductor package 10 of the first embodiment even in a case where the sealing resin 49 is replaced with the underfill resin 79.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
For example, although the semiconductor chip 20 is embedded in the outermost insulating layer 32 of the wiring substrate 30 according to the above-described embodiments and modified examples, the semiconductor chip 20 may be embedded in other insulating layers. However, in the case of embedding the semiconductor chip 20 in another insulating layer, the other insulating layer is to be determined in view of the balance between the values of the physical properties (e.g., thermal expansion coefficient, Young's modulus) of the upper and lower sides of the semiconductor package 10.
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 8035217, | Jun 08 2007 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing same |
| 20100052135, | |||
| 20100120176, | |||
| 20100252937, | |||
| 20120119379, | |||
| JP2005235807, | |||
| JP2008306071, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Sep 10 2012 | Shinko Electric Industries Co., Ltd. | (assignment on the face of the patent) | / |
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