Improved mask layout patterns are described for closely spaced primitives in phase shift photolithography masks. In one example, at least a portion of a photolithography mask layout is decomposed into primitives. Jogs are identified from among the primitives, the jogs being characterized by three adjacent corners. E-fields are determined for the identified jogs and are applied to synthesize an electric field at a substrate. The mask layout is corrected using the synthesized electric field and a printed wafer pattern is calculated.
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1. A computer-implemented method comprising:
decomposing at least a portion of a mask layout of a photolithography mask into primitives:
identifying jogs from among the primitives, the identified jogs being characterized by three adjacent corners;
determining electric fields for the identified jogs;
applying the determined electric fields to synthesize an electric field at a substrate;
correcting the mask layout using the synthesized electric field; and
calculating a printed wafer pattern using the corrected mask layout.
12. A phase shift photolithography mask determined by:
decomposing at least a portion of a mask layout of a photolithography mask into primitives;
identifying jogs from among the primitives, the identified jogs being characterized by three adjacent corners;
determining electric fields for the identified jogs;
applying the determined electric fields to synthesize an electric field at a substrate;
correcting the mask layout using the synthesized electric field; and
calculating a printed wafer pattern using the corrected mask layout.
9. A non-transitory computer-readable medium having instructions that, when executed by the computer, cause the computer to perform operations comprising:
decomposing at least a portion of a mask layout of a photolithography mask into primitives;
identifying jogs from among the primitives, the identified jogs being characterized by three adjacent corners;
determining electric fields for the identified jogs;
applying the determined electric fields to synthesize an electric field at a substrate;
correcting the mask layout using the synthesized electric field; and
calculating a printed wafer pattern using the corrected mask layout.
16. A computer-implemented method comprising:
decomposing at least a portion of a mask layout of as photolithography mask into primitives;
identifying types of primitives from among the primitives;
determining electric fields for a specific type of primitive by a factor;
factoring the determined electric field for the specific type of primitive, the factor including a physical dimension related to the specific type of primitive;
applying the determined electric fields to synthesize an electric field at a substrate;
correcting the mask layout using the synthesized electric field; and
calculating a printed wafer pattern using the corrected mask layout.
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This patent application is a U.S. National Phase Application under 35 U.S.C. §371 of International Application No. PCT/US2011/067978, filed Dec. 29, 2011, entitled “IMPROVED MASK LAYOUT PATTERNS FOR CLOSELY SPACED PRIMITIVES IN PHASE SHIFT PHOTOLITHOGRAPHY MASKS”.
The present description relates to the field of mask pattern layout for photolithography and, in particular, to improving mask layout patterns by factoring E-field calculations for determining phase shift masks.
Electronic and micromechanical devices are formed by patterning successive layers on a substrate using lithography. The patterns are formed by applying a layer of photoresist to a surface. Light is then passed through a patterned imaging plate, such as a mask or reticle, to expose the photoresist in patterns that correspond to the desired features on the substrate. A developer is applied and the photoresist is etched away leaving only the features in a pattern corresponding to the pattern on the mask. As the size of the features, such as parts of transistors, decreases, there are more features on the same size mask and the mask designs becomes more complex.
For very small features, phase shift technology (referred to as phase shift masks) is used. In a conventional non-phase shift mask, the light transmitted through adjacent transparent areas of the mask is in phase and the features are large enough that the phase of the light does not significantly affect the amount of light that hits the photoresist. Each transparent area on the mask results in a corresponding exposed area on the photoresist. With very small features, that is when the dimensions of the features are close to the wavelength of the light, diffraction occurs as the light passes through the mask. The light passing through adjacent transparent areas will interfere constructively or destructively, so that in some places on the photoresist the amplitude of the light adds together and on some places of the photoresist that light will cancel itself out. The resulting pattern on the photoresist ends up different from the pattern on the mask.
In a phase shift mask, light transmitted through adjacent features is phase shifted by the mask so that constructive and destructive interference is intentionally used to form the pattern on the photoresist. The mask is a grid of pixels that either block light, transmit light, or transmit light with a phase shift. The intentional use of optical interference gives greater control over the creation of small features. However it makes mask design more complex.
Masks are designed using computer software. For complex mask designs (e.g., the designs of phase shift masks for sub-wavelength features), accurate mask design software is very complex and the calculations may be very slow. As a result, approximations and simplifications are used to estimate the pattern that will be created by a particular mask. The thin mask method uses geometrical optics to calculate the electric field transmitted by light passing through the mask onto the photoresist. The thin mask method ignores light scattering effects due to the shape of particular mask features. There is more than one approach to effectively add thick mask effects to the thin mask method. A boundary layer method modifies the thin mask field in feature edge areas (the so-called boundary layer) to account for some scattering effects. The edge domain decomposition method adds edge scattering corrections to the thin mask field to improve the accuracy. Other methods are also used.
However, actual masks are not thin. Accurately accounting for the effects of the thickness of the mask becomes more important as features become smaller and can allow the mask design to be corrected for increasingly strong scattering effects and aggressive illumination schemes.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Embodiments of the present invention allow for the patterning of sub-wavelength features in chromeless phase shift masks. Higher order correction effects are included. This accounts for strong scattering effects of smaller structures including coupling effects from neighboring features. Embodiments of the invention may be extended to include interactions between edges, corners, jogs, notches and other features.
A typical mask layout has a collection of sub-wavelength features, i.e. features that are smaller than the wavelength of the light used to perform photolithography. The features may be decomposed into geometry entities or primitives such as edges, spaces, corners, and jogs or notches. For each primitive, the scattered electric fields of the photolithography light are calculated using a rigorous simulator and then stored for later use.
The scattered field calculation may be made by first applying previously calculated scattered fields for each primitive. A filtering scheme may then be applied for scattered fields from the jogs or notches. The filtered scattered field may then be used to calculate the printed wafer pattern. This process may be repeated until the printed wafer pattern matches with the target pattern within any particular predefined criteria.
A nomenclature may be applied to the jog primitive so that a first outer corner 123 is labeled jog1, the center corner 125 is labeled corner, and the third corner, the second outer corner 127 is labeled jog2. Electric fields may be calculated for each corner using existing techniques by approximating the two sides of the corner as infinite straight lines. The electric field for jog1, Ejog1, is approximated as an electric field for a corner 123 of two infinite lines 121, 131 that meet at a right angle. Similarly the electric field for corner, Ecorner, is approximated based on the right angle corner of two infinite lines 131, 133 and the electric field for jog2, Ejog2, is approximated using the right angle corner of the last two lines 133, 129 of the jog primitive.
Many rigorous methods exist to estimate a transmitted E-field. For example, in the Finite Difference Time Domain method, the Maxwell equations are replaced by a set of finite difference equations obtained by discretizing the Maxwell equations in space and time. This provides relationships between current states and the states of a subsequent time step. The E-field is then solved by stepping the solutions over time.
Another rigorous method, the Waveguide method, is a frequency domain method in which the simulation area is divided into 2D or 3D rectangular blocks. The material is considered uniform throughout each block so that the Maxwell equations can be solved analytically for each block. Solutions of all blocks are related by boundary conditions, which result in a set of linear algebraic questions that are then solved using matrix methods.
Having determined an E-field value for each of the three corners, the E-field for the jog primitive may be determined. To determine the electric field of the jog primitive these three E values can be combined as the sum of the fields of the two outer corners less the field of the center corner or:
E=Ejog1+Ejog2−Ecorner.
This electric field, E, value may be used in a library to be applied for analyzing fields on a mask and performing any of a number of different corrections. However, for even higher accuracy, the E value may be corrected for the approximations in assuming that the corners had infinite lines. In the Equation, the electric field at the corner is corrected by a factor that includes the length of the longest side of the corner. The equation also modifies the correction factor for process parameters such as α, β and σ. The Equation below shows a more refined E calculation.
In the Equation α, β and σare process parameters that are determined empirically and vary for different photolithography equipment, chemistry, and mask geometries. Ljog1 and Ljog2 are the physical lengths as projected onto a surface of the straight segments 131, 133 on either side of the corner 125 of the jog primitive. Accordingly, the correction factor enclosed within brackets not only accommodates changes in process but also corrects for the actual size of the jog primitive.
A similar approach may be applied to other kinds of features by factoring the normally provided E-field with a factor that takes into account the dimensions of the primitive. The techniques above are not limited to the jogs shown in
As can be seen from the equation the dimensions aspect of the factor is a negative exponent. As a result as the distance increases the resulting value decreases. This shows that the impact of nearby shapes decreases with distance. The E-field correction factor is therefore useful primarily for features that are nearby. The particular distance beyond which the factor is not useful will depend upon the precision desired, the size of the field and the process parameters.
The determined E-fields for jog primitives may be applied to mask layout patterns using a process for photolithography simulation as shown in
At 240, E-fields corresponding to the primitives are obtained. These may be pre-calculated E-fields or they may be retrieved from a library. The scattered fields may be calculated independently or for use in a library using rigorous simulations, prior empirical values and in other ways. For jog primitives, the approaches described above may be used. These fields are then combined at 250 to synthesize a scattered field that would be projected onto a photoresist layer of a substrate during actual photolithography.
At 260, a simulation may be conducted using the synthesized field to determine the features that would be generated by using the estimated mask from 220. The simulated features are compared to the original desired design features at 270 to determine whether the simulated features are sufficiently similar to the desired features that the mask should be used without further modification. If so, the process ends at 280. If not, the mask is modified at 290 to try to generate features that are closer to the desired features. The process then loops back to 230 to analyze the modified mask.
An initial mask is input into the mask manipulator 310 and the mask deconstructor 340 deconstructs the mask into its primitives (e.g., edges, spaces, corners, jogs, etc.). The E-field synthesizer 350 looks up the E-field for each primitive in the library 380 of E-fields and also any pre-calculated E-fields for some primitives and then applies these to the E-field synthesizer. The resulting synthesized field corresponds to the field that would be generated on the photoresist during exposure.
The feature calculator 360 uses the synthesized field to determine the features that would result from the application of the mask. The feature comparator 370 then compares these features with the desired features. The mask manipulator 310 changes the mask to reduce the discrepancy between the desired features and the synthesized features, and the resulting new mask is analyzed in the same way as described above.
The display 330 may show the synthesized field as well as the results of the comparison done by the feature comparator 370. If any user input is required, it may be given using the user input module 320.
Electronic system 600 includes a bus 605 or other communications device to communicate information, and a processor 610 coupled to the bus 605 to process information. While the electronic system 600 is illustrated with a single processor, the electronic system 600 may include multiple processors or co-processors. The electronic system 600 further includes a random access memory (RAM) or other dynamic storage device 620 (referred to as memory), coupled to the bus 605 to store information and instructions to be executed by the processor 610. The memory 620 also may be used to store temporary variables or other intermediate information during execution of instructions by the processor 610.
The electronic system 600 also includes a read only memory (ROM) and/or other static storage device 630 coupled to bus 605 to store static information and instructions for the processor 610. A data storage device 640 is coupled to the bus 605 to store information and instructions.
The electronic system 600 may also be coupled via the bus 605 to a display device 650, such as a light emitting diode (LED) or liquid crystal display (LCD), to display information to a user. An input device 660, including alphanumeric and other keys, is typically coupled to the bus 605 to communicate information and command selections to the processor 610. Another type of user input device is a cursor control 670, such as a mouse, a trackball, or cursor direction keys to communicate direction information and command selections to the processor 610 and to control cursor movement on a display 650. The electronic system 600 further includes a network interface 680, such as a wired network interface 687 or a wireless network interface 685 to provide access to a network, such as a local area network.
Instructions are provided to memory from a storage device, such as magnetic disk, a read-only memory (ROM) integrated circuit, CD-ROM, DVD, via a remote connection (e.g., over a wired or wireless network via the network interface) providing access to one or more electronically-accessible media, etc. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, execution of sequences of instructions is not limited to any specific combination of hardware circuitry and software instructions.
A computer-readable medium includes any mechanism that provides (i.e., stores and/or transmits) content (e.g., computer executable instructions) in a form readable by an electronic device (e.g., a computer, a personal digital assistant, a cellular telephone). For example, a computer-readable medium may include read only memory (ROM), random access memory (RAM), magnetic disk storage media; optical storage media; or flash memory devices, etc.
Methods and apparatuses are described herein with respect to integrated circuit manufacturing; however, the techniques described may be applied to the manufacturing and/or design process of any integrated device. Integrated devices include integrated circuits, micromachines, thin film structures such as disk drive heads, gene chips, micro-electromechanical systems (MEMS), or any other article of manufacture that is manufactured using lithography techniques.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
The above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Hu, Bin, Oh, Chulwoo, Singh, Vivek K., Kim, Sungwon, Yavuz, Mehmet E.
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